Patent Application
20250015764
This application claims priority to foreign French patent application No. FR 2307281, filed on Jul. 7, 2023, the disclosure of which is incorporated by reference in its entirety.
The present invention relates to a multiband Doherty power amplifier. The invention is applicable, in particular, to telecommunications devices which may be used in mobile telephone networks or in Wi-Fi networks.
4G/5G/6G and Wi-Fi 6/6E/7 modern communication standards considerably increase the complexity of RF front-end modules, of which the power amplifier is a critical part, in terms of size and of energy consumption.
Specifically, the need for reduced energy consumption with reduced size and manufacturing cost is pushing research towards multiband power amplifiers with high efficiency and a high level of integration, with strong linearity requirements.
Signals used in 4G/5G/6G and Wi-Fi 6/6E/7 standards have high peak-to-average power ratios (PAPRs) (greater than 4 dB) because, notably, of the presence of a large number of modulated subcarriers in these OFDM communication systems.
With a high PAPR, it is all the more necessary to lower the power level of the power amplifier with respect to the peak power (back-off), in order to meet strict linearity specifications.
More specifically, the power back-off is a power level below the saturation point which makes it possible to make the amplifier operate in a linear zone. Usually, power amplifiers operate close to the saturation point since it is there that the efficiency is maximum. In order to ensure that the amplifier is operating in the linear zone, the power level is lowered from the point of maximum efficiency. The power reduction level is called “power back-off”.
In power amplifiers of the prior art, power reduction considerably degrades the average efficiency of the power amplifier. Thus, besides the fact that the power amplifier must preserve high efficiency despite the power back-off, the power amplifier must also be wideband or multiband in order to cover an increased number of frequency bands.
The Doherty power amplifier is an advantageous solution for efficiently amplifying signals with high PAPRs. The operating principle of the Doherty amplifier is illustrated by
The Doherty power amplifier uses the concept of active (or dynamic) load modulation, wherein the load seen by the main amplifier 2 is modulated by injecting a current from the auxiliary amplifier 3. The main amplifier 2, conventionally operating in class AB, is always active, while the auxiliary amplifier 3, conventionally operating in class C or deep AB, contributes only in the back-off region.
Doherty power amplifiers generally have a limited optimal operating band (fractional band FBW<10%) and require accurate phase control at the impedance matching circuit 6 in order to maintain high performance (efficiency and linearity) over the targeted frequency band.
The operating fractional band is given by the following relationship:
FBW=(Fmax−Fmin)/Fcentral
with Fmin being the minimum frequency of the operating band, Fmax the maximum frequency of the operating band, and Fcentral the centre frequency.
In order to overcome the degradation of the performance of Doherty power amplifiers over a high frequency range, tunable Doherty power amplifier architectures have recently been introduced.
In [2], a Doherty power amplifier architecture having a widened frequency band (1.55-2.3 GHZ) comprises several tunable capacitors. The amplifier requires the use of an (external) digital pre-distortion technique, in order to maintain the linearity level required over the whole frequency band, which damages the energy efficiency of the system.
In [3], an alternative Doherty power amplifier architecture has linear behaviour over the 1.9 GHZ-2.7 GHz band without requiring a digital pre-distortion technique. The amplifier comprises tunable capacitors integrated on SOI-CMOS, which improves the linearity in frequency. However, the operating band FBW remains less than 25%.
There is therefore a need to provide a linear Doherty power amplifier having an improved fractional operating band FBW, and not using a digital pre-distortion technique.
One subject of the invention is therefore a Doherty amplifier as defined according to claims 1 to 5.
Other features, details and advantages of the invention will become apparent on reading the description given with reference to the appended drawings, which are given by way of example.
The Doherty amplifier according to the invention is illustrated by
The input port PE receives the input RF signal RFIN to be amplified. A pre-amplification stage PRA makes it possible to amplify the input RF signal RFIN, so as to generate an intermediate signal SI, in order to increase the overall gain of the Doherty amplifier.
A common network RCO, which comprises a switch SW, is connected at the output of the pre-amplification stage PRA. The common network RCO is also connected to a high-band amplification pathway VAHB and to a low-band amplification pathway VALB. The switch SW may selectively activate the high-band amplification pathway VAHB or the low-band amplification pathway VALB in accordance with the carrier frequency of the input RF signal. The Doherty amplifier also comprises external means for controlling the bias signals for the transistors according to whether the high-band amplification pathway VAHB or the low-band amplification pathway VALB is selected.
To this end, the switch SW comprises an input terminal BE, connected to the pre-amplification stage PRA, and two output terminals. One output terminal BS1 is connected to the high-band amplification pathway VAHB, and one output terminal BS2 is connected to the low-band amplification pathway VALB. One example of a switch which may be used is an SPDT (single-pole double-throw) switch with one input and two outputs.
One or other of the amplification pathways of the Doherty amplifier is selected automatically in accordance with the knowledge of the carrier frequency of the signal to be amplified.
For example, the amplification pathways may be switched between dynamically, that is to say when the Doherty amplifier is in use. According to another embodiment, the Doherty amplifier, integrated into a telecommunications device (for example a base station or a user terminal), may control the switching between the amplification pathways in accordance with the movement of the user and/or with the changing of cell by the user.
The switch from one amplification pathway to the other may be controlled by a control device (not shown in the figures).
The high-band amplification pathway VAHB is adapted to amplify the intermediate signal, the operating frequency band of which is located in a frequency band referred to as the upper frequency band. According to the operating principle of the Doherty amplifier recalled above, the high-band amplification pathway VAHB comprises a main amplifier APHB operating in class AB, and an auxiliary amplifier AAHB operating in the class C or deep AB. Moreover, the high-band amplification pathway VAHB comprises an output impedance matching network OMNHB connected to the main amplifier APHB, to the auxiliary amplifier AAHB and to the output port PS1 at which the amplified signal is extracted. The signals originating from the main amplifier and auxiliary amplifier are recombined at the node A.
The main/auxiliary amplifier may be composed of a transistor (LDMOS transistor in
Advantageously, the main amplifier and the auxiliary amplifier of each pathway comprise LDMOS (laterally-diffused metal-oxide-semiconductor) transistors, which offer a high breakdown voltage (greater than 10 volts), which is necessary for applications requiring high output powers (>1 W) such as mobile telephones or telecommunications base stations. Other technologies may be envisaged for the transistors of the power stage, notably MOS+MOS or MOS+LDMOS stacked transistors, BiCMOS or indeed GaAs, GaN or InP transistors.
According to one embodiment, the output of the main amplifier APHB (drain of the transistor) is connected to the output of the auxiliary amplifier AAHB (drain of the transistor) by means of an impedance inverter such as a pi network with localized elements which is equivalent to a quarter-wavelength line. The impedance inverter is composed of a capacitor Cinvm1 connected between the output of the main amplifier APHB and ground, of a capacitor Cinva1 connected between the output of the auxiliary amplifier AAHB and ground, and of a coil Linv1 connecting the two outputs of the main amplifier APHB and of the auxiliary amplifier AAHB.
The output combiner may adopt a different topology, such as a topology described in [4].
The capacitors Cinvm1 and Cinva1 and the coil Linv1 are sized so that the characteristic impedance Zc of the impedance inverter is equal to Zc=2×Zopt, with Zopt being the optimal load impedance at the node A, which corresponds to the output of the auxiliary amplifier AAHB.
The output network OMNHB comprises a coil LSUPM1 connected between the external power supply voltage source Vdd of the main amplifier APHB and the output of the main amplifier APHB. Likewise, a coil LSUPA1 is connected between the external power supply voltage source Vdd2 of the auxiliary amplifier AAHB and the node A.
A controllable resonant network, composed of a coil LH2o1 and of a variable capacitor CH2o1, is connected between the node A and ground. This resonant network constitutes a controllable harmonic termination which is used to improve the rejection of the second harmonic with respect to the fundamental frequency.
The LC filter composed of a coil LSO1, of a capacitor CSO1, of the capacitor CPO1 and of the coil Lpo1 is part of the network for matching output to the fundamental frequency.
The low-band amplification pathway VALB is adapted to amplify the intermediate signal, the operating frequency band of which is located in a frequency band referred to as the lower frequency band. It comprises an output impedance matching network OMNLB of the low-band amplification pathway which may be identical (but not necessarily) to the output impedance matching network OMNHB of the high-band amplification pathway, the sizing of the components being able to be different from one pathway to the other.
The Doherty amplifier comprises an output port PS1 for the high-band amplification pathway VAHB and an output port PS2 for the low-band amplification pathway VALB. The output port PS1 of the high-band amplification pathway VAHB may be connected to an antenna or to an antenna select switch, and the output port PS2 of the low-band amplification pathway VALB may be connected to a different antenna or to an antenna select switch.
The upper frequency band and the lower frequency band are preferably disjoint. For example, the components of the high-band amplification pathway VAHB may be sized in order to amplify the input signal in the 2.1-2.7 GHz operating band, while the components of the low-band amplification pathway VALB may be sized in order to amplify the input signal in the 1.7-2.1 GHz operating band.
The Doherty amplifier according to the invention comprises an intermediate impedance matching network ISMN2, connected between the pre-amplification stage PRA and each of the main amplifiers (APHB, APLB) and auxiliary amplifiers (AAHB, AALB). The intermediate impedance matching network ISMN2 makes it possible to present an optimal source impedance to each of the amplifiers. It is advantageously distributed between the common network RCO, the high-band amplification pathway VAHB and the low-band amplification pathway VALB. Thus, some of the components of the intermediate impedance matching network ISMN2 are part of the common network RCO, while other components of the intermediate impedance matching network ISMN2 are part of the high-band amplification pathway VAHB and of the low-band amplification pathway VALB.
The design of the intermediate impedance matching network ISMN2 is a critical aspect in order to obtain good RF performance for the Doherty amplifier. Specifically, it must present both an optimal source impedance for the output stages and an optimal load impedance for the pre-amplification stage.
The fact that some of the components of the intermediate impedance matching network ISMN2 are part of the common network RCO, between the pre-amplification stage PRA and the switch SW, makes it possible to reduce the size of the chip on which the Doherty amplifier is etched.
Thus, the power divider stage, which makes it possible to distribute the power of the signal between the main amplifier APHB and the auxiliary amplifier AAHB, comprises a first resonant circuit LC1 arranged in the common network RCO, a second resonant circuit RC2 arranged in the high-band amplification pathway VAHB, and a third resonant circuit RC3 arranged in the low-band amplification pathway VALB.
The first resonant circuit LC1 comprises a capacitor CCD connected between the output of the pre-amplification stage PRA and the input terminal of the switch SW, and an inductor Ldiv connected between the input terminal of the switch SW and ground.
The second resonant circuit RC2 comprises two capacitors (Cdiv11, Cdiv12) connected in parallel across the resistor Rdiv1. The two capacitors are connected to the output terminal of the switch SW which activates the high-band amplification pathway VAHB. The capacitor Cdiv11 is on the branch of the main amplifier APHB, and the capacitor Cdiv12 is on the branch of the auxiliary amplifier AAHB. An inductor Lpa1 is connected between the capacitor Cdiv12 and ground. The resistor Rdiv1 connects the capacitors (Cdiv11, Cdiv12) connected in parallel. The resistor Rdiv1 may be a variable resistor, in order to adjust the amplitude and the phase on the high-band amplification pathway VAHB.
The shared inductor Ldiv thus forms a modified Wilkinson divider with the capacitors Cdiv11 and Cdiv12 and the resistor Rdiv1 when the high-band amplification pathway VAHB is activated and with the capacitors Cdiv21 and Cdiv22 and the resistor Rdiv2 when the low-band amplification pathway VALB is activated.
The third resonant circuit RC3 comprises two capacitors (Cdiv21, Cdiv22) connected in parallel across the resistor Rdiv2. The two capacitors are connected to the output terminal of the switch SW which activates the low-band amplification pathway VALB. The resistor Rdiv2 connects the capacitors (Cdiv21, Cdiv22) connected in parallel.
According to one embodiment of the invention, in the high-band amplification pathway VAHB, a first tunable resonant network RRA1HB is connected to the gate of the main amplifier APHB and configured to introduce a predefined first phase shift ϕm. To this end, the first tunable resonant network RRA1HB comprises an inductor Lpm1, connected between the second resonant circuit RC2 and ground, and a variable capacitor Csm1 connected between the second resonant circuit RC2 and the gate of the main amplifier APHB.
Likewise, in the high-band amplification pathway VAHB, a second tunable resonant network RRA2HB is connected to the gate of the auxiliary amplifier AAHB and configured to introduce a predefined second phase shift a. To this end, the second tunable resonant network RRA2HB comprises an inductor Lpa1, connected between a node B1 and ground. The node B1 connects the second resonant circuit RC2 to the gate of the auxiliary amplifier AAHB via a variable capacitor Csa1 placed in series with an inductor Lsa1. A capacitor Cpa1 is connected between an intermediate point, situated between the variable capacitor Csa1 and the inductor Lsa1, and ground.
The first tunable resonant network RRA1HB is sized and controlled so that it presents the optimal source impedance to the main amplifier APHB while at the same time introducing the predefined first phase shift ϕm. Likewise, the second tunable resonant network RRA2HB is sized and controlled so that it presents the optimal source impedance to the auxiliary amplifier AAHB while at the same time introducing the predefined second phase shift ϕa.
In the low-band amplification pathway VALB, a first tunable resonant network RRA1LB is identical to the first resonant network RRA1HB of the high-band amplification network VAHB. The first tunable resonant network RRA1LB introduces a predefined first phase shift ϕm.
In the low-band amplification pathway VALB, a second tunable resonant network RRA2LB is connected to the gate of the auxiliary amplifier AALB and configured to introduce a predefined second phase shift Da to the RF signal. To this end, the second tunable resonant network RRA2LB comprises a variable capacitor Csa2 placed in series with an inductor Lsa2. A capacitor Cpa2 is connected between an intermediate point, situated between the variable capacitor Csa2 and the inductor Lsa2, and ground.
According to one particularly advantageous embodiment, the second tunable resonant network RRA2LB of the low-band amplification pathway VALB does not comprise an inductor connected between the node B2 and ground. The second tunable resonant network RRA2LB of the low-band amplification pathway VALB thus comprises one inductor (or coil) fewer than the second tunable resonant network RRA2HB of the high-band amplification pathway VAHB.
Specifically, the switch SW does not offer perfect isolation between the high-band amplification pathway VAHB and the low-band amplification pathway VALB. When the low-band amplification pathway VALB is activated, the intermediate impedance matching network ISMN2 is capable of forming the impedance and phase level required, taking account of the parasites of the inactive path (that is to say of the high-band amplification pathway VAHB). The variable capacitors of the amplification pathways and the bias voltages of the transistors may also be adjusted so that performance is optimized in accordance with the targeted frequency. The resistor Rdiv2 of the third resonant circuit RC3 may be a variable resistor, which makes it possible to adjust the amplitude and phase levels required, taking account of the parasites of the inactive path.
Thus, the parasitic impedance of the high-band amplification pathway VAHB makes it possible to do without an additional bulky inductor in the second tunable resonant network RRA2LB of the low-band amplification pathway VALB.
This is particularly advantageous for a use of the Doherty amplifier in applications which are constrained in size such as mobile telephones, smart objects or small cells.
In the high-band amplification pathway VAHB and in the low-band amplification pathway VALB, the value of the first phase shift ϕm and the value of the second phase shift ϕa are determined so that their difference has a predefined value in the back-off region of the main amplifier (APHB, APLB) and of the auxiliary amplifier (AAHB, AALB).
The phase difference ϕdiff=ϕm−ϕa is optimized in order to ensure optimal load modulation and power combination, at the node A, in the back-off region (ϕdiff is substantially equal to 90° in theory). At a given frequency, the difference ϕdiff depends on the power because of the non-linearity of the input impedances of the main amplifier and of the auxiliary amplifier. These input impedances, as well as the transfer function of the intermediate impedance matching networks, vary in accordance with the frequency. These effects lead to variation of ϕdiff and degrade the performance of the Doherty amplifier. In order to avoid such degradation, ϕdiff is optimized and readjusted in the back-off zone (typical back-off value of 4 to 8 dB for mobile applications).
In each of the amplification pathways, the baseband impedances at the gate and at the drain of the main amplifier and of the auxiliary amplifier introduce a memory effect and cause degradation of the linearity performance. In order to attenuate this effect, the main amplifier and the auxiliary amplifier are biased via a parallel LC resonator (Ltank11−Ctank11, Ltank12−Ctank12, Ltank21−Ctank21, Ltank22−Ctank22) connected to the gate of the transistors.
According to one embodiment, the pre-amplification stage PRA (or driver) comprises two stages connected in a cascade, with a first amplifier stage DRV1 and a second amplifier stage DRV2 (which is connected to an external power supply source via an inductor Lsupd), in order to maintain a high power gain (typically of the order of 30 dB) for all the high- and low-band operating frequencies (a power gain of 30 dB or more may be obtained with two pre-amplification stages, against less than 30 dB with a single pre-amplification stage). Specifically, when the high-band amplification pathway VAHB is activated, the power gain may be reduced, because of the intrinsic gain characteristics of the transistors (for a given output power and therefore transistor size).
The second amplifier DRV2 is connected directly to the intermediate impedance matching network ISMN2, in particular to the capacitor CCD of the common network RCO.
The first amplifier DRV1 and/or the second amplifier DRV2 advantageously comprise a common-gate transistor (T11, T12) and a common-source transistor (T21, T22), in a cascode configuration. This topology makes it possible to maximize the overall gain of the Doherty amplifier.
In the first stage DRV1 and in the second stage DRV2, a MOS transistor (for example, a body-contact MOS (BC-MOS) transistor using SOI technology) may be used for the common-source transistor (T21 and T22), and an LDMOS transistor may be used for the common-gate transistor (T11 and T12). This embodiment is not, however, exclusive, and using the LDMOS transistor for all the transistors of the pre-amplification stage PRA may be envisaged.
It is also possible to envisage other types of transistors or combinations of transistors.
The pre-amplification stage PRA also comprises an input impedance matching network IMN configured to match the input impedance of the first stage DRV1 to a predefined source impedance value (conventionally 50 ohms). For this purpose, a capacitor C10, connected to the input port PE, is connected to the gate of the common source T21 via a capacitor C15. An inductor L11 is connected between an intermediate point, situated between the two capacitors, and ground. The gate of the common source T21 is biased via a resistor R14. The common gate T11 is biased via a resistor R12. A capacitor C13 is connected between the resistor R12 and ground.
Analogously, the pre-amplification stage PRA comprises a second impedance matching network ISMN1 connected between the first stage DRV1 and the second stage DRV2 (inductors L16 and Lp2, resistor R19 and capacitors C17 and C18 connected similarly to the components of the input impedance matching network IMN).
The second impedance matching network ISMN1 may comprise a second-harmonic filter PSH, connected between the gate of the common source T22 and ground. The second-harmonic filter PSH comprises an inductor LH2i in series with a capacitor CH2i, which may be controllable in order to control the second-harmonic impedance with respect to the carrier frequency.
Connecting the first amplifier DRV1 and the second amplifier DRV2 in a cascade may result in instabilities. In order to guarantee stability of the first stage DRV1, a feedback circuit CRE comprising a capacitor C21 and a variable resistor R20 in series is connected between the drain of the common-gate transistor T11 and the gate of the common-source transistor T21.
The value of the variable resistor R20 is controlled in accordance with the amplification pathway selected.
According to one embodiment of the invention, it is also possible to use only a single amplification stage DRV, as
According to one embodiment (using SOI technology), each of the variable capacitors used in the Doherty amplifier is composed of a fixed-value capacitor, of a set of coarse-control capacitors and of a set of fine-control capacitors, connected in parallel. The set of coarse-control capacitors and the set of fine-control capacitors is composed of several branches of variable capacitors, each capacitor being connected to a stack of transistors in order to weight the value of the coarse control or of the fine control.
The quality factor (Q) of the variable capacitor defines the control range TR (ratio between maximum and minimum capacitance value), and the voltage value at the terminals of the capacitor determines the number (N) of stacked transistors as well as the gate width (Wg) of the transistors. Several transistors are stacked in order to withstand the maximum voltage level in the OFF state.
There are other ways of producing the variable capacitors in accordance with the integration technology under consideration (RF-MEMS or BST technologies, for example).
According to the simulations of the power-added efficiency PAE, the Doherty amplifier makes it possible to maintain high efficiency and, according to the curves of the AM/AM and AM/PM characteristics, very good linearity is obtained over the 1.7-2.7 GHz frequency range.
The performance of the Doherty amplifier according to the invention may also be characterized using a figure of merit FOM defined by the following relationship:
FOM=PAE+|ACLR|
ACLR (for “adjacent channel leakage power ratio”) is defined as the ratio of the filtered average power centred on the attributed channel frequency to the filtered average power centred on an adjacent-channel frequency.
The power-added efficiency PAE makes it possible to correctly characterize energy efficiency, while the filtered average power ratio ACLR makes it possible to correctly characterize linearity in the presence of an amplitude- and phase-modulated transmission signal.
The following table also illustrates the very good performance, in terms of efficiency and in terms of linearity, of the Doherty amplifier according to the invention (ACLR measured for the LTE wireless communication standard, E-UTRA (for “Evolved Universal Terrestrial Radio Access”)).
Thus, the Doherty amplifier makes it possible to obtain a factor of merit FOM greater than 75 over the whole 1.7-2.7 GHz band, providing an output power Pout equal to 28 dBm, without using digital pre-distortion.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2307281 | Jul 2023 | FR | national |
