This application claims priority to European Application 20214956.3, filed on Dec. 17, 2020. The content of this earlier filed application is incorporated by reference herein in its entirety.
Examples relate to concepts for patch antennas and particular to a method for forming a multiband patch antenna.
The usage of a dual polarized and dual band antenna may depend on several aspects of the antenna. For example, a wide impedance bandwidth in both the frequency bands, low cross-polarization or a better port-to-port isolation, just to name a few, may be important for a design of an antenna. Therefore, an antenna with matching characteristics may be desired.
Some examples of apparatuses and/or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which
Parameter to characterize a dual polarized and dual band antenna may be e.g., a wide impedance bandwidth in both the frequency bands, low cross-polarization, a better port-to-port isolation, directional radiation pattern without beam squint, high gain with good efficiency and/or a compact size, just to name a few. Available antenna designs may not meet above mentioned requirements in a single antenna. The antenna proposed herein may meet a plurality of mentioned parameters.
The patch antenna proposed herein may cover new radio (NR) FR2 bands, e.g., n257 (26.5 GHz-29.5 GHz), n258 (24.25 GHz-27.5 GHz), n261 (27.25 GHz-28.35 GHz) and
n260 (37 GHz-40 GHz). There has been prior work on design of antennas for 5G millimeter-Wave (mm Wave) since the first 5G specification was released by 3GPP. For example,
The design of a 2×4 array single-polarized dual-band slotted-patch antenna for 28 GHz and 38 GHz is described in (A). Though dual-band frequency response is achieved in Ref. (A) but it has very narrow bandwidth of 1.2 GHz and 1.5 GHz at 28 GHz and 38 GHz, respectively. In reference (B) an 8×8 patch antenna array having dual-linear polarized and spatial diversity is discussed for 28 GHz. The design has a pair of dual-linearly polarized patch antenna on multilayer substrate with a common ground layer. Stacked-patch antenna design approach for 28 GHz is used in (C) with 5 GHz impedance bandwidth and in (G) with 6 GHz impedance bandwidth. But the drawback in both the designs are that the antennas are only single polarized. Circularly polarized dual-band antennas for 28 GHz and 38 GHz using a single feed are discussed in (D), €. The beam squint issue in the radiation pattern is seen in €. A multi-layered dual-polarized antenna having a bandwidth of 2 GHz at 28 GHz is discussed in (F). SIW based dual-band antenna for 28 GHz and 38 GHz is discussed in (H) but it does not have dual-polarization. Polarization diversity can be achieved by physical placements of the antenna, but this would increase the number of antennas as compared to dual-polarized antenna thus taking up more space and increasing the costs and size.
Various examples will now be described more fully with reference to the accompanying drawings in which some examples are illustrated. In the figures, the thicknesses of lines, layers and/or regions may be exaggerated for clarity.
Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and will subsequently be described in detail. However, this detailed description does not limit further examples to the particular forms described. Further examples may cover all modifications, equivalents, and alternatives falling within the scope of the disclosure. Like numbers refer to like or similar elements throughout the description of the figures, which may be implemented identically or in modified form when compared to one another while providing for the same or a similar functionality.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an “or”, this is to be understood to disclose all possible combinations, i.e. only A, only B as well as A and B. An alternative wording for the same combinations is “at least one of the group A and B”. The same applies for combinations of more than 2 Elements.
The terminology used herein for the purpose of describing particular examples is not intended to be limiting for further examples. Whenever a singular form such as “a,” “an” and “the” is used and using only a single element is neither explicitly or implicitly defined as being mandatory, further examples may also use plural elements to implement the same functionality. Likewise, when a functionality is subsequently described as being implemented using multiple elements, further examples may implement the same functionality using a single element or processing entity. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used, specify the presence of the stated features, integers, steps, operations, processes, acts, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components and/or any group thereof.
Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their ordinary meaning of the art to which the examples belong.
An excitation patch may be an element to excite a material to radiate a signal. A radiation characteristic of an excitation patch may depend on a dimension of the excitation patch. The first excitation patch 20 may have a different dimension as the second excitation patch 22. Therefore, by using two different excitation patches a radiation characteristic may be improved. For example, the first radiation patch may have an impedance matching for a frequency of at least 22 GHz, at least 24 GHz or at least 26 GHz and/or for a frequency of at most 30 GHZ or at most 28 GHz. For example, the second radiation patch may have an impedance matching for a frequency of at least 34 GHz, at least 36 GHz or at least 38 GHz and/or for a frequency of at most 42 GHZ, at most 40 GHz or at most 39 GHz. Therefore, a proposed multiband patch antenna 10 may have an impedance matching for two frequencies and/or over a broader frequency range.
A feeding patch 24 may be an element to excite the excitation patches 20, 22. The feeding patch 24 may be used to proximity feed the first excitation patch 20 and the second excitation patch 22 simultaneously. An excitation of the excitation patches 20, 22 may belong to an arrangement of the feeding patch 24 with respect to the excitation patches 20, 22. For example, a feeding patch 24 arrangement between the first excitation patch 20 and the second excitation patch 24 may excite both excitation patches 20, 22 equally. Therefore, a return loss characteristic of a multiband patch antenna 10 formed by two excitation patches 20, 22 may depend on an arrangement of the feeding patch 24 (see also
For example, a proposed patch antenna 10 design may be a combination of an inner excitation patch 22 (second excitation patch) and an outer excitation patch 20 (first excitation patch), both the patches may be fed using another smaller circular feeding patch 24. The smaller circular feeding patch may couple proximately with the inner excitation patch 22 and the outer excitation patch 20.
In comparison to an aperture coupled antenna front to back ratio (FBR), gain and antenna efficiency may be improved by the proposed patch antenna 10. In comparison to dipole antenna, which may be single polarized antenna and for dual polarization, two dipoles antennas are required, the proposed patch antenna 10 may decrease an overall size of an antenna arrangement. In comparison to a dielectric resonator antenna a height to achieve a bandwidth may be decreased by the proposed patch antenna 10. In comparison to a substrate integrated waveguide antenna the proposed patch antenna 10 may improve a bandwidth.
The feeding patch 24 may be arranged between the first excitation patch 20 and the second excitation patch 22. Thus, an excitation of the first 20 and the second excitation patch 22 may be improved by only one feeding patch 24. For example, the first 20 and the second excitation patch 22 may be excited with the same intensity by the feeding patch 24.
The second excitation patch may be enclosed by the first excitation patch. By enclosing the second excitation patch by the first excitation patch, a radiation characteristic of both patches may be adjustable, because both patches may interact in a desired way. For example, a center of the second excitation patch 24 may be arranged at a center of the first excitation patch 22. Therefore, the manufacturing process and/or the feeding may be improved and/or simplified.
The separation gap Gp between the first excitation patch 20 and the second excitation patch 22 may influence the impedance matching, e.g., for higher frequencies such a 39 GHz (see
More details and aspects are mentioned in connection with the examples described below. The example shown in
The excitation of the first and the second excitation patch with one feeding patch simultaneously, may improve and/or facilitate a manufacturing process. Therefore, a manufacturing process of a multiband patch antenna with desired characteristics may be simplified.
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
The parasitic patch 511 may be placed over the example of the antenna described above in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
Thus, an antenna gain and a beam squint issue may be not negative influenced by the parasitic patch.
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
The feeding patch 924 and the second feeding patch 944 are arranged on opposite edges of the second excitation patch 922. Due to a symmetric of antenna 900 a beam squint may be reduced. Optionally, a first phase for feeding the feeding patch 920 may have a phase difference to a second phase for feeding the second feeding patch 944. For example, the second feeding patch 944 may have be fed with a phase difference of 180° in comparison to a phase of the first feeding patch 924. Thus, a balanced feed may be achieved and a beam squint may be further reduced.
The patch antenna may comprise a first feeding network for the feeding patch 924 and the second feeding patch 944, wherein the first feeding network may be a balanced feeding network. The balanced feeding network may have a phase difference of 180°. Due to a symmetric of antenna 900 a beam squint may be reduced.
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
In
In
The main lobe direction for the E-plane (1140a, 1140c, 1140e) may shift to the broadside direction for an increasing phase difference. The main lobe direction for the H-plane (1140b, 1140d, 1140f) also may shift for an increasing phase difference towards the broadside direction.
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
In
The main lobe magnitude increases for an increasing phase difference. The main lobe magnitude is summarized in Tab. 1 for the
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
For the second minima at higher frequency an impact of the width of the separation gap may be less important as for the first minima. Further, there may be no trend in a change of the return loss characteristic for an increasing width of the separation gap. For Gp=30 μm (1320) the second minima may shift to higher frequency in comparison to Gp=10 μm (1310) and for Gp=50 μm (1330) the second minima may shift to lower frequency in comparison to graph 1310. Also, for a change of the bandwidth at the second minima there may be no trend in a change of the return loss characteristic perceptible. Thus, a decreasing of the separation gap may improve a return loss characteristic for the first minima without deteriorating the return loss characteristic for the second minima.
For example, a similar effect can be seen at
Therefore, there may be a trade-off between the total efficiency for the first minima, caused by the first excitation patch and the second minima, caused by the second excitation patch. So, a desired design for the separation gap may depend on a case of application. A return loss characteristic of an antenna proposed above may be chosen in a desired way by adjusting the separation gap between the first and the second excitation patch.
A distance between the first excitation patch and the second excitation patch may be at most 16 μm, at most 14 μm, at most 12 μm or at most 10 μm.
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
The S11-parameter is shown in
For example, a similar effect can be seen at
Furthermore, there may be a trade-off between the total efficiency (impedance matching) for the first minima, and the bandwidth of the first minima. So, a desired design for the feeding gap may depend on a case of application. A return loss characteristic of an antenna proposed above may be chosen by adjusting the feeding gap between the first and the second excitation patch.
A distance between the feeding patch and the first excitation patch and/or the second excitation patch may be at least 70 μm, at least 80 μm, at least 90 μm, or at least 100 μm.
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
The S11-parameter is shown in
For example, a similar effect can be seen at
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
Further the patch antenna 1700 may comprise a plurality of dielectric layers 1790, 1791, 1792, 1793, e.g., made of Rogers RT 5880 with εr=2.2 (relative permittivity) and Dielectric loss=0.0009. A thickness of a dielectric layer 1790 may be at least 0.224 mm, at least 0.234 mm or at least 0.244 mm and/or at most 0.274 mm, at most 2.64 mm or at most 2.54 mm. A thickness of a dielectric layer 1791 may be at least 0.9 mm, at least 0.95 mm or at least 1 mm and/or at most 1.1 mm, at most 1.05 mm or at most 1.016 mm. A thickness of a dielectric layer 1792 may be at least 0.115 mm, at least 0.12 mm or at least 0.125 mm and/or at most 0.135 mm, at most 0.13 mm or at most 0.127 mm. A thickness of a dielectric layer 1793 may be at least 0.115 mm, at least 0.12 mm or at least 0.125 mm and/or at most 0.135 mm, at most 0.13 mm or at most 0.127 mm. A return loss characteristic may depend on a thickness of the pluralities of dielectric layers, especially on the dielectric layer 1790. For example, a thickness of the dielectric layer 1790 may improve a return loss characteristic of the patch antenna 1700.
The antenna design of the patch antenna 1700 shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
The ground layer (e.g., L4) may be arranged in a first layer of a printed circuit board the excitation layer (e.g., L3) may be arranged in a second layer of the printed circuit board and the parasitic patch may be arranged in a third layer (e.g., L1) of the printed circuit board, wherein the second layer of the printed circuit board may be arranged between the first layer and third layer of the printed circuit board.
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
The feeding patches 1924, 1964, 1944, 1984 are arranged between the first excitation patch 1920 and the second excitation patch 1922 such that the feeding patches 1924, 1964, 1944, 1984 may have coupling to both the excitation patches 1920, 1922. The first feeding patch 1924 may be excited by equal amplitude and a 180° phase shift signal compared to the second feeding patch 1944 (ΔΦ=180°). In the similar way the third feeding patch 1964 may have an equal amplitude and 180° phase shift signal compared to fourth feeding patch 1984 (ΔΦ=180°).
The multiband patch antenna may further comprise a third feeding patch 1964 and a fourth feeding patch 1984, as shown in
The patch antenna may further comprise a second feeding network for the third feeding patch 1964 and the fourth feeding 1984 patch, wherein the second feeding network may be a balanced feeding network. The balanced feeding network may have a phase difference of 180°. Due to a symmetric of the antenna a beam squint may be reduced.
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
The main lobe magnitude in
The main lobe magnitude in
A beam tilt of ˜10° can be observed for co-polarization for Φ=0° for port1 (see graph 2610a) and for Φ=90° for port2 (see graph 2630b). The small beam tilt may be caused by a delay line used for a first feeding network. Thus, by adjusting a parameter of the first feeding network a radiation characteristic of the patch antenna may be improved.
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
The main lobe magnitude in
The main lobe magnitude in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and/or below. The example shown in
More details and aspects are mentioned in connection with the examples described above and. The example shown in
The proposed patch antenna may be a combination of an inner patch (second excitation patch) and an outer patch (first excitation patch), both the patches are fed using another smaller circular patch (feeding patch), which couples proximately with the inner and outer patches. When only one excitation patch may be used for the proposed patch antenna design, a beam squint issue may be observed. The proposed dual-excitation technique improves a symmetry of the antenna structure, which may reduce a beam squint issue. A balanced feeding network may improve a yield maximum radiation in the broadside. A parasitic patch added in an upper layer of the patch antenna may enhance an impedance bandwidth of the bands. Further, the concept may be extended for the design of dual-polarized antenna by adding the balanced feed orthogonally. The proposed patch antenna may be scalable for any frequency. The proposed patch antenna may help to achieve a compact, wideband, high gain and high efficiency patch antenna for 5G mm-wave RFM. This will be suitable to integrate in advanced 5G mobility systems with better performance.
An electronic device, e.g., a mobile device, may comprise a proposed multiband patch antenna.
In some aspects, application processor 3105 may include, for example, one or more CPU cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as serial peripheral interface (SPI), inter-integrated circuit (I2C) or universal programmable serial interface module, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose input-output (IO), memory card controllers such as secure digital/multi-media card (SD/MMC) or similar, universal serial bus (USB) interfaces, mobile industry processor interface (MIPI) interfaces and Joint Test Access Group (JTAG) test access ports.
In some aspects, baseband module 3110 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and/or a multi-chip module containing two or more integrated circuits.
In some aspects, application processor 3205 may include one or more CPU cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface module, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose IO, memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces and Joint Test Access Group (JTAG) test access ports.
In some aspects, baseband processor 3210 may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip module containing two or more integrated circuits.
In some aspects, memory 3220 may include one or more of volatile memory including dynamic random access memory (DRAM) and/or synchronous dynamic random access memory (SDRAM), and nonvolatile memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM) and/or a three-dimensional crosspoint memory. Memory 3220 may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.
In some aspects, power management integrated circuitry 3225 may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions.
In some aspects, power tee circuitry 3230 may provide for electrical power drawn from a network cable to provide both power supply and data connectivity to the base station radio head 3200 using a single cable.
In some aspects, network controller 3235 may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless.
In some aspects, satellite navigation receiver module 3245 may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the global positioning system (GPS), Globalnaya Navigatsionnaya Sputnikovaya Sistema (GLONASS), Galileo and/or BeiDou. The receiver 3245 may provide data to application processor 3205 which may include one or more of position data or time data. Application processor 3205 may use time data to synchronize operations with other radio base stations.
In some aspects, user interface 3250 may include one or more of physical or virtual buttons, such as a reset button, one or more indicators such as light emitting diodes (LEDs) and a display screen.
Millimeter wave communication circuitry 3300 may include protocol processing circuitry 3305, which may implement one or more of medium access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), radio resource control (RRC) and non-access stratum (NAS) functions. Protocol processing circuitry 3305 may include one or more processing cores (not shown) to execute instructions and one or more memory structures (not shown) to store program and data information.
Millimeter wave communication circuitry 3300 may further include digital baseband circuitry 3310, which may implement physical layer (PHY) functions including one or more of hybrid automatic repeat request (HARD) functions, scrambling and/or descrambling, coding and/or decoding, layer mapping and/or de-mapping, modulation symbol mapping, received symbol and/or bit metric determination, multi-antenna port pre-coding and/or decoding which may include one or more of space-time, space-frequency or spatial coding, reference signal generation and/or detection, preamble sequence generation and/or decoding, synchronization sequence generation and/or detection, control channel signal blind decoding, and other related functions.
Millimeter wave communication circuitry 3300 may further include transmit circuitry 3315, receive circuitry 3320 and/or antenna array circuitry 3330.
Millimeter wave communication circuitry 3300 may further include radio frequency (RF) circuitry 3325. In an aspect of the invention, RF circuitry 3325 may include multiple parallel RF chains for one or more of transmit or receive functions, each connected to one or more antennas of the antenna array 3330.
In an aspect of the disclosure, protocol processing circuitry 3305 may include one or more instances of control circuitry (not shown) to provide control functions for one or more of digital baseband circuitry 3310, transmit circuitry 3315, receive circuitry 3320, and/or radio frequency circuitry 3325.
The exemplary transmit circuitry 3315 of
Radio frequency circuitry 3325 may include one or more instances of radio chain circuitry 3372, which in some aspects may include one or more filters, power amplifiers, low noise amplifiers, programmable phase shifters and power supplies (not shown).
Radio frequency circuitry 3325 may include power combining and dividing circuitry 3374 in some aspects. In some aspects, power combining and dividing circuitry 3374 may operate bidirectionally, such that the same physical circuitry may be configured to operate as a power divider when the device is transmitting, and as a power combiner when the device is receiving. In some aspects, power combining and dividing circuitry 3374 may one or more include wholly or partially separate circuitries to perform power dividing when the device is transmitting and power combining when the device is receiving. In some aspects, power combining and dividing circuitry 3374 may include passive circuitry comprising one or more two-way power divider/combiners arranged in a tree. In some aspects, power combining and dividing circuitry 3374 may include active circuitry comprising amplifier circuits.
In some aspects, radio frequency circuitry 3325 may connect to transmit circuitry 3315 and receive circuitry 3320 in
In some aspects, one or more radio chain interfaces 3376 may provide one or more interfaces to one or more receive or transmit signals, each associated with a single antenna structure which may comprise one or more antennas.
In some aspects, the combined radio chain interface 3378 may provide a single interface to one or more receive or transmit signals, each associated with a group of antenna structures comprising one or more antennas.
In some aspects, the one or more parallel receive circuitry 3382 and one or more combined receive circuitry 3384 may include one or more Intermediate Frequency (IF) down-conversion circuitry 3386, IF processing circuitry 3388, baseband down-conversion circuitry 3390, baseband processing circuitry 3392 and analog-to-digital converter (ADC) circuitry 3394.
In an aspect, RF circuitry XREF to 3325 may include one or more of each of IF interface circuitry 3405, filtering circuitry 3410, upconversion and downconversion circuitry 3415, synthesizer circuitry 3420, filtering and amplification circuitry 3425, power combining and dividing circuitry 3430 and radio chain circuitry 3435.
B2 Baseband Processor Sub-System
In an aspect, baseband processor may contain one or more digital baseband systems 3540.
In an aspect, the one or more digital baseband subsystems 3540 may be coupled via interconnect subsystem 3565 to one or more of CPU subsystem 3570, audio subsystem 3575 and interface subsystem 3580.
In an aspect, the one or more digital baseband subsystems 3540 may be coupled via interconnect subsystem 3545 to one or more of each of digital baseband interface 3560 and mixed-signal baseband sub-system 3535.
In an aspect, interconnect subsystem 3565 and 3545 may each include one or more of each of buses point-to-point connections and network-on-chip (NOC) structures.
In an aspect, audio sub-system 3575 may include one or more of digital signal processing circuitry, buffer memory, program memory, speech processing accelerator circuitry, data converter circuitry such as analog-to-digital and digital-to-analog converter circuitry, and analog circuitry including one or more of amplifiers and filters.
In an aspect, mixed signal baseband sub-system 3600 may include one or more of IF interface 3605, analog IF subsystem 3610, downconverter and upconverter subsystem 3620, analog baseband subsystem 3630, data converter subsystem 3635, synthesizer 3625 and control sub-system 3640.
In an example aspect of
In an example aspect of
In an aspect, boot loader sub-system 3710 may include digital logic circuitry configured to perform configuration of the program memory and running state associated with each of the one or more DSP sub-systems 3705. Configuration of the program memory of each of the one or more DSP sub-systems 3705 may include loading executable program code from storage external to baseband processing sub-system (3700 cross reference). Configuration of the running state associated with each of the one or more DSP sub-systems 3705 may include one or more of the steps of: setting the state of at least one DSP core which may be incorporated into each of the one or more DSP sub-systems to a state in which it is not running, and setting the state of at least one DSP core which may be incorporated into each of the one or more DSP sub-systems into a state in which it begins executing program code starting from a predefined memory location.
In an aspect, shared memory sub-system 3715 may include one or more of read-only memory (ROM), static random access memory (SRAM), embedded dynamic random access memory (eDRAM) and non-volatile random access memory (NVRAM).
In an aspect, digital I/O subsystem 3720 may include one or more of serial interfaces such as I2C, SPI or other 1, 2 or 3-wire serial interfaces, parallel interfaces such as general-purpose input-output (GPIO), register access interfaces and direct memory access (DMA). In an aspect, a register access interface implemented in digital I/O subsystem 3720 may permit a microprocessor core external to baseband processing subsystem (3700 cross reference) to read and/or write one or more of control and data registers and memory. In an aspect, DMA logic circuitry implemented in digital I/O subsystem 3720 may permit transfer of contiguous blocks of data between memory locations including memory locations internal and external to baseband processing subsystem (3700 cross reference).
In an aspect, digital baseband interface sub-system 3725 may provide for the transfer of digital baseband samples between baseband processing subsystem (3700 cross reference) and mixed signal baseband or radio-frequency circuitry external to baseband processing subsystem (3700 cross reference). In an aspect, digital baseband samples transferred by digital baseband interface sub-system 3725 may include in-phase and quadrature (I/Q) samples.
In an aspect, controller sub-system 3740 may include one or more of each of control and status registers and control state machines. In an aspect, control and status registers may be accessed via a register interface and may provide for one or more of: starting and stopping operation of control state machines, resetting control state machines to a default state, configuring optional processing features, configuring the generation of interrupts and reporting the status of operations. In an aspect, each of the one or more control state machines may control the sequence of operation of each of the one or more accelerator sub-systems 3745.
In an aspect, DSP sub-system 3800 may include one or more of each of DSP core sub-system 3805, local memory 3810, direct memory access sub-system 3815, accelerator sub-system 3820, external interface sub-system 3825, power management unit 3830 and interconnect sub-system 3835.
In an aspect, local memory 3800 may include one or more of each of read-only memory, static random access memory or embedded dynamic random access memory.
In an aspect, direct memory access sub-system 3815 may provide registers and control state machine circuitry adapted to transfer blocks of data between memory locations including memory locations internal and external to digital signal processor sub-system 3800.
In an aspect, external interface sub-system 3825 may provide for access by a microprocessor system external to DSP sub-system 3800 to one or more of memory, control registers and status registers which may be implemented in DSP sub-system 3800. In an aspect, external interface sub-system 3825 may provide for transfer of data between local memory 3800 and storage external to DSP sub-system 3800 under the control of one or more of DMA sub-system 3815 and DSP core sub-system 3805.
The aspects and features mentioned and described together with one or more of the previously detailed examples and figures, may as well be combined with one or more of the other examples in order to replace a like feature of the other example or in order to additionally introduce the feature to the other example.
The description and drawings merely illustrate the principles of the disclosure. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art. All statements herein reciting principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.
A block diagram may, for instance, illustrate a high-level circuit diagram implementing the principles of the disclosure. Similarly, a flow chart, a flow diagram, a state transition diagram, a pseudo code, and the like may represent various processes, operations or steps, which may, for instance, be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. Methods disclosed in the specification or in the claims may be implemented by a device having means for performing each of the respective acts of these methods.
Examples may further be or relate to a (computer) program including a program code to execute one or more of the above methods when the program is executed on a computer, processor or other programmable hardware component. Thus, steps, operations or processes of different ones of the methods described above may also be executed by programmed computers, processors or other programmable hardware components. Examples may also cover program storage devices, such as digital data storage media, which are machine-, processor- or computer-readable and encode and/or contain machine-executable, processor-executable or computer-executable programs and instructions. Program storage devices may include or be digital storage devices, magnetic storage media such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media, for example. Other examples may also include computers, processors, control units, (field) programmable logic arrays ((F)PLAs), (field) programmable gate arrays ((F)PGAs), graphics processor units (GPU), application-specific integrated circuits (ASICs), integrated circuits (ICs) or system-on-a-chip (SoCs) systems programmed to execute the steps of the methods described above.
It is to be understood that the disclosure of multiple acts, processes, operations, steps or functions disclosed in the specification or claims may not be construed as to be within the specific order, unless explicitly or implicitly stated otherwise, for instance for technical reasons. Therefore, the disclosure of multiple acts or functions will not limit these to a particular order unless such acts or functions are not interchangeable for technical reasons. Furthermore, in some examples a single act, function, process, operation or step may include or may be broken into multiple sub-acts, -functions, -processes, -operations or -steps, respectively. Such sub acts may be included and part of the disclosure of this single act unless explicitly excluded.
If some aspects have been described in relation to a device or system, these aspects should also be understood as a description of the corresponding method and vice versa. For example, a block, device or functional aspect of the device or system may correspond to a feature, such as a method step, of the corresponding method. Accordingly, aspects described in relation to a method shall also be understood as a description of a corresponding block, a corresponding element, a property or a functional feature of a corresponding device or a corresponding system.
Furthermore, the following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it is to be noted that—although a dependent claim may refer in the claims to a specific combination with one or more other claims—other examples may also include a combination of the dependent claim with the subject matter of each other dependent or independent claim. Such combinations are explicitly proposed herein unless it is stated that a specific combination is not intended. Furthermore, it is intended to include also features of a claim to any other independent claim even if this claim is not directly made dependent to the independent claim.
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