This invention relates to digitally controlled RF phase shifters, and more particularly to phase shifter bits including active elements for performing phase shifting.
Modern electromagnetic communications, surveillance and sensing increasingly rely on array antennas for interfacing or transducing between guided and unguided or freely propagating electromagnetic waves. The advantages of array antennas include the potential for large aperture with relatively light weight, instantaneous beam scanning, and multiple simultaneous beams, including “mbnopulse” operation.
The beam scanning attribute of array antennas requires that the phases of electromagnetic radiation applied to or from each elemental antenna of the array be controlled or adjusted, and these adjustments are performed by electromagnetic radio-frequency (RF) “phase shifters,” where the definition of the term “RF” now includes all frequencies below light frequencies. The general background of the use of phase shifters and array antennas is described in U.S. Pat. No. 5,093,667, issued Mar. 3, 1992 in the name of Andricos. The use of phase shifters in conjunction with an array antenna for monopulse applications is described in U.S. Pat. No. 5,017,927, issued May 21, 1991 in the name of Agrawal et al.
The number of phase shifters in a phased-array antenna system may be as great as twice the number of antenna elements, in order to provide different phase shifts for transmitted and received signals. The cost of phase shifters may represent a major portion of the cost of an array antenna system. A common and relatively inexpensive type of phase shift bit is an ordinary transmission line, well known in the art, having a time delay equal to the desired phase shift at the frequency of operation. A plurality of such transmission lines can be intercoupled with electronic switches to form a multibit or digital phase shifter. In such an arrangement, several phase shifters are intercoupled, having different phase shifts, such as 180°, 90°, 45°, 22½°, and 11¼° for a 5-bit phase shifter. Such a combination of phase shifts can be combined to produce any desired phase shift ranging from 0° to 360°, with no more than about 60 of phase error. Naturally, more bits can be used if a smaller phase shift maximum error is desired. A disadvantage of such transmission-line phase shifters is that they tend to introduce transmission loss into the signal traversing the phase shifter. Another disadvantage of such transmission-line phase shifters is that the bandwidth of the phase shifter depends on its length. Details of a three-bit switched transmission line phase shifter are described in U.S. Pat. No. 4,754,265, issued Jun. 28, 1988 in the name of Henderson et al.
Other types of electromagnetic phase shifters are known. Phase shifters directly controlled by light are described in U.S. Pat. No. 4,675,628, issued Jun. 23, 1987 in the name of Rosen. Electromagnetic phase shifters in which the signal is phase shifted, amplitude controlled, and combined to produce the phase shifted signal are described in U.S. Pat. No. 4,994,773, issued Feb. 19, 1992 in the name of Chen et al.
Improved or alternative phase shifter configurations are desired.
A controllable RF phase shifter according to an aspect of the invention comprises a controllable active RF phase bit including an RF path having a first phase increment (0° or 180°). The phase shifter (also includes a controllable passive RF phase bit) including an RF path having a second phase increment (0°, 90°) different from the first phase increment (0°, 180°). RF coupling means are coupled to the active and passive RF phase bits, for coupling the RF paths of the active and passive phase bits in cascade. Control means are coupled to the active and passive phase bits for controlling each of the active and passive RF phase bits to one of first and second states, for thereby imposing upon RF signal traversing the cascade the first phase increment (180°), the second phase (90°) increment, the sum of the first and second phase increments (270°), or no phase increment (0°).
A phase shifter according to an aspect of the invention comprises a solid-state device including a path for the flow of electrical current between first and second electrodes and a control electrode for controlling the flow of current through the path. A source of signal to be phase shifted is coupled to the control electrode of the device, for controlling the flow of current through the path in response to the signal in such a manner that first electrode signal appearing at the first electrode in response to the signal coupled to the control electrode is in a first phase state (180°) relative to the signal at the control electrode, and in such a manner that second electrode signal appearing at the second electrode in response to the signal coupled to the control electrode is in a second phase state (0°), different from the first phase state (180°). A first switch includes a common terminal coupled to the first electrode of the device and a first independent terminal coupled to reference potential, and also includes a second independent terminal, for, in a first state (180°) of the first switch, coupling the first electrode of the device to the second independent terminal of the first switch, and for, in a second state (0°), coupling the first electrode of the device to the reference potential. A second switch includes a common terminal coupled to the second electrode of the device and a first independent terminal, and also includes a second independent terminal coupled to reference potential, for, in a first state (180°) of the second switch, coupling the second electrode of the device to the second independent terminal of the second switch, and for, in a second state (0°) of the second switch, coupling the second electrode of the device to the first independent terminal of the second switch. A third switch includes a common terminal, and first and second independent terminals. The first independent terminal of the third switch is coupled to the first independent terminal of the second switch and the second independent terminal of the third switch is coupled to the second independent terminal of the first switch. The third switch connects the common terminal of the third switch to the second independent terminal of the third switch in a first state (180°) of the third switch, and connects the common terminal of the third switch to the first independent terminal of the third switch in the second state (0°) of the third switch. Control means are coupled to the first, second, and third switches, for, in a first nominal phase condition (180°), simultaneously controlling the first, second, and third switches to the first states (180°) of the first, second, and third switches, and for, in a second nominal phase condition (0°), simultaneously controlling the first, second, and third switches to the second states (0°) of the first, second, and third switches.
In a particularly advantageous embodiment of this aspect of the invention, the first phase state is 180° and the second phase state is 0°.
A phase shifter according to an aspect of the invention comprises a solid-state device including a path (source to drain) for the flow of electrical current between first and second electrodes, and also includes a control electrode for controlling the flow of current through the path (source to drain). The phase shifter also includes a source of signal to be phase shifted. The source of signal is coupled to the control electrode of the device, for controlling the flow of current through the path (source to drain) in response to the signal in such a manner that first electrode signal appearing at the first electrode in response to the signal coupled to the control electrode is nominally out-of-phase relative thereto, and in such a manner that second electrode signal appearing at the second electrode in response to the signal coupled to the control electrode is nominally in-phase relative thereto. The phase shifter also includes a first switch including a common terminal coupled to the first electrode of the device and a first independent terminal coupled to reference potential (ground). The first switch also includes a second independent terminal. The first switch, in a first state (180°) of the first switch, couples the first electrode of the device to the second independent terminal of the first switch, and in a second state (0°), couples the first electrode of the device to the reference potential (ground). A second switch includes a common terminal coupled to the second electrode of the device and also includes a first independent terminal, and also includes a second independent terminal coupled to reference potential (ground). The second switch, in a first state (180°) of the second switch, couples the second electrode of the device to the second independent terminal of the second switch, and in a second state (0°) of the second switch, couples the second electrode of the device to the first independent terminal of the second switch. A third switch includes a common terminal, and first and second independent terminals. The first independent terminal of the third switch is coupled to the first independent terminal of the second switch, and the second independent terminal of the third switch is coupled to the second independent terminal of the first switch. The third switch connects the common terminal of the third switch to the second independent terminal of the third switch in a first state (180°) of the third switch, and connects the common terminal of the third switch to the first independent terminal of the third switch in the second state (0°) of the third switch. Control means are coupled to the first, second, and third switches, for, in a 180° condition, simultaneously controlling the first, second, and third switches to the first states of the first, second, and third switches, and for, in a 0° condition, simultaneously controlling the first, second, and third switches to the second states (0°) of the first, second, and third switches.
An active electromagnetic RF phase bit according to another aspect of the invention comprises a FET including source, drain, and gate electrodes, and direct-current biasing means coupled to the source, drain, and gate electrodes, for providing biasing energization to the FET. Source, drain, and gate direct-current blocking means are coupled to the source, drain, and gate, respectively, of the FET, for providing RF ports into the bias energized source, drain, and gate electrodes of the FET. An RF signal input path is coupled to the gate direct-current blocking means, whereby electromagnetic RF applied to the RF input port is coupled to the gate electrode of the FET. The RF phase bit also includes first, second, and third three-port, single-pole, double-throw RF switches, each including a common or “movable” port and also including first and second individual ports to which the common port is connected in first (0°) and second (180°) states, respectively, of the RF switches. The common port of the first RF switch is coupled or connected to the drain direct-current blocking means, and the first individual port of the first RF switch is coupled or connected to an RF reference potential such as ground. The common port of the second RF switch is coupled to the source direct-current blocking means, and the second individual port of the second RF switch is coupled or connected to RF reference potential. The RF phase bit includes first coupling means coupling the second individual port of the third RF switch to the second individual port of the first RF switch, and second coupling means coupling the first individual port of the third RF switch to the first individual port of the second RF switch. An RF output signal path is coupled to the common port of the third RF switch. Control means are provided, coupled to the first, second, and third RF switches, for causing the third RF switch to assume the first state in response to a request for a reference phase condition (0°) and the second state (180°) in response to a request for a 180° reference phase condition, and for causing the first and second RF switches to assume the first state in response to a request for a reference phase condition and the second state in response to a request for a 180° phase condition.
In a particular embodiment of this aspect of the invention, each of the first and second coupling means comprises an RF attenuator, which may be controllable. Each of the source and drain direct-current blocking means may comprise a capacitor. In one embodiment, each of the direct-current biasing means coupled to the source, drain, and gate electrodes, respectively, comprises at least an impedance element, exhibiting an impedance of at least 250 ohms at operational frequencies of the phase bit, coupled to the source, drain, and gate electrodes, respectively, and to at least one bias voltage source. A preferred version of this aspect of the invention includes, in each of the direct-current biasing means coupled to the source, drain, and gate electrodes, respectively, a capacitor coupled the impedance element and to the reference potential.
According to another aspect of the invention, a multibit RF phase shifter comprises a phase shifter path for the flow of RF signal between first and second phase shifter ports. The multibit RF phase shifter includes a passive first phase bit having a phase increment of less than 180° relative to a reference value. The first phase bit comprises first and second differing lengths of transmission line, and first bit switching means coupled to the first and second lengths of transmission line for, in a first state (0°) of the first phase bit, connecting the first length of transmission line in the first path, and for, in a second state (180°) of the first phase bit, connecting the second length of transmission line in the phase shifter path. The multibit RF phase shifter also includes an active second RF phase bit. The active second RF phase bit comprises a FET including source, drain, and gate electrodes, and direct-current biasing means coupled to the source, drain, and gate electrodes, for providing biasing energization to the FET. The multibit RF phase shifter also includes source, drain, and gate direct-current blocking means coupled to the source, drain, and gate, respectively, of the FET, for providing RF paths, but not direct-current paths, to the bias energized source, drain, and gate electrodes of the FET. A second RF signal path is coupled to the gate direct-current blocking means, whereby electromagnetic RF applied to a second phase bit RF input port is coupled to the gate electrode of the FET. First, second, and third three-port, single-pole, double-throw RF switches each include a common port, and first and second individual ports to which the common port is connected in first (0°) and second (180°) states, respectively, of the RF switches. The common port of the first RF switch is coupled to the drain direct-current blocking means, and the first individual port of the first RF switch is connected to RF reference potential. The common port of the second RF switch is coupled to the source direct-current blocking means, and the second individual port of the second RF switch is connected to RF reference potential. A first coupling means couples the second individual port of the third RF switch to the second port of the first RF switch, and second coupling means couples the first individual port of the third RF switch to the first individual port of the second RF switch. Second RF phase bit control means are coupled to the first, second, and third RF switches for causing the third RF switch to assume the first state (0°) in response to a request for a nominal 0° phase condition and the second state (180°) in response to a request for a nominal 180° phase condition, and for causing the first and second RF switches to assume the first state (0°) in response to a request for a reference phase condition and the second state (180°) in response to a request for a 180° phase condition. Second RF phase bit connection means are coupled to the phase shifter path, to the RF input port and to the common port of the third RF switch, for cascading the first phase bit with the second phase bit.
In a particularly advantageous version of this aspect of the invention, the first phase bit includes no active element other than switching element(s).
A phase shifter according to another aspect of the invention comprises a solid-state device including a path for the flow of electrical current between first and second electrodes and a control electrode for controlling the flow of current through the path. The phase shifter also includes a source of signal to be phase shifted, the source of signal being coupled to the control electrode of the device, for controlling the flow of current through the path in response to the signal in such a manner that first electrode signal appearing at the first electrode in response to the signal coupled to the control electrode is in a first phase state relative thereto, and in such a manner that second electrode signal appearing at the second electrode in response to the signal coupled to the control electrode is in a second phase state, different from the first phase state. A first switch includes a common terminal coupled to the first electrode of the device and a first independent terminal coupled to reference potential, and also includes a second independent terminal, for, in a first state of the first switch, coupling the first electrode of the device to the second independent terminal of the first switch to thereby define a first signal path for the flow of signal from the first electrode of the device to the second independent terminal of the first switch, and for, in a second state, coupling the first electrode of the device to the reference potential. A second switch includes a common terminal coupled to the second electrode of the device and a first independent terminal, and also includes a second independent terminal coupled to reference potential, for, in a first state of the second switch, coupling the second electrode of the device to the second independent terminal of the second switch, and for, in a second state of the second switch, coupling the second electrode of the device to the first independent terminal of the second switch, thereby defining a second signal path for the flow of signal from the second electrode of the device to the second independent terminal of the second switch. A third switch includes a common terminal, and first and second independent terminals. The first independent terminal of the third switch is coupled by a fourth signal path to the first independent terminal of the second switch, and the second independent terminal of the third switch is coupled by a third signal path to the second independent terminal of the first switch. The third switch connects the common terminal of the third switch to the second independent terminal of the third switch in a first state of the third switch, and connects the common terminal of the third switch to the first independent terminal of the third switch in the second state of the third switch. Control means are coupled to the first, second, and third switches, for, in a first nominal phase condition, simultaneously controlling the first, second, and third switches to the first states of the first, second, and third switches, and for, in a second nominal phase condition, simultaneously controlling the first, second, and third switches to the second states of the first, second, and third switches. A passive phase introducing element is coupled in at least one of the first, second, third, and fourth signal paths, for modifying the phase difference or phase shift occurring upon simultaneous control by the control means between the first and second nominal phase conditions to be other than. In a particularly advantageous embodiment of this embodiment of the invention, the first phase state of the first electrode signal appearing at the first electrode in response to the signal coupled to the control electrode is nominally 180°, and the second phase state (O) of the second electrode signal appearing at the second electrode in response to the signal coupled to the control electrode is nominally 0°. Such a phase shifter may further include or be associated with a controllable passive RF phase bit including an RF path having a second phase increment different from the phase difference.
a is a simplified diagram in block and schematic form, illustrating an active 180° passive phase bit, in the 0° condition, for use in the arrangement of
a illustrates a portion of the arrangement of
In
Unguided electromagnetic radiation received or transduced by antenna 12 of
Multibit phase shifter 13 of
A phase shift controller is illustrated in
As mentioned, an actual array antenna arrangement includes a plurality of elemental antennas such as 12 of
The above description of the operation of the structure 10 of
Similarly, in
In practice, the various elements of a phased-array antenna, and its phase shifters and control, are made in the form of solid-state elements. Everyone knows that such solid-state devices tend to be very small. This small size is very advantageous for many applications, including phase shifters for array antennas, because the weight and size reduction tends to make the equipment more amenable to portability or for use in vehicles, especially airborne or space vehicles. One major disadvantage of passive phase shifters such as those described in conjunction with
Another problem with passive phase shifters using transmission lines is that the physical size of some of the transmission lines may be large. Large size is a problem, because the substrates on which many solid-state systems are made are small. As an example, the excess length (over and above the reference length) of the transmission line suitable for 180° phase shift at 1 GHz may be as great as 6 inches for the case of air dielectric. The presence of the solid-state substrate may reduce this minimum length, and the excess length at higher frequencies is proportionally smaller. However, even lesser lengths may be in excess of those that can be conveniently incorporated into a solid-state RF structure.
According to an aspect of the invention, at least the greatest phase bit of a multibit phase shifter is made as an active phase bit using an active device, and the remainder are passive phase bits. In the optimum case, the active phase bit has gain, thereby tending to offset or compensate for the losses in the passive phase bits of the phase shifter.
a is a simplified schematic diagram of an active 180° phase shifter or phase bit which may be used as the active phase bit 14 of
The RF signal applied to gate 314g of FET 314 is coupled out-of-phase or with a 180° phase shift to the drain 314d of FET 314, and thence by way of a node 361 and an RF coupling, DC blocking capacitor 316 to the common or movable element 311m of a switch 311. Common or movable element 311m of switch 311 can selectively contact a switch terminal 3111 and a switch terminal 3112. Switch terminal 3111 is coupled to a reference potential, illustrated as ground. Switch terminal 3112 is coupled by way of an attenuator illustrated as a block 322 to a terminal 3132 of a switch 313.
The RF signal applied to gate 314g of FET 314 of
Switch 313 of active 180° phase shifter 14 of
A gate bias source designated generally as 340 in
A drain bias source designated generally as 360 in
In operation of the phase shifter 14 of
b illustrates the states of switches 311, 312, and 313 in a state different from that illustrated in
Those skilled in the art know that FET 314 of
As so far described, active phase shifter controller 370 controls the state of switches 311, 312, and 313 under the control of a state control signal applied to control input port 14c. However, there are four passive phase bits in the particular 5-bit phase shifter of the example. These passive phase bits each exhibit different attenuation or heat loss. Thus, depending upon the state of the multibit phase shifter, there may be four different attenuation states attributable to the passive phase bits. According to an aspect of the invention, attenuators 310, 320, and 330 are controllable, and have their attenuation adjusted under the control of an attenuation controller. The attenuation controller is illustrated as a block 372 in
a illustrates another embodiment according to an aspect of the invention. Elements of
A controllable RF phase shifter (10) according to an aspect of the invention comprises a controllable active RF phase bit (14) including an RF path (311, 312, 313, 314) having a first phase increment (0° or 180°). The phase shifter (10) also includes a controllable passive RF phase bit (16) including an RF path (214, 216) having a second phase increment (0°, 90°) different from the first phase increment (0°, 180°). RF coupling means (70) are coupled to the active (14) and passive (16) RF phase bits, for coupling the RF paths of the active and passive phase bits in cascade. Control means (30) are coupled to the active (14) and passive (16) phase bits for controlling each of the active (14) and passive (16) RF phase bits to one of first and second states, for thereby imposing upon RF signal traversing the cascade the first phase increment (180°), the second phase (90°) increment, the sum of the first and second phase increments (270°), or no phase increment (0°).
A phase shifter (14) according to an aspect of the invention comprises a solid-state device (314) including a path (314s to 314d) for the flow of electrical current between first (314d) and second (314s) electrodes and a control electrode (314g) for controlling the flow of current through the path. A source (12) of signal to be phase shifted is coupled to the control electrode (314g) of the device, for controlling the flow of current through the path in response to the signal in such a manner that first electrode (314d) signal appearing at the first electrode (314d) in response to the signal coupled to the control electrode (314g) is in a first phase state (180°) relative to the signal at the control electrode, and in such a manner that second electrode (314s) signal appearing at the second electrode (314s) in response to the signal coupled to the control electrode (314g) is in a second phase state (0°), different from the first phase state (180°). A first switch (311) includes a common terminal (311m) coupled to the first electrode (314d) of the device (314) and a first independent terminal (3111) coupled to reference potential, and also includes a second independent terminal (3112), for, in a first state (180°) of the first switch (311), coupling the first electrode (314d) of the device (314) to the second independent terminal (3112) of the first switch (311), and for, in a second state (0°), coupling the first electrode (314s) of the device (314) to the reference potential. A second switch (312) includes a common terminal (312m) coupled to the second electrode (314s) of the device (314) and a first independent terminal (3121), and also includes a second independent terminal (3122) coupled to reference potential, for, in a first state (180°) of the second switch (312), coupling the second electrode (314s) of the device 9314) to the second independent terminal (3122) of the second switch (312), and for, in a second state (0°) of the second switch (312), coupling the second electrode (314s) of the device (314) to the first independent terminal (3121) of the second switch (312). A third switch (313) includes a common terminal (313m), and first (3131) and second (3132) independent terminals. The first independent terminal (3131) of the third switch (313) is coupled to the first independent terminal (3121) of the second switch (312) and the second independent terminal (3132) of the third switch (313) is coupled to the second independent terminal (3112) of the first switch (311). The third switch (313) connects the common terminal (313m) of the third switch (313) to the second independent terminal (3132) of the third switch (313) in a first state (180°) of the third switch (313), and connects the common terminal (313m) of the third switch (313) to the first independent terminal (3131) of the third switch (313) in the second state (0°) of the third switch (313). Control means (370) are coupled to the first (311), second (312), and third (313) switches, for, in a first nominal phase condition (180°), simultaneously controlling the first (311), second (312), and third (313) switches to the first states (180°) of the first (331), second (312) and third (313) switches, and for, in a second nominal phase condition (0°), simultaneously controlling the first (311), second (312), and third (313) switches to the second states (0°) of the first (311), second (312), and third (313) switches.
In a particularly advantageous embodiment of this aspect of the invention, the first phase state is 180° and the second phase state is 0°.
A phase shifter (14) according to an aspect of the invention comprises a solid-state device (314) including a path (source to drain) for the flow of electrical current between first (314d) and second (314s) electrodes, and also includes a control electrode (314g) for controlling the flow of current through the path (source to drain). The phase shifter (14) also includes a source (14i) of signal to be phase shifted. The source (14i) of signal is coupled to the control electrode (314g) of the device (314), for controlling the flow of current through the path (source to drain) in response to the signal in such a manner that first electrode (314d) signal appearing at the first electrode (314d) in response to the signal coupled to the control electrode (314g) is nominally out-of-phase relative thereto, and in such a manner that second electrode (314s) signal appearing at the second electrode (314s) in response to the signal coupled to the control electrode (314g) is nominally in-phase relative thereto. The phase shifter (14) also includes a first switch (311) including a common terminal (311m) coupled to the first electrode (314d) of the device and a first independent terminal (3111) coupled to reference potential (ground). The first switch (311) also includes a second independent terminal (3112). The first switch (311), in a first state (180°) of the first switch (311), couples the first electrode (314d) of the device (314) to the second independent terminal (3112) of the first switch (311), and in a second state (0°), couples the first electrode (314d) of the device (314) to the reference potential (ground). A second switch (312) includes a common terminal (312m) coupled to the second electrode (314s) of the device (314) and also includes a first independent terminal (3121), and also includes a second independent terminal (3122) coupled to reference potential (ground). The second switch (312), in a first state (180°) of the second switch (312), couples the second electrode (314s) of the device (314) to the second independent terminal (3122) of the second switch (312), and in a second state (0°) of the second switch (312), couples the second electrode (314s) of the device (314) to the first independent terminal (3121) of the second switch (312). A third switch (313) includes a common terminal (313m), and first (3131) and second (3132) independent terminals. The first (3131) independent terminal of the third switch is coupled to the first independent terminal (3121) of the second switch (312), and the second independent terminal (3122) of the third switch is coupled to the second independent terminal (3112) of the first switch (311). The third switch (313) connects the common terminal (313m) of the third switch (313) to the second independent terminal (3132) of the third switch in a first state (180°) of the third switch (313), and connects the common terminal (313m) of the third switch (313) to the first independent terminal (3131) of the third switch in the second state (0°) of the third switch (313). Control means are coupled to the first (311), second (312), and third (313) switches, for, in a 180° condition, simultaneously controlling the first (311), second (312), and third (313) switches to the first states of the first (311), second (312), and third (313) switches, and for, in a 0° condition, simultaneously controlling the first (311), second (312), and third (313) switches to the second states (0°) of the first (311), second (312), and third (313) switches.
An active electromagnetic RF phase bit (14) according to another aspect of the invention comprises a FET (314) including source (314s), drain (314d), and gate (314g) electrodes, and direct-current biasing means (340, 350, 360) coupled to the source (314s), drain (314d), and gate (314g) electrodes, for providing biasing energization to the FET (314). Source (314s), drain (314d), and gate (314g) direct-current blocking means (318, 316, 310) are coupled to the source (314s), drain (314d), and gate (314g), respectively, of the FET (314), for providing RF ports into the bias energized source (314s), drain (314d), and gate (314g) electrodes of the FET (314). An RF signal input path (14i, 308) is coupled to the gate (314g) direct-current blocking means (310), whereby electromagnetic RF applied to the RF input port (14i) is coupled to the gate (314g) electrode of the FET (314). The RF phase bit (14) also includes first (311), second (312), and third (313) three-port, single-pole, double-throw RF switches, each including a common or “movable” port (311m, 312m, 313m) and also including first (3111, 3121, 3131) and second (3112, 3122, and 3132) individual ports to which the common port (311m, 312m, 313m) is connected in first (0°) and second (180°) states, respectively, of the RF switches. The common port (311m) of the first RF switch (311) is coupled or connected to the drain (314d) direct-current blocking means (316), and the first individual port (3111) of the first RF switch (311) is coupled or connected to an RF reference potential such as ground. The common port (312m) of the second RF switch (312) is coupled to the source (314s) direct-current blocking means (318), and the second individual port (3122) of the second RF switch (312) is coupled or connected to RF reference potential. The RF phase bit (14) includes first coupling means (322) coupling the second individual port (3132) of the third RF switch (313) to the second individual port (3112) of the first RF switch (311), and second coupling means (332) coupling the first individual port (3131) of the third RF switch (313) to the first individual port (3121) of the second RF switch (312). An RF output signal path (14o) is coupled to the common port (313m) of the third RP switch (313). Control means (370) are provided, coupled to the first (311), second (312), and third (313) RF switches, for causing the third RF switch (313) to assume the first state in response to a request for a reference phase condition (0°) and the second state (180°) in response to a request for a 180° reference phase condition, and for causing the first and second RF switches to assume the first state in response to a request for a reference phase condition and the second state in response to a request for a 180° phase condition.
In a particular embodiment of this aspect of the invention, each of the first (322) and second (332) coupling means comprises an RF attenuator, which may be controllable. Each of the source (314s) and drain (314d) direct-current blocking means (316, 318) may comprise a capacitor. In one embodiment, each of the direct-current biasing means (340, 350, 360) coupled to the source (314s), drain (314d), and gate (314g) electrodes, respectively, comprises at least an impedance element (342, 352, 362), exhibiting an impedance of at least 250 ohms at operational frequencies of the phase bit, coupled to the source (314s), drain (314d), and gate (314g) electrodes, respectively, and to at least one bias voltage source (314s). A preferred version of this aspect of the invention includes, in each of the direct-current biasing means (340, 350, 360) coupled to the source (314s), drain (314d), and gate (314g) electrodes, respectively, a capacitor (344, 354, 364) coupled the impedance element (342, 352, 362) and to the reference potential.
According to another aspect of the invention, a multibit RF phase shifter (10) comprises a phase shifter path (14, 16, . . . ) for the flow of RF signal between first (14i) and second (22o) phase shifter ports. The multibit RF phase shifter (10) includes a passive first phase bit (16) having a phase increment of less than 180° relative to a reference value. The first phase bit (16) comprises first (214) and second (216) differing lengths of transmission line, and first bit switching means (210, 212) coupled to the first (214) and second (216) lengths of transmission line for, in a first state (0°) of the first phase bit (16), connecting the first length (214) of transmission line in the first path, and for, in a second state (180°) of the first phase bit (16), connecting the second length (216) of transmission line in the phase shifter path. The multibit RF phase shifter (10) also includes an active second RF phase bit (14). The active second RF phase bit (14) comprises a FET (314) including source (314s), drain (314d), and gate (314g) electrodes, and direct-current biasing means (340, 350, 360) coupled to the source (314s), drain (314d), and gate (314g) electrodes, for providing biasing energization to the FET (314). The multibit RF phase shifter also includes source (314s), drain (314d), and gate (314g) direct-current blocking means coupled to the source (314s), drain (314d), and gate (314g), respectively, of the FET (314), for providing RF paths, but not direct-current paths, to the bias energized source (314s), drain (314d), and gate (314g) electrodes of the FET (314). A second RF signal path is coupled to the gate (314g) direct-current blocking means, whereby electromagnetic RF applied to a second phase bit RF input port is coupled to the gate (314g) electrode of the FET (314). First (311), second (312), and third (313) three-port, single-pole, double-throw RF switches each include a common port (311m, 312m, 313m), and first (3111, 3121, 3131) and second individual ports (3112, 3122, 3132) to which the common port (311m, 312m, 313m) is connected in first (0°) and second (180°) states, respectively, of the RF switches. The common port (311m) of the first RF switch (311) is coupled to the drain (314d) direct-current blocking means (316), and the first individual port (3111) of the first RF switch (311) is connected to RF reference potential. The common port (312m) of the second RF switch (312) is coupled to the source (314s) direct-current blocking means (318), and the second individual port (3122) of the second RF switch (312) is connected to RF reference potential. A first coupling means (322) couples the second individual port (3132) of the third RF switch (313) to the second port (3112) of the first RF switch (311), and second coupling means (332) couples the first individual port (3131) of the third RF switch (313) to the first individual port (3121) of the second RF switch (312). Second RF phase bit control means (370) are coupled to the first (311), second (312), and third (313) RF switches for causing the third RF switch (313) to assume the first state (0°) in response to a request for a nominal 0° phase condition and the second state (180°) in response to a request for a nominal 180° phase condition, and for causing the first (311) and second (312) RF switches to assume the first state (0°) in response to a request for a reference phase condition and the second state (180°) in response to a request for a 180° phase condition. Second RF phase bit connection means (14o, 70) are coupled to the phase shifter (14) path, to the RF input port and to the common port (312m) of the third RF switch, for cascading the first phase bit with the second phase bit.
In a particularly advantageous version of this aspect of the invention, the first phase bit (16) includes no active element other than switching element(s).
A phase shifter (400) according to another aspect of the invention comprises a solid-state device (314) including a path (314s to 314d) for the flow of electrical current between first (314d) and second (314s) electrodes and a control electrode (314g) for controlling the flow of current through the path (314s to 314d). The phase shifter (400) also includes a source (12) of signal to be phase shifted, the source (12) of signal being coupled to the control electrode (314g) of the device (314), for controlling the flow of current through the path (314s to 314d) in response to the signal in such a manner that first electrode (314d) signal appearing at the first electrode (314d) in response to the signal coupled to the control electrode (314g) is in a first phase state (180°) relative thereto, and in such a manner that second electrode (314s) signal appearing at the second electrode (314s) in response to the signal coupled to the control electrode (314g) is in a second phase state (0°), different from the first phase state (180°). A first switch (311) includes a common terminal (311m) coupled to the first electrode (314d) of the device (314) and a first independent terminal (3111) coupled to reference potential (ground), and also includes a second independent terminal (3112), for, in a first state (180°) of the first switch (311), coupling the first electrode (314d) of the device (314) to the second independent terminal (3112) of the first switch (311) to thereby define a first signal path (361, 316, 311m, 3112) for the flow of signal from the first electrode (314d) of the device (314) to the second independent terminal (3112) of the first switch (311), and for, in a second state (0°), coupling the first electrode (314d) of the device (314) to the reference potential (ground). A second switch (312) includes a common terminal (312m) coupled to the second electrode (314s) of the device (314) and a first independent terminal (3121), and also includes a second independent terminal (3122) coupled to reference potential (ground), for, in a first state (180°) of the second switch (312), coupling the second electrode (314s) of the device (314) to the second independent terminal (3122) of the second switch (312), and for, in a second state (0°) of the second switch (312), coupling the second electrode (314s) of the device (314) to the first independent terminal (3121) of the second switch (312), thereby defining a second signal path (351, 318, 312m, 3121) for the flow of signal from the second electrode (314s) of the device (314) to the second independent terminal (3122) of the second switch (312). A third switch (313) includes a common terminal (313m), and first (3131) and second (3132) independent terminals. The first independent (3131) terminal of the third switch (313) is coupled by a fourth signal path (332) to the first independent terminal (3121) of the second switch (312), and the second independent terminal (3132) of the third switch (313) is coupled by a third signal path (322) to the second independent terminal (3112) of the first switch (311). The third switch (313) connects the common terminal (313m) of the third switch (313) to the second independent terminal (3132) of the third switch (313) in a first state (180°) of the third switch (313), and connects the common terminal (313m) of the third switch (313) to the first independent terminal (3131) of the third switch (313) in the second state (0°) of the third switch (313). Control means (370) are coupled to the first (311), second (312), and third (313) switches, for, in a first nominal phase condition (180°), simultaneously controlling the first (311), second (312), and third (313) switches to the first states (180°) of the first (311), second (312), and third (313) switches, and for, in a second nominal phase condition (0°), simultaneously controlling the first (311), second (312), and third (313) switches to the second states (0°) of the first (311), second (312), and third (313) switches. A passive phase introducing element (410) is coupled in at least one of the first (401), second (402), third (403) and fourth (404) signal paths, for modifying the phase difference occurring upon simultaneous control by the control means between the first (180°) and second (0°) nominal phase conditions to be other than 180°. In a particularly advantageous embodiment of this embodiment of the invention, the first phase state (180°) of the first electrode signal (314d) appearing at the first electrode (314d) in response to the signal coupled to the control electrode (314g) is nominally 180°, and the second phase state (0°) of the second electrode signal (314s) appearing at the second electrode (314s) in response to the signal coupled to the control electrode (314g) is nominally 0°. Such a phase shifter may further include or be associated with a controllable passive RF phase bit including an RF path having a second phase increment different from the phase difference.
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