1. Field
The present disclosure relates to communication equipment and, more specifically but not exclusively, to radio-frequency (RF) receivers.
2. Description of the Related Art
This section introduces aspects that may help facilitate a better understanding of the disclosure. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art.
Recent development of very high-speed, high-resolution, and high-dynamic-range linear analog-to-digital converters (ADCs) enables implementation of certain RF-receiver functions using a digital signal processor (DSP) instead of the analog RF hardware conventionally used for these purposes in the previous generation of RF receivers. However, the use of wider bandwidths, multiple spectral bands, and/or spectrum sharing introduces new challenges to the receiver design.
Whereas multichannel-receiver architectures often need local oscillator (LO) signals in multiple spectral bands, a phase-lock loop (PLL) for providing a LO signal is a relatively complex circuit. Such a circuit can take up a relatively large chip area and/or consume considerable power. In addition, a PLL may result in an increased level of electromagnetic interference (EMI), ground bouncing, frequency pulling, and other deleterious effects that tend to degrade the overall receiver performance.
An embodiment of a disclosed multichannel receiver may use a single master clock to generate (i) the sampling-clock signal that sets the sampling rate of the receiver's ADC and (ii) multiple electrical local-oscillator signals that are used in various channels of the receiver's analog down-converter to translate to intermediate frequency the RF signals received on the receiver's array of antennas. The multichannel receiver may employ a plurality of interconnected frequency dividers configured to variously divide the master-clock frequency to generate the sampling-clock signal and the multiple local-oscillator signals in a manner that causes these signals to have different respective frequencies. The use of a single master clock may advantageously enable the multichannel receiver to have a smaller size, consume less power, and exhibit lower levels of phase noise and EMI than conventional receivers that rely on multiple PLLs to generate sampling-clock and local-oscillator signals.
According to one embodiment, a multichannel receiver comprises: a plurality of mixers, each one of the plurality of mixers being configured to mix a respective one of a plurality of electrical RF signals and a respective one of a plurality of electrical LO signals to generate a respective one of a plurality of electrical intermediate-frequency (IF) signals, each electrical LO signal of the plurality of LO signals having a different frequency; an ADC configured to convert the electrical IF signals into a corresponding digital IF signal carrying a sequence of discrete digital samples generated by the ADC at a sampling rate determined by a sampling-clock signal; and a plurality of frequency dividers configured to frequency divide a master-clock signal to generate the sampling-clock signal and the plurality of electrical LO signals of different frequencies.
According to another embodiment, a receiver comprises: a first mixer configured to mix a first electrical RF signal and a first electrical LO signal to generate a first electrical IF signal; an ADC configured to convert the first electrical IF signal into a corresponding digital IF signal carrying a sequence of discrete digital samples generated by the ADC at a sampling rate determined by a sampling-clock signal; a first clock generator configured to generate a master-clock signal; a first frequency divider configured to frequency divide the master-clock signal to generate the first electrical LO signal; and a second frequency divider configured to frequency divide the master-clock signal to generate the sampling-clock signal.
Other aspects, features, and benefits of various disclosed embodiments will become more fully apparent, by way of example, from the following detailed description and the accompanying drawings, in which:
Receiver 100 comprises an array of antennas 1021-102n, each coupled to a respective one of RF front-end (FE) circuits 1061-106n. In operation, each antenna 102i converts a received electromagnetic wave into a corresponding electrical RF signal 104i, where i=1, 2, . . . , n. Each FE circuit 106i then transforms electrical signal 104i generated by antenna 102i into a corresponding electrical RF signal 108i more suitable for down-conversion to intermediate frequency (IF) in a multichannel down-converter 110. In an example embodiment, the signal transformation performed in FE circuit 106i may include, but is not limited to (i) signal amplification to compensate for transmission losses and (ii) rejection of possible out-of-band noise and interference. These operations can be achieved, e.g., as known in the art, using one or more low-noise amplifiers (LNAs) and one or more filter stages, respectively (not explicitly shown in
Multichannel down-converter 110 includes a plurality of mixers 1121-112n, each configured to mix the corresponding one of electrical signals 1081-108n with a corresponding one of electrical local-oscillator (LO) signals 1161-116n. Each of the resulting translated electrical signals 1181-118n may optionally be filtered in a respective band-pass filter (not explicitly shown in
In an example embodiment, ADC 140 is an RF-sampling ADC (RF-ADC) that has a relatively high resolution and a relatively high dynamic range, and is capable of sampling IF signal 132 at a sampling rate that is higher, by at least a factor of two, than the bandwidth of this IF signal. RF-ADCs that can be used as ADC 140 are commercially available from several vendors. For example, Texas Instruments Inc. and Analog Devices Inc. offer for sale two families of direct RF-sampling ADCs under the product codes ADC32RFXX and AD96XX, respectively. A person of ordinary skill in the art will be able to select, from those two families, a suitable ADC for use in an embodiment of receiver 100.
A digital electrical signal 142 generated by ADC 140 is applied to a digital signal processor (DSP) 150 configured to recover the data encoded in the electromagnetic wave received by antennas 1021-102n. The digital signal processing implemented in DSP 150 may include, but is not limited to (i) digital down-conversion from the designated IF band to baseband, (ii) digital filtering, and (iii) data decoding. The recovered data are directed to external circuits via an electrical output signal 152.
LO signals 1161-116n and a sampling-clock signal 138 that clocks ADC 140 are generated using a master-clock generator 160. More specifically, master-clock generator 160 is configured to generate a master-clock signal 162 having a relatively high frequency (see example values given in the text below), sufficiently low jitter, and sufficiently fast slew rate. In an example embodiment, master-clock generator 160 may be implemented using a PLL. The output of the voltage-controlled oscillator (VCO) in the PLL may be buffered, e.g., as known in the art, to cause master-clock signal 162 to have the aforementioned desired characteristics.
A plurality of frequency dividers 1700-170n are configured to variously divide the frequency of master-clock signal 162 to generate divided-frequency signals 1720-172n, respectively. Each of divided-frequency signals 1720-172n typically has multiple frequency components that include a respective main divided frequency and also higher harmonics and/or sub-harmonics of the main divided frequency. The main divided frequency in a divided-frequency signal 172k generated by frequency divider 170k is lower than the frequency of master-clock signal 162 by a fixed division factor Mk (also see
In some embodiments, frequency dividers 1700-170n may benefit from or be implemented using circuits disclosed in the following publications: (i) Benzad Razavi, “RF Microelectronics,” Prentice Hall, 1998, pp. 290-297; (ii) Louis Fan Fei, “Frequency Divider Design Strategies,” Broadband Technology, March 2005; (iii) Mohit Arora, Clock Dividers Made Easy, SNUG Boston, 2002; and (iv) Myung-Woon Hwang, Jong-Tae Hwang, and Gyu-Hyeong Cho, “Design of high-speed CMOS prescaler,” IEEE APC on ASICs, 2000. These publications are incorporated herein by reference in their entirety.
A filter 174i located between frequency divider 170 and mixer 112i is configured to generate LO signal 116i by passing through the main divided frequency of signal 172i, while stopping, attenuating, and/or rejecting the higher-order harmonics and, in some embodiments, also the sub-harmonics thereof. In an example embodiment, filters 1741-174n can be implemented as low-pass filters. In an alternative embodiment, filters 1741-174n can be implemented as band-pass filters.
A filter 180 located between frequency divider 1700 and ADC 140 generates sampling-clock signal 138 by passing through the main divided frequency of signal 1720 and a predetermined number of the odd higher harmonics thereof, while stopping or rejecting the other harmonics and sub-harmonics of the main divided frequency, and possibly noise that may be coupled to the sampling-clock channel due to EMI, the presence of power-supply noise, and/or via any other coupling mechanism. A representative filter that can be used as filter 180, as well as representative benefits of its use in generating the sampling-clock signal of an ADC, such as ADC 140, are described in commonly owned U.S. Patent Application Publication No. 2014/0210536, which is incorporated herein by reference in its entirety.
An example embodiment of receiver 100 may be implemented as an RF integrated circuit (IC) or chipset. For example, in one embodiment, receiver 100 may be implemented using the following three ICs: (i) an RF-ADC IC, e.g., containing ADC 140; (ii) a multiband down-converter IC, e.g., containing down-converter 110 and, optionally, a circuit portion 190 indicated by the corresponding dashed rectangle in
The architecture of receiver 100 may provide one or more of the following benefits.
An example embodiment of receiver 100 uses a single common PLL (e.g., located in 160,
An example embodiment of receiver 100 may be used for applications where low cost and enhanced performance are simultaneously required.
The use of filter 180 positively contributes to the improved signal-to-noise ratio (SNR), sensitivity, and blocking exhibited by receiver 100.
The use of a chipset, e.g., as outlined above, in an embodiment of receiver 100 may result in further size and/or cost reduction. Reduced power consumption may also reduce the junction temperature of one or more of the ICs in the chipset, which may positively contribute to the overall reliability of the receiver and of the corresponding wireless communication system.
DSP 200 comprises a digital down-converter 202 and a digital demodulator 204. Digital down-converter 202 is configured to translate digital signal 142 to one or more baseband channels for demodulation and decoding in digital demodulator 204. Frequency translation is achieved by digitally mixing, in digital mixers 2201-220n, (i) a plurality of portions 2121-212n of digital electrical signal 142 generated by a digital signal splitter 210 and (ii) a plurality of digital LO signals 2161-216n generated by numerically controlled oscillators (NCOs) 2141-214n, respectively, as indicated in
NCOs 2141-214n generate digital LO signals 2161-216n using a common (single) digital-reference-clock signal 208 generated by a digital clock generator 206. In some embodiments, digital-reference-clock signal 208 may optionally be provided, as a reference input signal, to the PLL in master-clock generator 160 (see
In some embodiments, digital clock generator 206 may generate digital-reference-clock signal 208 based on an external clock reference signal 205.
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In one embodiment, receiver 100 may be designed using the following frequency plan:
In an alternative embodiment, receiver 100 may be designed using the following frequency plan:
In yet another alternative embodiment, receiver 100 may be designed using the following frequency plan:
Based on the above examples, a person of ordinary skill in the art will understand how to make additional alternative frequency plans for use in the corresponding alternative embodiments of receiver 100.
Circuit 400 comprises a plurality of frequency dividers 4700-470n that are generally analogous to frequency dividers 1700-170n. However, unlike frequency dividers 1700-170n in receiver 100, which are connected in parallel to one another, frequency dividers 4700-470n in circuit 400 are serially connected to one another. As a result, the main divided frequency of signal 172k in circuit 400 depends on the division factors M0-Mk of all preceding frequency dividers 470 and can be expressed as FVCO/(M0×M1× . . . ×Mk). In contrast, the main divided frequency of signal 172k in the embodiment of receiver 100 shown in
A person of ordinary skill in the art will understand that various alternative connections of frequency dividers are also possible in a divider circuit configured to generate signals 1720-172n. For example, in an alternative embodiment of the divider circuit, some frequency dividers may be connected serially with one another, while some other frequency dividers may be connected in parallel to one another.
One difference between receivers 100 and 500 is that the latter receiver has a “complex” IF-signal-processing chain, as opposed to the “real” IF-signal-processing chain used in the former receiver. Receiver 500 implements the complex IF-signal processing using two parallel circuit planes, the elements of which are labeled using subscripts I and Q, respectively, where the “I” stands for “in-phase,” and the “Q” stands for “quadrature.” Receiver 500 employs a plurality of complex mixers 5121-512n to generate appropriate input signals for the I and Q circuit planes. More specifically, a complex mixer 512i generates a respective input signal for the I circuit plane by mixing, in its first mixer, a first copy of signal 108i and a first copy of LO signal 116i. Complex mixer 512i also generates a respective input signal for the Q circuit plane by mixing, in its second mixer, a second copy of signal 108i and a relatively phase-shifted copy of the same LO signal 116i that is generated in the complex mixer by applying a relative phase shift of approximately 90 degrees to a second copy of LO signal 116i.
A digital output signal 542I of the I circuit plane is generated by ADC 140I. A digital output signal 542Q of the Q circuit plane is similarly generated by ADC 140Q. Both ADCs are clocked using sampling-clock signal 138. Digital signals 542I and 542Q are applied to a DSP 550 for appropriate processing therein to recover the data encoded in the electromagnetic wave received by antennas 1021-102n.
According to an example embodiment disclosed above in reference to
In some embodiments of the above apparatus, the apparatus further comprises a first clock generator (e.g., 160,
In some embodiments of any of the above apparatus, the apparatus further comprises: a second clock generator (e.g., 206,
In some embodiments of any of the above apparatus, the digital down-converter is a part of a digital signal processor (e.g., 150,
In some embodiments of any of the above apparatus, the digital down-converter comprises: a digital signal splitter (e.g., 210,
In some embodiments of any of the above apparatus, the plurality of interconnected frequency dividers comprises two or more frequency dividers (e.g., 1700-170n,
In some embodiments of any of the above apparatus, the plurality of interconnected frequency dividers comprises two or more frequency dividers (e.g., 4700-470n,
In some embodiments of any of the above apparatus, one or more of the plurality of interconnected frequency dividers are configured to divide the frequency of the master-clock signal in a manner that causes different electrical LO signals of the plurality of electrical LO signals to have different respective frequencies.
In some embodiments of any of the above apparatus, some of the plurality of interconnected frequency dividers are further configured to divide the frequency of the master-clock signal in a manner that causes the sampling-clock signal to have a frequency that is different from any of the respective frequencies.
In some embodiments of any of the above apparatus, some of the plurality of interconnected frequency dividers are configured to divide the frequency of the master-clock signal in a manner that causes the sampling-clock signal to have a frequency that is different from a frequency of any other of the plurality of electrical LO signals.
In some embodiments of any of the above apparatus, the plurality of interconnected frequency dividers includes a set of frequency dividers, with each frequency divider in said set being configured to apply a respective integer frequency-division factor.
In some embodiments of any of the above apparatus, the set of frequency dividers is configured such that a set of integer values that consists of the respective integer frequency-division factors includes two or more consecutive integers (e.g., M1=8, M2=9, M3=10, M4=11).
In some embodiments of any of the above apparatus, the plurality of interconnected frequency dividers includes a set of frequency dividers, with each frequency divider in said set being configured to apply a respective fractional frequency-division factor.
In some embodiments of any of the above apparatus, the apparatus further comprises an array of antennas (e.g., 1021-102n,
In some embodiments of any of the above apparatus, the ADC (e.g., 140,
In some embodiments of any of the above apparatus, the multichannel down-converter is an analog electrical circuit.
In some embodiments of any of the above apparatus, the multichannel down-converter is a mixed-signal electrical circuit that includes an analog circuit portion and a digital circuit portion.
According to another example embodiment disclosed above in reference to
In some embodiments of the above apparatus, the first electrical LO signal and the sampling-clock signal have different respective frequencies.
In some embodiments of any of the above apparatus, the electrical analog down-converter includes a second mixer (e.g., 112j, i≠j,
In some embodiments of any of the above apparatus, the first electrical LO signal and the second electrical LO signal have different respective frequencies.
In some embodiments of any of the above apparatus, the apparatus further comprises a second clock generator (e.g., 206,
In some embodiments of any of the above apparatus, the apparatus further comprises a filter (e.g., an optional filter configured to filter 118i, not explicitly shown in
While this disclosure includes references to illustrative embodiments, this specification is not intended to be construed in a limiting sense.
For example, in some embodiments, receiver 100 may be modified to be a single-channel receiver. The corresponding modification of receiver 100 may include removing or disabling all but one channel of down-converter 110, thereby transforming that down-converter into a single-channel down-converter.
Various modifications of the described embodiments, as well as other embodiments within the scope of the disclosure, which are apparent to persons skilled in the art to which the disclosure pertains are deemed to lie within the principle and scope of the disclosure, e.g., as expressed in the following claims.
Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value or range.
It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this disclosure may be made by those skilled in the art without departing from the scope of the disclosure, e.g., as expressed in the following claims.
Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence.
Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the disclosure. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.”
Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements.
The described embodiments are to be considered in all respects as only illustrative and not restrictive. In particular, the scope of the disclosure is indicated by the appended claims rather than by the description and figures herein. All changes that come within the meaning and range of equivalency of the claims are to be embraced within their scope.
The description and drawings merely illustrate the principles of the disclosure. It will thus be appreciated that those of ordinary skill in the art will be able to devise various arrangements that, although not explicitly described or shown herein, embody the principles of the disclosure and are included within its spirit and scope. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions. Moreover, all statements herein reciting principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.
The functions of the various elements shown in the figures, including any functional blocks labeled as “processors,” may be provided through the use of dedicated hardware as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which may be shared. Moreover, explicit use of the term “processor” or “controller” should not be construed to refer exclusively to hardware capable of executing software, and may implicitly include, without limitation, digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non volatile storage. Other hardware, conventional and/or custom, may also be included.
It should be appreciated by those of ordinary skill in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the disclosure.