Patent Application
20070047579
1. Field of the Invention
This invention relates broadly to telecommunications. More particularly, this invention relates to methods and apparatus for a link layer—physical layer interface.
2. State of the Art
Modern telecommunication relies on many protocols for the transport and multiplexing of data. Moreover, many different transmission media are used, e.g. copper wire, optical fiber, radio signal, etc. It is desirable that the different protocols be able to make use of different media. Telecommunication media and protocols are often conceived of as “layers”. While there is some disagreement as to how many layers there should be, most protocol suites share the concept of at least three layers: media, transport, and application. The media layer may be divided into two layers: the physical layer and the link layer. The physical layer involves the actual signaling and medium for the signals, e.g. serial data link (RS-232), 10 megabit Ethernet (10BASE-T), and the synchronous optical network (SONET), etc. The link layer involves addressing schemes such as media access control (MAC), asynchronous transfer mode (ATM), high level data link control (HDLC), fiber channel (FC), generic framing procedure (GFP), etc. Protocol layers communicate with each other via “interfaces”. Popular link layer—physical layer interfaces include Universal Test & Operations Physical Interface for ATM (UTOPIA), packet over SONET physical layer (POS-PHY), system packet interface (SPI), etc.
Link layer protocols and their associated physical layer interfaces utilize different protocol data units (PDUs). For example, ATM and the UTOPIA interface utilize the 53-byte cell. The basic SONET frame is 810 bytes. However, SONET bandwidth is adjusted using virtual concatenated groups (VCGs). Other protocols use variable length packets. Many different link layer protocols are adapted to use the SONET physical layer via the various interfaces mentioned above.
Generic Framing Procedure utilizes a variable length PDU and requires that the PDU length be indicated at the start of the PDU. When receiving data via a link layer protocol for retransmission using GFP, the data must be buffered until a full packet has been received (and the packet length thus known) before it can be retransmitted. Furthermore, when receiving data via a link layer protocol for retransmission via a SONET signal, it is often necessary to compensate for different clock domains. This requires a buffer and some kind of flow control signaling.
In constructing SONET switching devices it is desirable to provide as much functionality as possible on a single chip. However, chip real estate is limited. While it might be desirable to provide the functionality of multiple link layer protocols on a single chip, generally there is simply not enough space.
It is therefore an object of the invention to provide a link layer—PHY layer interface which is optimal for GFP.
It is also an object of the invention to provide a link layer—PHY layer interface which minimizes the need for buffers.
It is another object of the invention to provide methods and apparatus for supporting multiple link layer protocols on a single chip.
In accord with these objects, which will be discussed in detail below, the invention provides a multipacket interface (MPI) which includes (in both transmit and receive directions) a 32-bit data path, a 5-bit channel identifier, a packet abort/error signal, a start-of-frame signal, an end-of-frame signal, a data valid signal, and an interface clock. In the transmit direction, the interface also includes a 1-bit data request signal and a 16-bit PDU length indicator. In the receive direction the interface also includes a 1-bit server signal failure signal. All of the receive side signals are outputs from the PHY layer side and inputs to the link layer side. All of the signals on the transmit side are inputs to the PHY layer device and outputs from the link layer device except for clock, channel number and data request which are outputs from the PHY layer side and inputs to the link layer device. The total number of pins needed to support the interface is 117 (55 for the receive part and 62 for the transmit part).
The interface according to the invention provides direct access to PDU Encapsulation (framing) channels and corresponding SONET VCGs to any kind of standards-based or proprietary link layer—PHY layer interface via an appropriate adaptation layer. This allows users greater flexibility in using the PDU framing channels and the SONET VCGs. If the inventive interface is implemented on both the PHY layer and the link layer, no adaptation layer is needed.
A clock adaptation buffer is not required on the PHY layer device as the interface makes use of the buffer on the adaptation layer device, or if the interface is implemented on both the PHY layer and the link layer, the adaptation buffer on the link layer device is used. Channel polling is performed on the PHY layer with the PHY layer being the timing master. The backpressure data request signal is controlled by the PHY layer.
The 5-bit channel identifier supports up to thirty-two channels (although the presently preferred embodiment uses twenty-four channels) or “ports” which are time division multiplexed over the four byte wide data path. The channel identifier is used together with the data request signal. This assures that head of line blocking on one channel does not adversely affect the other channels. The 5-bit out-of-band channel ID allows for greater bandwidth and higher speed.
The use of an out-of-band payload length indicator allows GFP framing on PDUs without having to buffer payload and add to latency. None of the existing link layer-PHY layer interfaces are capable of doing this; but the interface according to the invention allows this optimization for GFP. Therefore, in this context, the interface allows optimal operation with respect to external network processors which already buffer payload.
The interface according to the invention also allows multiple different types of PDUs (fixed and variable length) to be exchanged on different channels of the same interface. In other words, the interface allows for mapping mixed traffic into a common transport layer. The interface according to the invention is easily adaptable to any of several link layer interfaces via a simple adaptation layer which can be provided on an ASIC (application specific integrated circuit) or FPGA (field programmable gate array).
Additional objects and advantages of the invention will become apparent to those skilled in the art upon reference to the detailed description taken in conjunction with the provided figures.
Turning now to
In the transmit (TX) direction, the Link Layer device receives three signals from the PHY layer device and transmits six signals to the PHY layer device. The received signals are: a clock signal PCLK2, a 5-bit channel identifier signal PTCHNUM, and a 1-bit data request signal PDREQ. The signals transmitted to the PHY layer device are: a 32-bit data signal PTDAT, a 1-bit start-of-frame signal PTSOF, a 1-bit end-of-frame signal PTEOF, a 1-bit packet abort/error signal PTABT, a 4-bit data valid signal PTDATVAL, and a 16-bit PDU length indicator signal PTPLI.
In the presently preferred embodiment of the invention, the total number of pins needed to support the interface is 117 (55 for the receive part and 62 for the transmit part). According to the presently preferred embodiment, the clock signals PCLK1 and PCLK2 are 100 MHz clock signals which provides a total bandwidth of about 3.2 GHz (3.2 gigabits per second) which makes the interface ideally suited for handling a 2.488 GHz SONET/SDH frame.
Those skilled in the art will appreciate that a standard SPI-3 interface includes the following receive side signals: a 32-bit data signal RDAT, a clock signal RFCLK, a 1-bit receive enable signal RENB, a 2-bit valid byte config signal RMOD, a 1-bit parity signal RPRTY, a 1-bit valid data signal RVAL, a 1 bit start of packet signal RSOP, a 1-bit end of packet signal REOP, a 1-bit errored packet signal RERR, and a 1-bit start transfer signal (indicates in-band address) RSX.
It will also be appreciated that the SPI-3 interface includes the following transmit side signals: a 32-bit data signal TDAT, a clock signal TFCLK, a 1-bit transmit enable signal TENB, a 2-bit valid byte config signal TMOD, a 1-bit parity signal TPRTY, a 1-bit start of packet signal TSOP, a 1-bit end of packet signal TEOP, a 1-bit errored packet signal TERR, a 1-bit start transfer signal (indicates in-band address) TSX, a 1-bit selected PHY status signal (Packet Available) STPA, a 1-bit polled PHY status signal with PHY address signal PTPA, a 5-bit direct status signal DTPA, and a 6-bit PHY selection address TADR.
Table 1 illustrates how the receive side of the multipacket interface (MPI) can be mapped into an SPI-3 and vice versa.
Table 2 illustrates how the interface of the transmit side of the MPI of the invention can be mapped into an SPI-3 and vice versa.
Those skilled in the art will appreciate that the NPU 116 includes a buffer which is used to buffer all data. If the NPU were provided with an interface according to the invention, the adaptation layer 114 and buffer 115 would not be needed. The PHY layer device 12 could directly control the buffer in the NPU using the packet length indicator PTPLI and data request PDREQ signals to effect flow control between the PHY layer device and the link layer device.
The device 114 supports thirty-two ports at both the TPI interface 10 and SPI-3 interface 117 and it is compliant with the OIF SPI-3 standard for the SPI-3 interface. The TPI interface 10 operates at 100 MHz, 32-bit data, full duplex, and is a timing slave to the device 12 (
Each PHY_Port is allocated a minimum 256 bytes of the FIFOs 114c, in both receive and transmit directions. To support a chunk size of 256 bytes, in the SPI-3 mode, it is recommended that each RX/TX Port Interface FIFO be at least 256×1.25=320 bytes. In the SPI-3 interface, programmable Chunk (burst) sizes of 64/128/256 bytes are supported. This is preferably a user configuration option for the entire interface. Only Slave (PHY) timing mode is supported for SPI-3. The interface operation is in accordance with the Single-PHY/Multi-PHY operational timing diagrams as presented in Sections 10, 10.2 and 11, 11.2 of “System Packet Level Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices OIF-SPI-3-01.0, June 2000”.
PTPA, DTPA, and STPA signals are deasserted during a transmit side FIFO error in the SPI-3 interface. The SPI-3 clock source is preferably selectable from either a local 100 MHz+/−50 ppm oscillator or an external variable clock source. The external variable clock source should be capable of generating a clock frequency range of 50 to 125 MHz.
The DDR SDRAM interface controller and Address generator 114b is capable of maintaining independent nonblocking queues in an external DDR SDRAM memory (not shown) for all of the thirty-two ports. The Address Controller 114b should be able to control an external memory having a minimum of 4 Mbytes.
Packets from the SPI-3 ports are mapped 1:1 to a corresponding MPI interface port. The device 114 does not terminate any un-errored user data packets, except as determined by the SPI-3 interface. The device 114 supports one standard SPI-3 interface. The signals described in Tables 1 and 2 as being supported are supported in the device 114.
Note that in the preferred embodiment of the invention DTPA support is not a requirement; hence, provisioning for the DTPA[3:0] pins is optional. Also the REOP or TEOP signals could indicate either End of Packet, or Block Available (length of block (chunk) programmable), to be able to Receive/Transmit long messages.
In the SPI-3—MPI adaptation FPGA, the SPI-3 interface is connected with a Link Layer device and the MPI is connected with a PHY Layer device in a Point to Point configuration.
The SPI-3 interface 117 is lead pin configurable to either Link (master) layer mode or PHY (slave) layer mode. However, in one embodiment of the invention, only the Slave mode is supported. Each interface (Transmit and Receive) is optionally configurable individually, hence there are two optional configuration lead pins.
Within a byte the MSB (bit 7) is the first bit to be transmitted. The Base Port address is programmable using a 3 bit offset. Individual Port addresses are unit increments from the Base Port address. The complete address range is 0 to 255. The transfer-control provides both packet-level transfer mode and byte-level transfer mode in MultiPHY mode. In Single PHY mode the transfer-control is byte-level transfer. However, if desired, only the packet-level transfer (PTPA) and byte level transfer based on selected port (STPA) need be supported.
In PHY mode, a space availability indication per channel using Polled Transmit Packet Available (PTPA) is asserted when a configurable number of bytes “nbytes1” or more, are available for storage in the Egress FIFO 114c. The de-assertion of PTPA is based on nbytes2 which indicates the number of bytes available for storage in the Egress FIFO. The values of nbytes1 and nbytes2 are programmable to 32, 64, 128, 256, 512 or 1024 bytes. Only one configuration applies for the whole interface. A space availability indication per channel using Selected Transmit Packet Available (STPA) is asserted when a configurable number of bytes “nbytes3” or more, are available for storage in the Egress FIFO 114c. The de-assertion of STPA shall be based on nbytes4 which indicates the number of bytes available for storage in the Egress FIFO. The values of nbytes3 and nbytes4 are programmable to values from 0 to 256 bytes in multiples of 8. Only one configuration applies for the whole interface.
In PHY mode and in the Receive direction (SPI-3 out) one of the channels is selected for packet transfer, based on a first available first serve, round robin algorithm. The device 114 will round robin to the next channel once the selected channel transfers an end of packet (EOP) signal or, if configured, when the selected channel transfers a programmed number of bytes. This latter case is termed Receive Burst Mode. The values of the receive burst sizes are 64, 128, 256, 512, and 1024. If configured in Receive Burst Mode, a reselection will occur when an end of packet is encountered, and the number of bytes transferred is less than the receive burst size. A block of packet data equal to the burst size is termed a chunk. Packet availability for a channel is recorded internally when either a complete packet has been stored (indicated by reception of an end of packet) or, if configured in Receive Burst mode, when a chunk of packet data equal to the burst size is stored in the channels Egress FIFO. A programmable pause of 0 or 2 cycles between transfers is implemented.
Odd, Even, or No Parity is generated and checked across the data bus. Minimum Packet size is 2 bytes. In SPI-3 Single PHY port mode, there is no port selection process using the RSX or TSX signal and the in-band address is configurable to Single PHY mode when configured in both Link/Master mode and PHY/Slave mode.
The device 114 is configurable to work in Single PHY mode and Port Aggregation mode. In Single PHY mode, the STPA signal is used in place of the DTPA signal as applicable, and defined in the standards.
The control interface 114e provides the following information to the Microprocessor block while in PHY mode: SPI-3 transmit start of packet error event and start of packet error counter (32-bits wide); SPI-3 transmit parity error event and parity error counter (32-bits wide); SPI-3 transmit packet error event and packet error counter (32-bits wide); SPI-3 transmit overflow status counter (transmit overflow condition occurs when a PHY device (12 in
Packets violating the (configurable) minimum packet size at the SPI-3 interface are discarded and counted. In PHY mode the above errors are Transmit SPI-3 errors and in Link mode are Receive SPI-3 errors. In Link mode the overflow status is indicated when the RENB is de-asserted and RVAL is asserted. The same counters are used in both modes (PHY or Link).
The DDR SDRAM memory controller 114b generates addressing for each Data Port (total of 32 ports). The interface 114f clocking is synchronous to the MPI interface 10. The SPI-3 interface FIFOs 114c are provided for both the PHY to LINK and the LINK to PHY directions; whereas, external DDR memory (not shown) is provided for only the LINK to PHY direction. This is because the PHY always pushes data to the link; and in the event that RENB signal is asserted by the Link Layer, there is data loss coming from the PHY. The interface 114f supports at least a 2×2.5 Gbps=5 Gbps combined Read/write bandwidth, plus overhead as needed. To minimize access delays, burst read/write is employed, with the minimum burst size equal to the smallest configurable Chunk size (64 bytes). There preferably is a configurable option to bypass the external memory in the LINK to PHY direction.
The DDR SDRAM interface 114f is preferably fully supported via dedicated resources for I/O, timing, and digital phase locked loops or delay locked loops.
When the SPI-3 interface operates off a different clock (50-125 MHz) with regard to the MPI interface, it is possible for the PHY interface to backpressure the Link Layer (in the Link Layer to PHY direction), via a combination of the PTPA/STPA signals asserted by the PHY, and the TENB signal asserted by the Link Layer. The PTPA and STPA signals derive from the usual Interface FIFO fill levels.
The read and writes to the memory (115 in
The device 114 has three main clocking domains: the MPI interface clock domain at 100 MHz (includes 114a, 114b, 114f, and part of 114c); the SPI-3 interface clock domain at any frequency between 50-125 MHz (includes 114d and part of 114c); and a Control Interface clock domain, controlled by the microprocessor interface clock 114e.
A special case of interest in the SPI-3 interface clock domain is the 100 MHz clock, in which case, it is possible to set up the operation such that the timing reduces to a synchronized case for the whole Data Path, including the intervening interface memory/interface FIFOs. However, in general, the timing domains for the MPI interface and the SPI-3 interface are separate and distinct, with the memory and the interface FIFOs serving as the clock domain boundary.
Those skilled in the art will appreciate that the Utopia-3 interface has the following receive side signals: a 32-bit data signal RDAT, a clock signal RCLK, a 1-bit receive enable signal RXENB, a 1-bit parity signal RXPRTY, a 1 bit start of cell signal RxSOC, a 4-bit cell available signal for direct reporting RXCLAV, and a 6-bit address signal for polling RXADDR.
On the transmit side, the Utopia-3 interface has the following signals: a 32-bit data signal TDAT, a clock signal TCLK, a 1-bit transmit enable signal TXENB, a 1-bit parity signal TXPRTY, a 1-bit start of cell signal TxSOC, a 4-bit cell available signal for direct reporting TxCLAV, and a 6-bit address signal for polling TXADDR.
Before turning to the timing diagrams, it should be explained that the interface according to the invention may be operated in three modes: transparent mode, monitoring mode, and termination mode. These modes are with respect to the functions performed by the PHY layer device.
In the transparent mode the decapsulated traffic goes directly out to the multipacket interface 10. Only octet boundaries are guaranteed. The SOF and EOF signals mark octet boundaries. Frame delineations have to be accomplished outside the device 12 which incorporates the multipacket interface 10.
In monitoring mode the frame delineations are done internal to the device 12, but the LAPS (Link Access Protocol for SDH)/PPP (Point to Point Protocol)/BCP (Bridge Control Protocol) or GFP payload headers are not discarded, and the SOF signal lines up with the start of the payload/protocol headers. This effectively results in non-intrusive monitoring of the LAPS/GFP frame, which is passed through unterminated. The core header in case of GFP is however discarded.
In termination mode the frame delineation is done internal to the device 12, but the LAPS/PPP/BCP or GFP headers are discarded, and the SOF signal lines up with the start of the terminated, decapsulated PDU.
These modes of operation are selectable via an application programming interface (API). For purposes of the interface behavior, it is the alignment/relationship of the SOF signal that is of interest. The following notations will be used in the remaining discussion of the interface.
“n”: The number of mapping and demapping processes, or channel numbers, are referred to as “n”. The individual process can be for mapping an Ethernet frame, a packet or a block coded tributary. According to the illustrated embodiment, there are up to twenty-four channels.
“s”: The number of STS-1/VC3s (one VC-4 is treated as bandwidth capable of carrying 3 VC-3s) which can be terminated for mapping and demapping processes within the core. According to the presently preferred embodiment s has a value of 0 to 47.
“q”: The number of GFP framing adaptation processes are numbered as “q”. For a linear extension header the number “q” and “n” may be different.
“PHY”: A physical channel which is capable of carrying an Ethernet frame or PPP packets.
The receive side of the interface 10 sends m bytes over n channels from the PHY layer 12 device to the link layer device 14. Byte slots are assigned in the 32-bit data path PRDAT according to m*8+7 to m*8. In other words: Byte #3 is assigned bits 31-24, Byte #2 is assigned bits 23-16, Byte #1 is assigned bits 15-8 and Byte#0 is assigned bits 7-0. The PRDATVAL signal has m lines, one for each Byte in the 32-bit data path. PRDATVAL goes high when a valid byte is on the data path. The PRSOF signal also has m lines which go high marking the start of frame (when occurring on the mth byte) for Ethernet and start of packet for PPP except for the case of transparent GFP mapping and transparent Mapping. PREOF has m lines which go high marking the End of Frame (when occurring on the mth byte) for Ethernet and end of packet for PPP except for transparent GFP mapping and transparent mapping. PRABT has m lines which go high for marking a corrupt Frame/Packet received (when occurring on the mth byte) and should be aborted. These lines are active only with the respective PREOF m signal and are not active in case of GFP transparent/generic transparent mapping. PRCHNUM has 5-bits indicating which of twenty-four logical channel outputs is being sent out on the 32-bit PRDAT. PRSSF goes high when the SONET server signal fails or GFP/HDLC framing errors appear on output packet(s). PRSSF is not qualified with PRDATVALm; however, PRSSF is qualified with the PRCHNUM corresponding to the particular channel ‘n’. For reporting channel alarms, PRCHNUM have to be interpreted with the PRDATVALm (needs to be high), together with the respective PRAB™ indicating FIFO overflow (or other error conditions) which are reported as an alarm. No action based on the alarm is taken within the device 12.
The minimum packet size transferred across the interface is 2-bytes long (corresponding to consecutive SOF and EOF indications. Note the difference between the Receive and Transmit directions. In the RX direction, two PDUs need to be separated by at least a single invalid byte (since SOF alignment is not done by buffering in the RX side within the PHY layer device); therefore, separate instances of EOF/SOF and DATVAL per byte is required. Each PRSOFm assertion has a corresponding unique PREOFm′ assertion (m may or may not equal m′). In other words, a frame may start in the Byte #1 location of the data path and end in a different Byte # location.
All valid payload bytes (including errors) are passed out onto the data bus along with the applicable PRDATVALm signal asserted. PRAB™ is asserted along with the PRDATVALm and PREOFm. When an internally generated SONET/SDH trail failure signal is active, the PRDATVALm remains inactive and no data is transferred across RX part of the interface 10. During a transfer of a PDU/packet/frame across the interface, if the internally generated SONET/SDH trail failure signal is asserted, the packet being transferred is aborted, except for transparent mapping. In case of transparent mappings, the data valid signal PRDATVALm is disabled. PRSSF is asserted for transparent mapping as well as framed mapping in GFP as shown by logical equation (max[q]=max[n] for GFP Null Mode; however, max[q]<max[n] for GFP Linear Mode).
The transmit side of the interface 10 sends m bytes over n channels from the link layer device 14 to the PHY layer device 12. Byte slots are assigned in the 32-bit data path PTDAT according to m*8+7 to m*8. In other words: Byte #3 is assigned bits 31-24, Byte #2 is assigned bits 23-16, Byte #1 is assigned bits 15-8 and Byte#0 is assigned bits 7-0. The PTDATVAL signal has m lines, one for each Byte in the 32-bit data path. PTDATVAL goes high when a valid byte is on the data path. The PTSOF signal also has one line which goes high marking the start of frame for Ethernet and start of packet for PPP except for the case of transparent GFP mapping and transparent Mapping. Note that in the transmit direction, a single PTSOF is enough. This is because (1) at least one PTDATVALm has to be active for at least one byte duration in between consecutive to-be-transmitted PDUs, and (2) a frame that includes an SOF and EOF indication on two consecutive bytes corresponds to a special case of an errored or aborted frame. For this special case, an SOF or EOF indication does not appear on the interface, however, the condition is internally decoded. PTEOF is a single line which goes high for marking the end of frame for Ethernet and end of packet for PPP (except for the case of transparent GFP mapping and transparent mapping). Note that in the transmit direction a single PTEOF is enough. This is for exactly the same reason that only a single PTSOF is enough. PTABT has a single line that goes high for aborting the mapping of the current input frame and is valid only for the case of framed GFP, PPP/HDLC, transparent HDLC and LAPS X.85 mapping. The PTABT signal is aligned with the PTEOF signal and both occur on the same cycle of PCLK2. PDREQ is a single line output from the PHY layer device to the link layer device indicating data is required for the channel indicated by PTCHNUM which is a five line output from the PHY layer device to the link layer device. The delay between the PTCHNUM signal and the return data over the PTDAT/PTSOF is 7 clock cycles (PCLK2). The PTCHNUM signal leads the PDREQ signal by three clock cycles (PCLK2). Thus, the delay between the PDREQ signal and the return data over the PTDAT/PTSOF is 4 clock cycles (PCLK2). PTPLI (the sixteen bit wide incoming PDU length indicator that can indicate a length of up to a 64K-byte) lines up with the PTSOF signal. The minimum sized frame transferred across the packet Interface is at least 2-bytes long for all cases. In case of a mismatch between the states of the PTPLI bits and PTEOF, the PTPLI value overrides the PTEOF indication. For a given data request via the PDREQ, if PTDATVALm is not asserted (with the respective mth bytes) without an immediately preceding PTEOF indication, then this indicates an external FIFO underflow condition and the appropriate error management action for the input PDU of interest is implemented.
PTDAT, PTSOF, PTEOF, and PTABT are ignored when PTDATVALm is inactive. Request for data for a channel is generated ahead of time when it needs to be mapped. The packet is aborted when PTABT, PTDATVALm and PTEOF are asserted simultaneously. If the signal PTABT is asserted without PTEOF or PTDATVALm being asserted, it is ignored. When a data request is generated for a channel, and no data is provided, and no current packet/frame transmission is in progress, then an indication is provided to the mapper to insert idle/fill characters as per the configuration. This occurs inside the PHY layer device 12. When a data request is generated for a channel, and no data is provided, and a current frame is being transmitted then the frame transmission for that channel is aborted. The payload is inserted with idle/fill characters until a PTSOF is asserted for the channel upon a data request.
Referring now to
From the foregoing, it will be appreciated that the multipacket interface provides direct access to PDU Encapsulation (framing) channels and corresponding SONET VCGs are made available to any kind of Standards based/Proprietary LINK Layer—PHY layer interface via an appropriate Adaptation Layer, that allows users greater flexibility in using the PDU Framing channels and the SONET VCGs. The MPI also allows GFP Framing on PDUs without having to buffer payload, thereby adding to latency. The multipacket interface allows optimal operation with respect to external Network Processors which already buffer payload. The interface is designed for adaptation to SONET/SDH, and allows robust framing for any generic PDU, of arbitrary length, with a fully deterministic adaptation overhead. It also allows the interface to be used by multiple types of PDUs on different channels on the same interface simultaneously. This facilitates Multi-service Aggregation applications, admitting mixed traffic for mapping into a common transport layer. An example of such a mixed application could be simultaneous mapping of ATM and Packet traffic requiring completely different and incompatible standard based physical interfaces—such as UTOPIA-2 and SPI-3.
There have been described and illustrated herein several embodiments of a multipacket interface. While particular embodiments of the invention have been described, it is not intended that the invention be limited thereto, as it is intended that the invention be as broad in scope as the art will allow and that the specification be read likewise. Thus, while a particular clock speed and data path width have been disclosed, it will be appreciated that other speeds and widths could be used. Also the five bit channel identifier is presently preferred but could be a different number of bits in a different embodiment having more or fewer channels. In addition, while the adaptation devices have been described as ASICs or FPGAs, it will be understood that a general purpose processor could be used. Also, additional pins could be provided in one or both directions to support other features such as parity for example. It will therefore be appreciated by those skilled in the art that yet other modifications could be made to the provided invention without deviating from its spirit and scope as claimed.
