Patent Application
20060251197
Not applicable.
Not applicable.
This invention is in the field of digital signal processing, and is more specifically directed to digital signal processing in digital audio systems, such as digital receivers, that support multiple audio sources.
In recent years, digital signal processing techniques have become prevalent in many electronic systems. Tremendous increases in the switching speed of digital circuits have enabled digital signal processing to replace, in large part, analog circuits in many applications. For example, the sampling rates of modern digital signal processing are sufficiently fast that digital techniques have become widely implemented in audio electronic applications. These digital audio signal processing techniques now extend even to the driving of the audio output amplifiers.
As a result of these advances in digital audio amplifiers, and advances in digital signal processing generally, audio-visual receivers can now be realized nearly entirely in the digital domain. To the extent that audio signals remain to be processed, these digital receivers can convert any received analog audio input signals to digital form, and process the corresponding signals in a similar manner as the other digital audio signals in the system.
Modern digital audio-visual receivers and digital audio receivers are typically required to be capable of receiving audio input from a wide variety of sources. For example, a typical digital audio amplifier can receive, process, and amplify audio signals from an AM/FM radio tuner (which may be built into the receiver), analog line-in inputs to receive analog audio from an external source, optical or other digital line-in inputs to receive audio signal from a satellite or cable television source, digital audio signals from a CD player, and still other sources. Because these digital receivers process the audio signals in the digital domain, the incoming audio signals must be either received in digital form, or converted from analog signals to digital signals. In either case, the resulting digital representation of the audio signals to be processed is in the form of a datastream of digital words (typically sixteen, twenty, or twenty-four bits in width), each digital word having a value corresponding to the amplitude of a sample of the audio signal at a sample point in time. Inherently, therefore, the digital audio signal datastreams are at a sampling frequency, which is the rate at which the digital samples are applied at the input to the digital audio signal processing circuitry.
As is well known in the art, these multiple digital audio signal sources generate digital output at different sampling frequencies relative to one another. Common digital audio sampling rates are 32 kHz, 44.1 kHz, and 48 kHz. For example, CD players and MP3 players typically generate 44.1 kHz datastreams, while DVD players typically generate digital audio at the 48 kHz sampling frequency. And higher-performance digital recordings at a sampling frequency of 96 kHz are now also being produced. Accordingly, modern digital audio receivers, and digital audio-visual receivers, must have the capability of handling digital audio signal datastreams at multiple sampling frequencies.
In addition, in digital audio receivers that drive so-called “class D” digital outputs, it is known that the frame rate of the pulse-width-modulated class D output switching can cause interference with AM tuner reception; specifically, this PWM frame rate can interfere with the AM tuned frequency itself, with intermediate frequencies generated in AM demodulation, or in image frequencies resulting from AM demodulation. For digital audio receivers that generate the PWM frame rate at a frequency multiple of the input sampling frequency, it is known that this AM interference from the PWM frame rate can be avoided by changing the sampling frequency of the digital audio signal for different AM tuned frequencies, to keep the PWM frame rate and its harmonics at frequencies away from the frequencies involved in AM demodulation.
However, the parameter of sampling frequency is an important parameter in many digital signal processing operations for audio applications. As is fundamental in the digital audio processing art, the infinite impulse response (IIR) digital filter is an important type of digital filter that is commonly used in audio processing. The second order IIR digital filter, commonly referred to as a “biquad”, is a popular IIR building block, and can be cascaded to provide very high order digital filter functions at low cost and high efficiency. For example, conventional digital audio processing devices, such as the TAS3103 digital audio processor available from Texas Instruments Incorporated, include on the order of twelve biquad IIR filters per audio channel to provide graphic equalization, speaker parameter equalization, phase compensation, and the like; additional biquads are used in bass and treble control, and other audio functions.
Biquads can be readily executed by programmable circuitry, such as a digital signal processor (DSP), or by a custom hardware architecture. For example, U.S. Patent Application Publication US 2005/0076073, entitled “Biquad Digital Filter Operating at Maximum Efficiency”, assigned to Texas Instruments Incorporated, provides an excellent description of a biquad architecture, for use in digital audio signal processing.
By way of background,
y(n)=b0·x(n)+b1·x(n−1)+b2·x(n−2)+a1·y(n−1)+a2·y(n−2)
where the sample indices n−1, n-2 refer to previous values of the input and output datastreams. Referring to
As is also fundamental in the art, the desired frequency response characteristics of the biquad filter is determined by the values of the coefficients a0, a1, a2, b0, b1, b2; indeed, the frequency response characteristics of any digital filter, of either IIR or FIR form, is determined by its coefficient values. Conversely, the shape of the desired particular frequency response, such as low-pass, high-pass, band-pass, notch, and the like, and the characteristic frequency f0 (i.e., the center, corner, midpoint, or other frequency of interest) of the filter, determine the values of these filter coefficients. However, as is also well known in the art, these filter coefficients do not depend only on the characteristic frequency f0 in the absolute, but instead typically depend on a ratio of the characteristic frequency f0 to the sampling frequency fs of the datastream.
In practice, the frequency response characteristics, including the characteristic frequency f0, of the digital filters applied in digital audio processing correspond to the desired audio output signal (e.g., in graphic equalization, treble and bass control, etc.), as either selected by the human listener or by the system designer. In other words, the desired frequency response of the digital filter is independent of the sampling frequency. But, as mentioned above, different audio signal sources present digital audio signals at different sampling frequencies; in addition, also as mentioned above, the sampling frequency fs may be adjusted to avoid interference effects. The frequency response and characteristic frequency f0 of the digital filters are independent of sampling frequency, and therefore do not change if the sampling frequency fs is changed. Because the characteristic frequency f0 remains fixed, the values of the filter coefficients a1, a2, b0, b1, b2, etc. must therefore be changed if the sampling frequency fs changes.
It has been observed, in conventional digital audio receivers, that the changing of filter coefficients with a change in sampling frequency fs is a cumbersome operation.
Digital audio processor 13 is a conventional integrated circuit for processing the selected audio signal by applying digital filters for equalization and other purposes, as discussed above, as well for performing other processing such as input and output crossbar mixing and switching, applying 3D effects, and the like. An example of conventional digital audio processor 13 is the TAS3103 digital audio processor mentioned above. Digital audio processor 13 applies its output as pulse-code-modulated (PCM) digital signals, one per channel, to audio amplifier 15. Audio amplifier 15 amplifies and formats the PCM audio signals into signals that drive power stages 171 through 174, each associated with one of the audio channels. Power stages 171 through 174 in turn drive speakers SPKR_1 through SPKR_4. In modern digital audio systems, audio amplifier 15 is a digital audio amplifier, and as such may also include additional digital filtering functions, as well as a pulse-width modulator to generate pulse-width-modulated control signals for application to power stages 17, driving speakers SPKR in a class D fashion.
In the conventional system of
It is therefore an object of this invention to provide a digital signal processor that can efficiently process input signals at various sampling rates.
It is a further object of this invention to provide such a processor that is especially well-suited for digital audio processing.
Other objects and advantages of this invention will be apparent to those of ordinary skill in the art having reference to the following specification together with its drawings.
The present invention may be implemented into a digital signal processor, such as a digital audio processor or the like, that applies digital filters and performs other digital signal processing on digital data received at one of multiple sampling frequencies. The processor includes memory banks, each of which stores a set of digital filter coefficients for an associated one of the multiple sampling frequencies at which the input data is being received. The memory banks are accessible by the circuitry, in the processor, that executes the digital filters, or other functions utilizing coefficients that have values dependent on the sampling frequency. Preferably, circuitry is provided that automatically detects the sampling frequency of the input signal. The associated memory bank associated with the sampling frequency of the input signal is then selected to provide the filter coefficients and other parameters to the processing circuitry.
a and 6b are representations of the contents of registers in the digital audio processor of
The present invention will be described in connection with its preferred embodiment, namely as implemented into a digital audio receiver, as it is contemplated that this invention will be especially beneficial in such an application. It is further contemplated, however, that this invention may prove advantageous in many other digital signal processing applications in which the sampling frequency of the input digital signal can change. Accordingly, it is to be understood that the following description is provided by way of example only, and is not intended to limit the true scope of this invention as claimed.
Referring now to
In a general sense, digital audio PWM processor 20 includes digital audio processing function 20d and pulse-width-modulation (PWM) function 20p. In general, digital audio processing function 20d digitally processes digital audio signals according to a sequence of functions including digital mixing, channel equalization, treble and bass control, soft volume, loudness compensation, dynamic range compensation, and the like. As mentioned above, and as will be described in further detail below, these digital audio processing operations are typically executed by way of digital filters. The output of digital audio processor 20d is forwarded to PWM function 20p, for example in the form of pulse-code-modulated (PCM) digital words. PWM function 20d converts the PCM digital audio signals at its inputs to corresponding pulse-width-modulated (PWM) output signals. In this example, PWM processor 20p produces, for each of the four supported channels, separate PWM control signals that are applied to a corresponding power stage 221 through 224, each of which drives a respective one of loudspeakers SPKR_1 through SPKR_4. Of course, more or fewer audio channels may be driven by receiver 21. In a simple stereo arrangement, only two channels may be processed; alternatively, as many as eight audio channels are now commonly handled by digital audio-visual receivers such as receiver 21. The number of channels supported and utilized by receiver 21 is a matter of choice for the designer and the user.
According to this embodiment of the invention, digital audio PWM processor 20, including both of the functions of digital audio processor 20d and PWM function 20p, along with the appropriate support controller and other circuitry, is preferably realized in a single integrated circuit. Alternatively, the two functions of digital audio processor 20d and PWM function 20p may be realized in separate integrated circuits from one another. In either case, it is contemplated that those skilled in the art, having reference to this specification including the detailed description of the construction and operation of digital audio PWM processor 20 provided below, will be able to realize this invention in a suitable manner for a specific application, without undue experimentation.
As mentioned above, system controller 30 provides audio source selection signals to multiplexer 16. In addition, system controller 30 provides channel volume control signals to PWM function 20p in digital audio PWM processor 20, and provides other control signals throughout receiver 21, including channel selection control to tuner 15 in response to user inputs received via front panel 25 or infrared receiver 27. According to the preferred embodiment of this invention, system controller 30 also provides multiple sets of digital filter coefficients to digital audio PWM processor 20, upon reset or power up of receiver 21 (or digital audio PWM processor 20 in receiver 21). These multiple sets of digital filter coefficients are stored in digital audio PWM processor 20, for use in applying digital filters to digital audio data of varying sample frequencies fs. In addition, control signals or data are provided by system controller 30 to digital audio PWM processor 20, over control channel CTRL_CH, to associate the multiple sets of coefficients with the appropriate sample frequencies, for manual switching among these coefficient sets, and to enable automatic switching, all as will be described in further detail below.
Referring now to
As shown in the example of
The construction of digital signal processing channel 441 will be described in detail, by way of example. It is contemplated that some or all of digital signal processing channels 44 are identically configured, although one or more of channels 44 may have special functionality, such as in the case of an extremely low bass channel for driving a sub-woofer, or in the case of a rear channel in a surround-sound system. According to this embodiment of the invention, biquad block 45 is first applied to the input digital audio signal from mixer 42. Biquad block 45 includes a series of biquad, second-order IIR, digital filters, executable in cascade. In this example, as many as seven biquad stages, implementing a digital filter of up to the fourteenth order, are implemented in cascade within biquad block 45. Biquad block 45 is useful for many audio processing functions, including such functions as parametric speaker equalization or “voicing”, implementation of graphic equalizer presets, and the like. Treble/bass function 46 receives the output of biquad block 45, and applies treble and bass adjustment as selected by the user or under program control, via controller 40. It is contemplated that treble/bass function 46 may also be implemented by cascaded biquads. The remainder of digital signal processing channel 441 includes soft volume block 47, which implements a precision soft volume control on the audio signal being processed for its channel. Loudness compensation block 48 applies a volume-dependent spectral shape on the audio signal, boosting bass frequencies when the output for the channel is low. Dynamic range compression (DRC) function 49 also shapes the spectrum of the output signal according to a linear frequency relationship, with the slope selected under user or program control via controller 40.
Additional signal processing functions, which are not shown in
It is contemplated that the signal processing functions of digital signal processing functions are preferably implemented as software routines executable by a digital signal processor (DSP) integrated circuit or core, having sufficient capability to execute the desired operations at the necessary data rate. In this implementation, program and data memory resources are provided either within the DSP integrated circuit, or external to and accessible by the DSP integrated circuit or core. It is contemplated that DSP circuitry such as described in U.S. Patent Application Publication US 2005/0076073, entitled “Biquad Digital Filter Operating at Maximum Efficiency”, assigned to Texas Instruments Incorporated, and incorporated herein by this reference, is an example of a suitable hardware architecture according to the preferred embodiment of the invention. Of course, custom or semi-custom logic circuitry may also be used to perform these operations within digital audio processor 20d.
Output crossbar 50 receives each of the digital output data streams from digital signal processing channels 441 through 44m, and routes the processed channels to the desired inputs of PWM function 20p in this example. Typically, the outputs of digital audio processor 30 are digital serial outputs, in PCM format as mentioned above. Output crossbar 50 thus permits programmable or user control of the assignment of channels to outputs, enabling a wide degree of freedom in the operation of the audio system.
Controller 40 in digital audio PWM processor 20 controls the operation of digital audio PWM processor 20 in response to predesigned control code and in response to user inputs. Controller 40 is preferably realized by way of programmable logic of a suitable architecture for executing these control functions and the particular functions described herein in connection with the preferred embodiment of the invention. The general control functions performed by controller 40 in controlling the operation of digital audio PWM processor 20 will not be described in detail, it being understood that those skilled in this art having reference to this specification will be readily able to implement such control functionality, without undue experimentation. In addition, clock circuitry 52 is also provided in digital audio PWM processor 20, to receive certain external clocks such as sample clock SCLK, a master high-speed clock (not shown), and other clocks used within receiver 21, and to generate the necessary clock signals for use internally to digital audio PWM processor 20 to effect its operations. It is therefore contemplated that clock circuitry 52 will include such clock circuit functions such as analog or digital phase-locked loops (or both), timer circuits, frequency dividers, and the like.
According to this embodiment of the invention, clock circuitry 52 also includes sample rate detector circuit 54, which detects the frequency of sample clock SCLK and thus the sampling frequency fs of the digital data received by digital audio PWM processor 20. In this example, sample rate detector circuit 54 includes a time base reference, for example a crystal oscillator, connected to external crystal XTL, for generating a reference frequency used in the detection of the frequency of sample clock SCLK. Those skilled in the art having reference to this specification will recognize alternative approaches to producing this time base reference time. External sources of periodic signals, such as any analog or digital circuitry capable of producing a periodic signal, may be used. The time reference may alternatively be produced internally to digital audio PWM processor 20 by way of analog or digital resonant circuitry such as a PLL or other periodic operating logic. Sample rate detector circuit 54 may be constructed to include a counter that counts cycles of sample clock SCLK relative to the reference clock based on external crystal XTL, and logic that generates output control signals to controller 40 based on the results of this relative counting, such control signals indicative of the frequency of sample clock SCLK relative to the reference clock.
It is contemplated that sample clock SCLK or a clock signal derived from sample clock SCLK will be provided to digital audio processor 20, considering that at least some of the operations of digital audio processor 20 must be carried out at sampling frequency fs. In the alternative, however, digital audio processor 20 may include circuitry for recovering a sample clock from the transitions of the incoming datastream itself, in which case an externally applied sample clock SCLK need not be applied to digital audio processor 20.
Also, according to this preferred embodiment of the invention, multiple coefficient memory banks 55 are provided, for storing sets of digital filter coefficients. In this example, three coefficient banks 550 through 552 are available in digital audio PWM processor 20. Each coefficient bank 55 contains sufficient memory for storing coefficient values for each of the digital filter functions within digital signal processing channels 44, for one or more sampling frequencies fs. For the example of digital audio processor 20d of
Association of sample rates with coefficient banks 550 through 552, and the selection of the desired one of coefficient banks 550 through 552, is effected by controller 40 in various ways, according to the preferred embodiment of the invention. Controller 40 includes bank control register 41, by way of which selection of a manual or automatic bank switching mode can be selected, preferably by system microcontroller 30 writing a control word over I2C control channel CTRL_CH. For automatic bank switching operation, rate select registers 43 can be written by system microcontroller 30, also over I2C control channel CTRL_CH, with the desired association of selected ones of coefficient banks 550 through 552 with particular sampling frequencies fs. As mentioned above, controller 40 also effects the storing of coefficient values in coefficient banks 550 through 552 during power-up or reset, with the values being communicated from system microcontroller 30 over I2C control channel CTRL_CH. And as will be described below, these coefficient values in coefficient banks 550 through 552 can also be updated by system microcontroller 30 over I2C control channel CTRL_CH, after power-up and during operation.
The operation of digital audio PWM processor 20 in utilizing the appropriate coefficient values, for digital filter and other coefficients that have values dependent on the sampling frequency fs, and according to the preferred embodiment of the invention, will now be described relative to
Power-on and reset, or a powered reset, of digital audio PWM processor 20 occurs in process 50, and according to this embodiment of the invention, begins initialization of the coefficient values stored in coefficient banks 550 through 552. In process 52, therefore, system microcontroller 30 forwards the coefficient values for the multiple coefficient banks 550 through 552 to digital audio PWM processor 20 over I2C control channel CTRL_CH. In turn, controller 40 of digital audio PWM processor 20 stores these values in the addressed locations of coefficient banks 550 through 552. Because digital audio PWM processor 20 is powering up at this time and therefore time-critical operation has not yet begin, the time required for transmittal of these values over control channel CTRL_CH can be tolerated.
In process 64, system microcontroller 30 forwards data rate association information to digital audio PWM processor 20 over control channel CTRL_CH, for storage in bank select registers 43.
Alternatively, if no bank select association values are provided by system microcontroller 30, default values are stored in bank select registers 43. An example of a default setting is to place set all bits in bank select register 430, and clear all bits in bank select registers 431, 432. This will cause digital audio PWM processor 20 to use coefficient bank 550 for all values of sampling frequency fs. Further in the alternative, or in addition, simple logic circuitry can effect the writing of default bit states into third bank select register 432 in response to the writing of any association data in either of bank select registers 430 or 431, for example by exclusive-OR of the states of the corresponding bits of bank select registers 430 or 431 (so that a “0” in the same bit position of bank select registers 430 or 431 forces a “1” state in that bit position of bank select register 432. This ensures that each of the available sample rates will have a coefficient bank 55 associated therewith. Other implementations that link coefficient banks 55 with one or more sample rates may alternatively be employed, as desired.
According to the preferred embodiment of the invention, digital audio PWM processor 20 can operate in a manual coefficient value bank selection mode, or in an automatic mode. System microcontroller 30 controls this selection in process 66, by writing a control sword to bank control register 41 in controller 40, again over control channel CTRL_CH.
Various arrangements of registers 41, 43 are contemplated. For example, while registers 41, 43 are shown in this description as being separate registers relative to one another, it is also contemplated that bank control register 41 and bank select registers 43 may be combined into one long register. Those skilled in the art having reference to this specification will be able to readily arrange these control registers in a manner optimized for each particular implementation of the invention.
Referring back to
On the other hand, if the automatic mode is selected (decision 67 is AUTO), then the selection of the appropriate one of coefficient bank 550, 551, or 552 is based on the operation of sample rate detector 54. In process 70, sample rate detector 70 measures the sampling frequency fs that is indicated by sample clock SCLK, relative to the reference clock based on external crystal XTL. Once the current sample rate is determined in process 70 and communicated to controller 40, process 72 is next performed by controller 40 to determine the correct one of coefficient banks 550 through 552. According to the preferred embodiment of the invention, process 72 is performed by scanning the corresponding bit position of rate select registers 430 through 432 in sequence, to determine the first register 43 that has its bit associated with the detected sample rate set. For example, rate select register 430 may first be interrogated, and if the bit position for the detected sample rate is not set, then rate select register 431 is then interrogated. The sequential scanning of rate select registers 43 enables the use of a default value of all “1” bits, preferably in the first rate select register 431, to ensure that an association exists for each sample rate, thus avoiding initialization errors. Upon controller 40 finding a match for the detected sample rate, process 74 is then performed to apply the coefficient values in the selected coefficient bank 550, 551, or 552to digital audio processor 20d as described above.
After this initialization, digital audio PWM processor 20 begins performing its desired digital audio signal processing of audio signals, including the applying of digital filters and other functions to each channel of digital audio, using the coefficient values in the selected coefficient bank 550 through 552 for the current sampling frequency.
During the operation of digital audio PWM processor 20, it is contemplated that system controller 30 or another source may wish to update one or more of the coefficient values in coefficient banks 550 through 552. This updating is permitted, according to the preferred embodiment of the invention, in both the manual and automatic mode. According to a preferred embodiment of this invention, the updated coefficient value may be written by system controller 30 over control channel CTRL_CH by forwarding a control word corresponding to bank control register 41, but with the digital values 1002, 1012, 1102 in the M bits indicating an update to coefficient bank 550, 551, or 552, respectively. The updated coefficient values can then be forwarded. Updating of the coefficient banks 55 without switching banks in manual mode, and without vulnerability to data corruption from a clock error or data rate change in automatic mode, is therefore readily accomplished.
Referring now to
In decision 79, controller 40 and sample rate detector 54 determine whether a new sample rate of sample clock SCLK is being received, relative to the previous sample rate. If a new sample rate is not detected (decision 79 is NO), then the association of the current coefficient bank 550, 551, or 552 has not changed, and digital audio can then again be produced after unmuting process 80.
However, if a new sample rate is detected (decision 79 is YES), either by the automatic detection by sample rate detector 54 or by a manual switching of the sample rate by a control word over control channel CTRL_CH, then processes 70 through 74 (
This invention therefore provides important advantages over conventional digital audio processors. Changes in the sampling frequency of the incoming digital audio datastream can now be easily handled, according to this invention, by permitting a simple switch of coefficient banks within the digital audio processor circuit. Downloading of a large number of coefficient values for a different sampling frequency, through a relatively slow data interface such as control channel CTRL_CH, is no longer necessary, as in conventional systems. In addition, the automatic detection of the sampling frequency of the input datastream permits the transparent and automatic selection of the appropriate coefficient values without user or system controller intervention.
While the present invention has been described according to its preferred embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.
