Patent Application
20250238134
Embodiments of the present disclosure generally relate to improving system performance through over-read usage.
When a device is performing a read or write, some of the Transaction Layer Packets (TLP) are not aligned. This can be because the original address was not aligned to 4K or the TLP size. Different components are configured to work in a different manner. An Advanced Extensible Interface (AXI) bus cannot read 12 bytes out of a 16 (or more) bytes wide bus. The bus has to break the total number of bytes into 8 bytes and 4 bytes transactions. The Peripheral Component Interconnect express (PCIe) bus adds overhead for every TLP, so breaking the 12 bytes means twice the amount of header. A switch might be optimized to work at 64 bytes chunks, and every smaller chunk will incur inefficiency. A Direct Memory Access (DMA) controller is optimized to work at 64 bytes alignment. In this case, due to the AXI limitation, the transfers will suffer from multiple inefficiencies.
Additionally, some of the inefficiencies appear not only when working with AXI, but even without AXI when the command data pointers or Physical Region Pages (PRP) are not aligned to 64. In previous approaches, the system suffers from these inefficiencies. Generally speaking, the device issues more PCIe packets in unaligned scenarios (e.g. when metadata is in place) to support host protocol and internal buses. This behavior leads to performance degradation.
Therefore, there is a need in the art for improving over-read usage through system checks for specific system needs.
Instead of handling transaction layer packets (TLP) without over-read usage, utilize adaptive over-read. As TLPs are transferred from the host along the Peripheral Component Interconnect express (PCIe) in the fabric to the device, some performance options are best suited. The fabric prefers bytes read in multiples of 64 bytes, while the PCIe works best in smaller byte chunks. Adaptive over-read allows a device to periodically check a system through testing over-read usage to compare the results for best performance of the system. The system is checked periodically, because different devices in the system can have an effect on the fabric and PCIe that may change performance preferences.
In one embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: receive a write command to write data to the memory device; execute the write command, wherein executing the write command comprises reading more data from a host device than corresponds to the write command; discard the more data; and deliver data corresponding to the write command to the memory device.
In another embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine whether execution of a write command would be an aligned read transfer; determine whether execution of the aligned read transfer is a non host memory buffer (HMB) and has an unsupported request (UR) bit; and determine an age of a last measurement of a range of data for the aligned read transfer.
In another embodiment, a data storage device comprises: means to store data; and a controller coupled to the means to store data, wherein the controller is configured to: operate in a multiple function nonvolatile memory express (NVMe) device (MFND) environment; determine that a first function of the MFND operates without metadata; determine that a second function of the MEND operates with aligned physical region page (PRPs); and perform over read operations for one or more of the first function and the second function.
So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.
In the following, reference is made to embodiments of the disclosure. However, it should be understood that the disclosure is not limited to specifically described embodiments. Instead, any combination of the following features and elements, whether related to different embodiments or not, is contemplated to implement and practice the disclosure. Furthermore, although embodiments of the disclosure may achieve advantages over other possible solutions and/or over the prior art, whether or not a particular advantage is achieved by a given embodiment is not limiting of the disclosure. Thus, the following aspects, features, embodiments, and advantages are merely illustrative and are not considered elements or limitations of the appended claims except where explicitly recited in a claim(s). Likewise, reference to “the disclosure” shall not be construed as a generalization of any inventive subject matter disclosed herein and shall not be considered to be an element or limitation of the appended claims except where explicitly recited in a claim(s).
Instead of handling transaction layer packets (TLP) without over-read usage, utilize adaptive over-read. As TLPs are transferred from the host along the Peripheral Component Interconnect express (PCIe) in the fabric to the device, some performance options are best suited. The fabric prefers bytes read in multiples of 64 bytes, while the PCIe works best in smaller byte chunks. Adaptive over-read allows a device to periodically check a system through testing over-read usage to compare the results for best performance of the system. The system is checked periodically, because different devices in the system can have an effect on the fabric and PCIe that may change performance preferences.
The host device 104 may store and/or retrieve data to and/or from one or more storage devices, such as the data storage device 106. As illustrated in
The host DRAM 138 may optionally include a host memory buffer (HMB) 150. The HMB 150 is a portion of the host DRAM 138 that is allocated to the data storage device 106 for exclusive use by a controller 108 of the data storage device 106. For example, the controller 108 may store mapping data, buffered commands, logical to physical (L2P) tables, metadata, and the like in the HMB 150. In other words, the HMB 150 may be used by the controller 108 to store data that would normally be stored in a volatile memory 112, a buffer 116, an internal memory of the controller 108, such as static random access memory (SRAM), and the like. In examples where the data storage device 106 does not include a DRAM (i.e., optional DRAM 118), the controller 108 may utilize the HMB 150 as the DRAM of the data storage device 106.
The data storage device 106 includes the controller 108, NVM 110, a power supply 111, volatile memory 112, the interface 114, a write buffer 116, and an optional DRAM 118. In some examples, the data storage device 106 may include additional components not shown in
Interface 114 may include one or both of a data bus for exchanging data with the host device 104 and a control bus for exchanging commands with the host device 104. Interface 114 may operate in accordance with any suitable protocol. For example, the interface 114 may operate in accordance with one or more of the following protocols: advanced technology attachment (ATA) (e.g., serial-ATA (SATA) and parallel-ATA (PATA)), Fibre Channel Protocol (FCP), small computer system interface (SCSI), serially attached SCSI (SAS), PCI, and PCIe, non-volatile memory express (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), or the like. Interface 114 (e.g., the data bus, the control bus, or both) is electrically connected to the controller 108, providing an electrical connection between the host device 104 and the controller 108, allowing data to be exchanged between the host device 104 and the controller 108. In some examples, the electrical connection of interface 114 may also permit the data storage device 106 to receive power from the host device 104. For example, as illustrated in
The NVM 110 may include a plurality of memory devices or memory units. NVM 110 may be configured to store and/or retrieve data. For instance, a memory unit of NVM 110 may receive data and a message from controller 108 that instructs the memory unit to store the data. Similarly, the memory unit may receive a message from controller 108 that instructs the memory unit to retrieve data. In some examples, each of the memory units may be referred to as a die. In some examples, the NVM 110 may include a plurality of dies (i.e., a plurality of memory units). In some examples, each memory unit may be configured to store relatively large amounts of data (e.g., 128 MB, 256 MB, 512 MB, 1 GB, 2 GB, 4 GB, 8 GB, 16 GB, 32 GB, 64 GB, 128 GB, 256 GB, 512 GB, 1 TB, etc.).
In some examples, each memory unit may include any type of non-volatile memory devices, such as flash memory devices, phase-change memory (PCM) devices, resistive random-access memory (ReRAM) devices, magneto-resistive random-access memory (MRAM) devices, ferroelectric random-access memory (F-RAM), holographic memory devices, and any other type of non-volatile memory devices.
The NVM 110 may comprise a plurality of flash memory devices or memory units. NVM Flash memory devices may include NAND or NOR-based flash memory devices and may store data based on a charge contained in a floating gate of a transistor for each flash memory cell. In NVM flash memory devices, the flash memory device may be divided into a plurality of dies, where each die of the plurality of dies includes a plurality of physical or logical blocks, which may be further divided into a plurality of pages. Each block of the plurality of blocks within a particular memory device may include a plurality of NVM cells. Rows of NVM cells may be electrically connected using a word line to define a page of a plurality of pages. Respective cells in each of the plurality of pages may be electrically connected to respective bit lines. Furthermore, NVM flash memory devices may be 2D or 3D devices and may be single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), or quad level cell (QLC). The controller 108 may write data to and read data from NVM flash memory devices at the page level and erase data from NVM flash memory devices at the block level.
The power supply 111 may provide power to one or more components of the data storage device 106. When operating in a standard mode, the power supply 111 may provide power to one or more components using power provided by an external device, such as the host device 104. For instance, the power supply 111 may provide power to the one or more components using power received from the host device 104 via interface 114. In some examples, the power supply 111 may include one or more power storage components configured to provide power to the one or more components when operating in a shutdown mode, such as where power ceases to be received from the external device. In this way, the power supply 111 may function as an onboard backup power source. Some examples of the one or more power storage components include, but are not limited to, capacitors, super-capacitors, batteries, and the like. In some examples, the amount of power that may be stored by the one or more power storage components may be a function of the cost and/or the size (e.g., area/volume) of the one or more power storage components. In other words, as the amount of power stored by the one or more power storage components increases, the cost and/or the size of the one or more power storage components also increases.
The volatile memory 112 may be used by controller 108 to store information. Volatile memory 112 may include one or more volatile memory devices. In some examples, controller 108 may use volatile memory 112 as a cache. For instance, controller 108 may store cached information in volatile memory 112 until the cached information is written to the NVM 110. As illustrated in
Controller 108 may manage one or more operations of the data storage device 106. For instance, controller 108 may manage the reading of data from and/or the writing of data to the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 may initiate a data storage command to store data to the NVM 110 and monitor the progress of the data storage command. Controller 108 may determine at least one operational characteristic of the storage system 100 and store at least one operational characteristic in the NVM 110. In some embodiments, when the data storage device 106 receives a write command from the host device 104, the controller 108 temporarily stores the data associated with the write command in the internal memory or write buffer 116 before sending the data to the NVM 110.
The controller 108 may include an optional second volatile memory 120. The optional second volatile memory 120 may be similar to the volatile memory 112. For example, the optional second volatile memory 120 may be SRAM. The controller 108 may allocate a portion of the optional second volatile memory to the host device 104 as controller memory buffer (CMB) 122. The CMB 122 may be accessed directly by the host device 104. For example, rather than maintaining one or more submission queues in the host device 104, the host device 104 may utilize the CMB 122 to store the one or more submission queues normally maintained in the host device 104. In other words, the host device 104 may generate commands and store the generated commands, with or without the associated data, in the CMB 122, where the controller 108 accesses the CMB 122 in order to retrieve the stored generated commands and/or associated data.
The device application initiates a read request (using AXI) which goes through the device endpoint that translates the read request to TLP (PCIe format). The request goes through the PCIe switch and arrives at the host. Inside the host (root complex), the transfer is directed (again using AXI) to the host DRAM controller, which fetches the needed data from the host DRAM. The data then traverses in the opposite direction back to the device application.
The second sector (shaded grey stripes) starts immediately after, so the first 24 bytes are concatenated with the 8 metadata bytes of the first sector, then 16 full lines of 32 bytes each, and finally 8 bytes of data, and 8 more of metadata (black stripes). This causes un-alignment in the memory in regards to a single LBA. The same example can be given for an LBA of 4K, or for metadata of other sizes, or simply for an unaligned PRP (protocol utilizes dword/4-bytes alignment only) or even a Scatter Gather List (SGL) that might be byte aligned.
As will be discussed herein, the disclosure proposes that the storage device controller will be allowed to utilize over-reading to achieve better performance. Over-reading means that the device will read X (e.g., 64, 128 or 256) bytes even when it requires less and will drop the un-needed data internally. The value of X depends on the amount of data needed to be read from the host DRAM. The value of X is calibrated on the fly to maximize performance.
Over-reading means that the device will read X (e.g. X=64, 128 or 256) bytes even when the system requires less and will drop the un-needed data internally. The value of X depends on the amount of data needed to be read from Host DRAM. The value of X is calibrated “on-the-fly” to maximize the performance
The method 500 begins at block 502. At block 502, the controller determines whether the device works with LCRC and 16 bytes header. The device will look at the LCRC and header size to determine whether bytes will be saved with use of the simple over-read approach. If the controller determines that the device does work with LCRC and the 16 byte header, then the method 500 proceeds to block 506. At block 506, the device does not use simple over-read. If the controller determines that the device does not work with LCRC and the 16 byte header, then the method 500 proceeds to block 504. At block 504, the controller determines whether the device works in mixed-work load.
The device will look at mixed-workloads because with only write commands the added bandwidth is acceptable for performance. When a mixed-work load utilizes both a read and write command, the device has bandwidth gains from saving in the device to host path. With read commands the device sends data to the host. In this example write commands are being discussed. If a bigger amount of data is needed to be passed saving the bandwidth when available, then that is best for the device. If the controller determines that the device does work in mix-work load, then the method 500 proceeds to block 506. If the controller determines that the device does not work in mixed-work load, then the method 500 proceeds to block 508. At block 508, the device does use simple over-read.
The adaptive over-read takes into consideration also external consideration, such as efficiency and requirements in the host and switches. In method 700, the device attempts all three modes: “no-over-read”, “simple-over-read”, and “optimized over-read”, and measures the latency. This test can be repeated periodically as workload might change over-time. The method 700 begins at block 702. At block 702, N=number of splits for non-over-read, O=number of overhead bytes per TLP, R=number of redundant bytes in optimized over-read. At block 704, the controller determines whether if (N−1)*O<R. If the controller determines that (N−1)*O<R, then the method 700 proceeds to block 706. At block 706, the controller does not use simple over-read. If the controller determines that (N−1)*O>R, then the method 700 proceeds to block 708. At block 708, the controller uses optimized over-read. Non-over-read total bytes is N*O+user-data-size. Over-read total bytes is user-data-size+R+O.
According to one embodiment an adaptive over-read approach can be used. The device will check the previous approach (no over-read), simple over-read, and optimized over-read to see which is best for the device. The device will be checked every once in a while in a predetermined time defined by the device to make the check. The check consists of measuring the latency of each operation, to then provide which operation gives the best results. The repeating of the check every predetermined time is done because when the traffic loads changes, there can be changes in other devices in the system that may affect the fabric behavior or the host behavior.
At block 910, the controller determines whether the last measurement for this range is old. The “range” is per function. In another embodiment, a range can be HMB and non-HMB, but can further be HMB, PRP, commands fetching, or data transfer. The “old” is in reference to if the last statement was done more some configurable threshold. When doing a measurement for the first time, or doing a re-measure, the time of the measurement is kept in the table, such as table 800 of
By testing three different read methods of unaligned data, and by managing a per function UR responses, the data storage device can optimize both HMB access and non-HMB access to achieve better performance. Using the new approach allows the device to utilize a customize approach to over-read usage that will increase optimization of the system, which will then increase performance.
In one embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: receive a write command to write data to the memory device; execute the write command, wherein executing the write command comprises reading more data from a host device than corresponds to the write command; discard the more data; and deliver data corresponding to the write command to the memory device. An amount of data corresponding to the write command is less than an aligned data size. The amount of data corresponding to the write command and the discarded more data collectively is equal to the aligned data size. The controller is configured to determine whether to perform a simplified over read or an optimized over read. The determining is performed by calculating whether (N−1)*O<R where N is a number of splits for non over reads, O is a number of overhead bytes per transaction layer packet (TLP), and R is a number of redundant bytes in the optimized over read. The optimized over read is performed when R> (N−1)*O. The controller is configured to perform an adaptive over read. The adapted over read is a periodic measuring of latency for not over reading, simplified over reading, and optimized over reading. The controller is configured to operate in a multiple function nonvolatile memory express (NVME) device (MFND) environment. At least one virtual host in the MFND environment has different requirements from at least one other virtual host. The at least one virtual host uses a different over read than the at least one other virtual host. The controller is further configured to detect an unsupported request notification from a host device, and wherein the controller is configured to continue to perform over reads.
In another embodiment, a data storage device comprises: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: determine whether execution of a write command would be an aligned read transfer; determine whether execution of the aligned read transfer is a non host memory buffer (HMB) and has an unsupported request (UR) bit; and determine an age of a last measurement of a range of data for the aligned read transfer. The controller is configured to over read data when determining that execution of the aligned read transfer would result in a non-aligned transfer. The range is per function. The age is determined by comparing a time of a last measurement to a threshold. The range is applicable to HMB, command fetching, data transfer, and physical region page (PRP).
In another embodiment, a data storage device comprises: means to store data; and a controller coupled to the means to store data, wherein the controller is configured to: operate in a multiple function nonvolatile memory express (NVMe) device (MFND) environment; determine that a first function of the MFND operates without metadata; determine that a second function of the MEND operates with aligned physical region page (PRPs); and perform over read operations for one or more of the first function and the second function. The controller is configured to return an unsupported request (UR) notification to a host device to a function of the MEND that only supports aligned reads and a read operation resulted in an over read. The controller is configured to disable over read for functions of the MEND that receive a UR notification.
While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
