Patent Application
20170277613
Field
The present disclosure relates generally to testing electronic devices. More specifically the present disclosure related to methods and apparatus for multiple mode testing in a vector memory restricted test environment.
Background
Wireless communication devices have become smaller and more powerful as well as more capable. Increasingly users rely on wireless communication devices for mobile phone use as well as email and Internet access. At the same time, devices have become smaller in size. Devices such as cellular telephones, personal digital assistants (PDAs), laptop computers, and other similar devices provide reliable service with expanded coverage areas. Such devices may be referred to as mobile stations, stations, access terminals, user terminals, subscriber units, user equipment, and similar terms.
These wireless communication devices typically use a system-on-chip (SoC) to provide many of the functions of the device. A SoC is an integrated circuit that combines all components of a computer or other electronic system on a single chip. The SoC device may contain digital, analog, mixed-signal, and radio frequency (RF) functions on a single substrate. SoCs are used widely due to their low power consumption.
A SoC may consist of a microcontroller or digital signal processor (DSP) core, memory blocks including a selection of ROM, RAM, EEPROM, and flash memory, as well as timing sources. The timing sources may include oscillators and phase-locked loops (PLL). Peripherals, including counter-timers, real-time timers, and power-on reset generators may also be incorporated. A wide variety of external and internal interfaces including analog-to-digital (ADC), digital-to-analog converters (DAC), voltage regulators and power management circuits are also typically included in a SoC. The desired performance of the end device may result in different mixes of the above functions to be included in the SoC. The SoC also includes a bus system for connecting the various functional blocks.
Testing a SoC may be complex and time consuming. During testing of an SoC different frequencies must be tested. Each frequency tested has a different specification. All operating frequencies must be tested to ensure that the SoC or other device performs as intended in all modes. In addition, the memory of the SoC must be tested. When the memory of the SoC is tested the tests are stored in a memory present on the test apparatus. Limits on this memory may increase testing costs. However, due to restricted vector memory this test coverage may be sacrificed when testers with lower limits of vector memory are used to conduct tests. In addition, in some cases cross-corner tests cannot be integrated into the test flow due to the lower vector memory limit in some testers.
There is a need in the art for a method and apparatus for multiple mode testing in a vector memory restricted environment.
Embodiments described herein provide a method for testing an electronic device. The method begins with the generation of at least one test setup vector for at least one test to be performed. An actual test vector is then generated. The actual test vector may be generated using test results obtained from testing at least one device of known good quality. A delay time parameter is then determined. The delay time parameter may be determined by waiting for the test controller to complete the test. After the delay time parameter has been determined, at least one test result is output as a test signature. An additional delay parameter may also be added to take into account any variations across chips that may be present when different chip manufacturing processes are used. The test signature and the delay time parameter may used to call the test.
An additional embodiment provides an apparatus for testing an electronic device having a test controller and a vector memory in communication with the test controller. In addition, the apparatus may include at least one clock in communication with the test controller and a power supply.
A further embodiment provides an apparatus for testing an electronic device. The apparatus provides: means for generating at least one test setup vector for at least one test to be performed; means for generating at least one actual test vector; means for determining a delay time parameter; means for outputting at least one test result as a test signature; and means for calling the at least one test signature to initiate at least one test.
A yet further embodiment provides a non-transitory computer-readable medium containing instructions, which when executed cause a processor to perform the steps of: generating at least one test setup vector for at least one test to be performed; generating at least one actual test vector; determining a delay time parameter; outputting at least one test result as a test signature; and calling the at least one test signature to initiate at least one test.
Various aspects are now described with reference to the drawings. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects. It may be evident, however, that such aspect(s) may be practiced without these specific details.
As used in this application, the terms “component,” “module,” “system” and the like are intended to include a computer-related entity, such as, but not limited to hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component may be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program and/or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components may communicate by way of local and/or remote processes such as in accordance with a signal having one or more data packets, such as data from one component interacting with another component in a local system, distributed system, and/or across a network such as the Internet with other systems by way of the signal.
As used herein, the term “determining” encompasses a wide variety of actions and therefore, “determining” can include calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, “determining” can include resolving, selecting choosing, establishing, and the like.
The phrase “based on” does not mean “based only on,” unless expressly specified otherwise. In other words, the phrase “based on” describes both “based only on” and “based at least on.”
Moreover, the term “or” is intended to man an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from the context, the phrase “X employs A or B” is intended to mean any of the natural inclusive permutations. That is, the phrase “X employs A or B” is satisfied by any of the following instances: X employs A; X employs B; or X employs both A and B. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from the context to be directed to a singular form.
The various illustrative logical blocks, modules, and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core or any other such configuration.
The steps or blocks of a method or algorithm described in connection with the present disclosure may be embodied directly in hardware, in a software module executed by a processor or in a combination of the two. A software module may reside in any form of storage medium that is known in the art. Some examples of storage media that may be used include RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, a hard disk, a removable disk, a CD-ROM, and so forth. A software module may comprise a single instruction, or many instructions, and may be distributed over several different code segments, among different programs and across multiple storage media. A storage medium may be coupled to a processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor.
The methods disclosed herein comprise one or more steps, blocks, or actions for achieving the described method. The method steps and/or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and/or use of specific steps and/or actions may be modified without departing from the scope of the claims.
The functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored as one or more instructions on a computer-readable medium. A computer-readable medium may be any available medium that can be accessed by a computer. By way of example, and not limitation, a computer-readable medium may comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. Disk and disc, as used herein, includes compact disk (CD), laser disk, optical disc, digital versatile disk (DVD), floppy disk, and Blu-ray® disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.
Software or instructions may also be transmitted over a transmission medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of transmission medium.
Further, it should be appreciated that modules and/or other appropriate means for performing the methods and techniques described herein, such as those illustrated by
Embodiments described herein relate to a method and apparatus for multiple mode testing in a vector memory restricted environment. Embodiments described below provide a three part solution: test setup separation, delay optimization using a parameter in vectors, and assembling an optimized flow based on per mode fallout. Some embodiments allow for testing adjustments to be made on the fly.
A test setup enables the clocks and power to bring up the intended test block. These test blocks may be small size, but may vary across testing modes. In the actual test, a parameter for the delay time for the test to be completed is determined. This may be done by taking the maximum memory and the slowest frequency independent of the operational modes. In the test setup phase separate vectors are generated for the test setup and the actual test stages. The actual test vectors are used across frequency modes. Different test setups are generated for different frequency modes. The frequencies of the frequency test mode used for testing may be predetermined. That actual test stage is independent of frequency when used with a parameter. Only the parameter may be varied across the frequencies being tested.
Delay optimization begins with the instructions for starting the test. First the controller finishes the test. During this wait time while the controller is finishing the test optimization may occur. The wait time may be altered depending on the mode being tested. The parameters are then obtained before testing and are based on tests of known good electronic devices. This allows the same test vector to be used with multiple frequencies.
A further embodiment permits the wait time to be set, as a delay parameter, to a fixed number of clock cycles instead of a fixed period of time. This assists in testing independent of the clock frequency. In an optimized test flow different test suites call the same pattern in the pattern map file, but with different parameters, thus reducing the amount of vector memory needed for storing the test vectors. These embodiments may be extended to enable memory repair of different modes using the same repair vectors. In addition, these embodiments may also be used to test voltage dip and voltage data retention.
A SoC is an integrated circuit that combines all components of a computer or other electronic system on a single chip. It may contain digital, analog, mixed-signal, and radio frequency (RF) functions. A SoC may consist of: a microcontroller or digital signal processor (DSP) core; memory blocks, including a selection of read-only memory (ROM), random access memory (RAM), electrically erasable programmable read-only memory (a type of non-volatile memory), and flash memory; timing sources including oscillators and phase-locked loops (PLL); peripherals including counter-timers, real-time timers, and power-on or reset generators; external interfaces; analog interfaces including analog to digital converters (ADC), digital to analog converters (DAC); voltage regulators; and power management circuits. A bus connects these blocks within the SoC.
Testing the SoCs may be an important part of the manufacturing process. Automated test equipment (ATE) is used to perform tests on a device, known as the device under test (DUT) using automation to quickly perform measurements and evaluate test results. An ATE may be a simple computer-controlled digital multimeter, or may be a more complex system with many test instruments capable of testing and diagnosing faults in SoCs. ATE systems are designed to reduce the amount of test time needed to verify that a particular electronic device functions correctly, or to quickly find the faults before the device is installed in an end product, such as a wireless device. An ATE system may consist of a master controller (often a computer) that synchronizes one or more capture instruments.
The ARM processor 104 interfaces with peripheral bridge 140, which also provides input and output interface with the system controller 110. The peripheral bridge communicates with multiple components using an application peripheral bus (APB) 142. An internal bus 138 operates in conjunction with the peripheral bridge 140 to communicate with additional devices within the SoC 100. The internal bus 138 may be an application specific bus (ASP) or an application handling bus (AHB). Memory controller 140 interfaces with ARM processor 104 using internal bus 138. The memory controller 140 also communicates with the external bus interface (EBI) 146. Memory controller 140 is also in communication with static random access memory (SRAM) 148, and flash memory 150. Flash memory 150 is in communication with flash programmer 154. The memory controller 144 is also in communication with peripheral data controller 152. Additional application specific logic 156 communicates with the internal bus 138 and may also have external connections. A second PIO 158 provides communication with an Ethernet medium access control (MAC) 160. The second PIO 158 also communicates with a universal asynchronous receiver/transmitter 162, a serial peripheral interface (SPI) 164, a two wire interface 166, and an analog to digital converter 168. These devices and interfaces connect through internal bus 138 with a controller area network bus (CAN) 170, a universal serial bus (USB) devices 172, a pulse width modulator (PWM) controller 174, a synchro serial controller 176, and a timer/counter 178. These devices, CAN 170, USB device 172, PWM controller 174, synchro serial controller 176 and timer/counter 178 interface with third PIO 180, which provides external input and output. While these elements are typical of many SoCs, other devices may be incorporated, and some may not be included.
Testing suites provide an efficient way to test SoCs and other electronic devices. Many test controllers incorporate vector memory as part of the device. A conventional memory may be envisioned as an array of cubbyholes, each of which contains a piece of information. Each cubbyhole has a unique name, called either address or location. Often memory systems provide two primitive operations: one that fetches data stored in a specified location and another that assigns new data to a specified location. Memory addresses may be incremented to support sequential access to some set of cubbyholes. More generally, many important data operations require that memory addresses be treated as data, which can be stored in memory location and manipulated in machine registers. The representation of list structure is an application of such address arithmetic.
To model memory structures, a new kind of data structure, called a vector may be used. Abstractly, a vector is a compound data object whose individual elements may be accessed by means of an integer index in an amount of time that is independent of the index. In order to describe memory operations two primitive scheme procedures may be used: (vector-ref vector n) returns the nth element of the vector, and (vector-set\vector n value) sets the nth element of the vector to the designed value. This access may be implemented through the use of address arithmetic to combine a base address that specifies the beginning location of a vector in memory with an index that specifies the offset of a particular element of the vector.
Vectors may be used to implement the basic pair structures required for a list structured memory. The memory may be divided into two vectors. This list structure may be represented as follows: a pointer to a pair is an index into the two vectors. The first item of the pair is the entry in the first vector with the designated index, and the second item in the pair is the entry in the second vector with the designated index. Also needed is a representation for objects other than pairs (such as numbers and symbols), and a way to distinguish one type of data from another. This may be done with the typed pointer, which extends the notion of “pointer” to include information on data type. The data type enables the system to distinguish a pointer to a pair (which consists of the “pair” data type and an index into the memory vectors) from pointers to other types of data. Two data objects are considered to be the same if their pointers are identical.
A pointer to a number, which may designate a specific test to perform, may consist of a type indicating numeric data together with the actual representation of the number. A symbol may be represented as a typed pointer that designates a sequence of the characters that form the symbol's printed representation. A reader views the symbols and keeps an array, known the object array (obarray), of all of the symbols that have been encountered. New symbols may be added to the obarray as they are encountered. Using these techniques, each primitive list operation of a register machine may be replaced with one or more primitive vector operations. These vector operations allow efficient storage of complex test patterns, however, vector memory limits may seriously affect the number of test vectors that may be stored.
A further embodiment allows the delay time or wait time to be set to a fixed number of clock cycles instead of a predetermined period of time. This may assist when it is desirable to test independent of clock frequency. In the optimized flow embodiment, different test suites may call the same pattern in the pattern map file with different delay time parameters. The embodiments described herein may also be extended to memory repair of the different modes, using the same test vectors. The test vectors may also be used to test voltage dip and voltage data retention.
It is understood that the specific order or hierarchy of blocks in the processes disclosed is an illustration of exemplary approaches. Based upon design preferences, it is understood that the specific order or hierarchy of blocks in the processes may be rearranged. The accompanying method claims present elements of the various blocks in a sample order, and are not meant to be limited to the specific order or hierarchy presented.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but is to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed as a means plus function unless the element is expressly recited using the phrase “means for.”
It is to be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the systems, methods, and apparatus described herein without departing from the scope of the claims.
