Patent Grant
9225239
Three approaches are commonly employed in implementing DC-to-DC converters—electronic circuits that converts a battery or DC voltage source to a different DC voltage. These methods comprise linear regulation, inductive switching regulators or so-called “switch-mode power supplies,” and switched capacitor converters, also known as charge pumps. Of these methods, the charge pump is valued for its simplicity, cost effectiveness, and relatively low noise operation. Under certain circumstances, the charge pump can operate at high conversion efficiencies, but not over the wide range of conditions that switched inductor based converters can achieve.
The operating principle of a charge pump is straight forward comprising a charging phase and a charge transfer phase which operate in alternating sequence. As shown in
During the charge transfer phase, capacitor 5 is connected in series with the battery, specifically with its negative terminal shorted to the positive terminal of the battery achieved by turning on MOSFET 1. The voltage of the series combination of capacitor 5 stacked atop the battery input has a voltage of Vbatt+Vbatt=2Vbatt, or twice the battery voltage, hence the name “doubler” ascribed to this charge pump. This series circuit is simultaneously connected to output capacitor 6 by turning on MOSFET 4. Capacitor 5 then transfers its charge to output capacitor 6 until Vout→2Vbatt as shown by the solid line and arrows.
After the initial charging of output capacitor 6, the charge pump's operation becomes efficient since the only current flowing is that needed to replenish the charge lost on output capacitor 6 supplied to the load. As long as the desired output voltage is twice that battery voltage, i.e. 2Vbatt, the efficiency of doubler charge pump 1 is high, even up to 98%. Any deviation between the actual output voltage Vout and the charge pump's ideal output VCP=n·Vin will result in a loss of efficiency as given by the relation
The voltage differential between the charge pump lowers efficiency by causing one of the transistors to saturate a drop the incremental business. One common condition leading to lower efficiency in a doubler charge pump is “over-pumping” the output to a voltage higher than desired or required by the load.
Fractional Charge Pump Implementation: A common solution is to over-pumping is to employ a fractional charge pump, one that steps up by 1.5× rather than doubling its input. Such a fractional charge pump 20 as shown in
During charging, capacitors 30 and 31 are connected in series and charge to a voltage equal to Vbatt/2. During charge transfer, capacitors 30 and 31 are wired in parallel, connected in series with the battery input Vbatt with the series combination connected across output capacitor 32. The output voltage is charged to a voltage Vout→1.5Vbatt, a voltage 25% lower than the output of the doubler charge pump 1.
By employing a 1.5×-type fractional charge pump technique, efficiency is improved at lower output voltages but limited to a maximum of 1.5 times its input. Moreover, a 1.5× fractional charge pump, like the 2×-type charge pump, does not regulate voltage. As a result, its output voltage varies with its input which is undesirable in many applications.
Charge Pump Efficiency Considerations: Since a charge pump's output voltage varies with its input, it is not well adapted as a power converter and must often be combined with a linear regulator connected in series with the charge pump, to limit the output voltage swing. The linear regulator may be connected in either the input or output of the charge pump.
For example, a lithium ion input ranges from 4.2V to 3.0V during its discharge. Under such circumstances the output of a fractional 1.5× charge pump will vary in its output from 63V to 4.5V. A 2×-type charge pump doubler's output will vary from 8.4V to 6V under the same circumstances. If the load voltage is maintained at a fixed voltage, either by a linear regulator or because the load clamps the voltage across its terminals, then the efficiency will vary with the input voltage. The efficiency variation of linear regulated 1.5× and 2× charge pumps are summarized in the following table for a few commonly needed supply voltages. The output voltages of unregulated charge pumps are included in the table for reference along with a linear regulator with no charge pump, referred to in the table as a 1× converter.
As shown, each output voltage exhibits a range of efficiencies that varies with the battery's voltage, starting with a lower efficiency when the Lilon cell is fully charged to 4.2V and improving as the battery discharges down to 3V. The term “NA” means not available, meaning that the charge pump is incapable of producing the desired output voltage over the full range of inputs. Efficiency has no meaning if the output falls out of regulation. It should be also be noted that the efficiency shown in the table, given by the relation:
is the maximum theoretical efficiency of the charge pump, not taking into account losses in MOSFET resistance, switching losses, or other parasitic effects. The losses may further degrade efficiency by 3% to 6% below the theoretical maximum efficiency values shown.
From the table it is clear that efficiency is highest when the desired output voltage is close to the unregulated charge pump voltage, i.e. when Vout≈VCP. Lower output voltages therefore suffer from lower efficiencies because the charge pump is over-pumping the voltage to too high a value. For example a 1.8V volt output for a charge pump doubler has a peak theoretical efficiency of 30% while a 3V output has a conversion efficiency of 50%. Under the same circumstances, the fractional charge pump has a higher efficiency, 40% for a 1.8V output and 67% for a 3V output, because it is not pumping its output to as high a voltage as the doubler.
On the other hand, a fractional charge pump cannot output all the voltages commonly desired in a system. For example, a 1.5× charge pump cannot produce a 5V output over the full lithium ion range. At slightly above 3.3V the output voltage will sag below the desired 5V and the system may fail, meaning a 1.5× charge pump cannot be used reliably to produce a 5V regulated supply, despite having a higher efficiency when it is able to do so.
So if higher charge-pump multiples are used, e.g. n=2, the converter regulates over a wider voltage range but operates at lower efficiencies. If lower conversion factors of n are used, e.g. n=1.5 or even n=1, then the converter cannot supply the voltage over the full battery operating range unless the condition VCP(min)>Vout can be maintained.
One solution to the range versus efficiency tradeoff is to employ mode switching, i.e. to combine the doubler and fractional charge pumps into a single circuit, operating in 1.5× mode until the battery discharges and switching into 2× mode when the battery discharges. In this manner a higher average efficiency may be maintained over the battery voltage range. Such mode switching charge pumps capable of operating at two different values of “n”, in this case at 1.5× and 2×, are referred to as dual-mode charge pumps.
For outputs such as 3V and 3.3V even the 1× mode, or linear regulator only mode, may be used for some portion of time before the charge pump needs to turn on. By combining 1.5× and 1× mode charge pumps into a single charge pump, the resulting dual-mode charge pump is better adapted to lower voltage outputs than combining 2× and 1.5× modes.
Even more versatile, but slightly more complex a tri-mode charge pump, may operate in any of three modes, for example operating in step-down-only 1×-mode when the battery is charged, switching to 1.5× mode as the battery becomes discharged, and jumping into 2× mode if a higher voltage or current is temporarily demanded by the load. As one example, a tri-mode charge pump can drive 3.6V white LEDs as the back light in a cell phone using its 1.5× and 1× modes, and then momentarily switch into 2× mode whenever the 4.5V camera flash LEDs are needed.
An example of a tri-mode charge pump 35 is illustrated in
Except in 1× bypass mode where the charge pump is not switching, tri-mode charge pump 35 operates by the same principal as single-mode charge pumps 1 and 20, i.e. by successively charging flying capacitors 45 and 46 to a voltage Vfly, then transferring their charge to output filter capacitor 49 as needed. In the 1.5× mode, the capacitors are series connected and each charged to a voltage of Vbatt/2 through conducting MOSFETs 36, 37 and 38 while all other MOSFETs remain off. In 2×-mode, each flying capacitor is placed in parallel with the battery and charged to a voltage Vbatt through conducting switches 36, 39, 42 and 38 while all other MOSFETs, including MOSFET 37 remain off.
The charge transfer mode is the same regardless whether flying capacitors 45 and 46 are charged to a voltage Vbatt or Vbatt/2. Conducting MOSFETs 40 and 42 connect the negative terminals of charged capacitors 45 and 46 to the input voltage Vbatt. Conducting MOSFETs 43 and 44 along with forward biased diodes 47 and 48 connect the positive terminals of charged capacitors 45 and 46 to the converter's output and to filter capacitor 49. Charge transfer there occurs so that Vout→(Vbatt+Vfly). If Vfly is charged to a voltage Vbatt, then Vout→2Vbatt and charge pump circuit 35 operates as a doubler. If Vfly is charged to a voltage Vbatt/2, then Vout→1.5Vbatt and circuit 35 operates as a 1.5×-type fractional charge pump.
To operate in 1× bypass mode, conducting MOSFETs 36, 42, 43, 44 and optionally 40 and 37 connect Vout directly to Vbatt. No switching action is needed in this operating mode.
So aside from the disadvantage of containing a large number of MOSFETs to implement the switching matrix, tri-mode charge pump 35 can adjust its mode to reduce over-pumping and improve operating efficiency at any given output voltage.
Limitations of Charge Pumps: Many systems today require more than one regulated output voltage. One solution to this problem is to step up the battery voltage with a charge pump and then regulate down to lower voltages using more than linear regulator as illustrated in schematic 50 of
As shown charge pump 51 powered by Lilon battery 58 generates a voltage VCP which is stored on reservoir capacitor 57 and then regulated by linear regulators 51, 52, and 53 to produce various required regulated voltages Vout1, Vout2, and Vout3. Capacitors 54, 55, and 56 provide added filtering and improve regulator stability.
For example using a doubler for charge pump 51, linear regulators 51, 52 and 53 may be used to produce any desired voltage from 1V to nearly 6V. Using a fractional charge pump to implement converter 51, the guaranteed voltage VCP is limited to below 3V since a 1.5×-mode cannot reliably produce a 3V output and since some voltage, typically 300 mV, is lost as a voltage drop across the linear regulator.
Furthermore, if both positive, i.e. above ground, and negative, i.e. below ground supply voltages are required by the system, the approach of
In summary, the limitation of today's charge pumps is that they produce a single-voltage single-polarity output. While the charge pumps output voltage may be varied in time by mode switching, it must always deliver a voltage VCP higher than the highest voltage required by the system. Such restrictions greatly limit the use of charge pumps, forcing designers to employ one charge-pump per load, undesirably increasing costs, component count, and printed circuit board space.
What is really needed is a multiple output charge pump voltage converter or regulator capable of producing any number of positive and negative supply voltages simultaneously with the minimum number of components.
A multiple output DC-to-DC voltage converter using a new time-multiplexed-capacitor converter algorithm and related circuit topologies is herein disclosed. Unlike conventional charge pumps limited to producing a single output per charge pump, the new time-multiplexed-capacitor topology and method generates multiple voltage outputs of both positive and negative polarities from a single supply voltage or battery input. For the sake of clarity, the various embodiments of this invention are subdivided into four classes—dual polarity multiple-output converters, multiple-positive-output converters, multiple negative output converters, and re-configurable multiple-output converters.
Dual-Polarity Time-Multiplexed-Capacitor Converters: One embodiment of this invention is a time-multiplexed-capacitor converter capable of producing positive and negative output voltages. A representative implementation of this embodiment includes a flying capacitor, a first output node, a second output node, and a switching network. The switching network configured to provide the following modes of circuit operation: 1) a first mode where the positive electrode of the flying capacitor is connected to an input voltage and the negative electrode of the flying capacitor is connected to ground; 2) a second mode where the negative electrode of the flying capacitor is connected to the input voltage and the positive electrode of the flying capacitor is connected to the first output node; and 3) a third mode where the positive electrode of the flying capacitor is connected to ground and the negative electrode of the flying capacitor is connected to the second output node.
The first mode of operation charges the flying capacitor to a voltage equal to the input voltage. The second mode of operation provides a voltage of twice the input voltage at the first output node. The third mode of operation provides a voltage equal in magnitude but opposite in polarity to the input voltage at the second output node. Thus, a positive boosted voltage and an inverted voltage are provided using a single multiplexed flying capacitor.
A second representative implementation of this embodiment includes a first flying capacitor, a second flying capacitor, a first output node, a second output node, and a switching network. The switching network configured to provide the following modes of circuit operation: 1) a first mode where the first and second flying capacitors are connected in series with the positive electrode of the first flying capacitor connected to an input voltage and the negative electrode of the second flying capacitor is connected to ground; 2) a second mode where the negative electrodes of the flying capacitors are connected to the input voltage and the positive electrodes of the flying capacitors are connected to the first output node; and 3) a third mode where the positive electrodes of the flying capacitors are connected to ground and the negative electrodes of the flying capacitors are connected to the second output node.
The first mode of operation charges the flying capacitor to a voltage equal to one half of the input voltage. The second mode of operation provides a voltage of 1.5 times the input voltage at the first output node. The third mode of operation provides a voltage equal to −0.5 the input voltage at the second output node. Thus, a positive boosted fractional voltage and an inverted fractional voltage are provided using two multiplexed flying capacitors.
Positive Multiple Output Time-Multiplexed-Capacitor Converters: Another embodiment of this invention is a time-multiplexed-capacitor dual-output converter capable of simultaneous producing two positive fractional outputs +1.5Vbatt and +0.5Vbatt (where Vbatt is represents the input voltage to the charge pump). A representative implementation of this embodiment includes a first flying capacitor, a second flying capacitor, a first output node, a second output node, and a switching network. The switching network configured to provide the following modes of circuit operation: 1) a first mode where the first and second flying capacitors are connected in series with the positive electrode of the first flying capacitor connected to an input voltage and the negative electrode of the second flying capacitor is connected to ground; 2) a second mode where the negative electrodes of the flying capacitors are connected to the input voltage and the positive electrodes of the flying capacitors are connected to the first output node; and 3) a third mode where the negative electrodes of the flying capacitors are connected to ground and the positive electrodes of the flying capacitors are connected to the second output node.
The first mode of operation charges the flying capacitor to a voltage equal to one half of the input voltage. The second mode of operation provides a voltage of 1.5 times the input voltage at the first output node. The third mode of operation provides a voltage equal to 0.5 the input voltage at the second output node. Thus, two positive boosted fractional voltages are provided using two multiplexed flying capacitors.
Multiple Negative Output Time-Multiplexed-Capacitor Converters: In another embodiment of this invention, a time-multiplexed-capacitor dual-output converter capable of simultaneously producing two negative fractional outputs −0.5Vbatt and −Vbatt. (where Vbatt is represents the input voltage to the charge pump). A representative implementation of this embodiment includes a first flying capacitor, a second flying capacitor, a first output node, a second output node, and a switching network. The switching network configured to provide the following modes of circuit operation: 1) a first mode where the first and second flying capacitors are connected in series with the positive electrode of the first flying capacitor connected to an input voltage and the negative electrode of the second flying capacitor is connected to ground; 2) a second mode where the positive electrodes of the flying capacitors are connected to ground and the negative electrodes of the flying capacitors are connected to the first output node; and 3) a third mode where the first and second flying capacitors are connected in series with the positive electrode of the first flying capacitor connected to ground and the negative electrode of the second flying capacitor is connected to the second output node.
The first mode of operation charges the flying capacitors to a voltage equal to one half of the input voltage. The second mode of operation provides a voltage of −0.5 times the input voltage at the first output node. The third mode of operation provides a voltage equal to −1.0 times the input voltage at the second output node. Thus, two inverted fractional voltages are provided using two multiplexed flying capacitors.
Reconfigurable Multi-Output Time-Multiplexed Fractional Charge Pumps: The time-multiplexed-capacitor charge pump can be scaled for supplying several different voltages simultaneously, and can be electronically reconfigured to produce a different set of voltages. A representative implementation of this embodiment includes a first flying capacitor, a second flying capacitor, a first output node, a second output node, a third output node, and a switching network. The switching network configured to provide the following modes of circuit operation: 1) a first mode where the flying capacitors are connected in series or in parallel between an input voltage (VIN) and ground to allow the flying capacitors to be charged to any of the following voltages: VIN, −VIN, ½ VIN, −½ VIN; and 2) a second mode where the first and second flying capacitors are connected in series with the negative electrode of the second flying capacitor connected to the input voltage and the positive electrode of the first flying capacitor is connected to the first output node; and 3) a third mode where the negative electrodes of the flying capacitors are connected to the input voltage and the positive electrodes of the flying capacitors are connected to the second output node.
A range of different output voltages are provided to the three output nodes depending on the configuration of the switching network during charging and output. At least the following combinations are available (each triple represents the output at the first output node, the voltage at the second output node and the voltage at the third output node):
1) 3Vbatt, 2Vbatt, −Vbatt,
2) 2Vbatt, 1.5Vbatt, 0.5Vbatt,
3) 2Vbatt, 1.5Vbatt, −0.5Vbatt,
4) unused, −Vbatt, −2.0batt,
5) unused, −0.5batt, −Vbatt.
A multiple output DC-to-DC voltage converter using a new time-multiplexed-capacitor converter algorithm and related circuit topologies is herein disclosed. Unlike conventional charge pumps limited to producing a single output per charge pump, the new time-multiplexed-capacitor topology and method generates multiple voltage outputs of both positive and negative polarities from a single supply voltage or battery input. For the sake of clarity, the various embodiments of this invention are subdivided into four classes—dual polarity multiple-output converters, multiple-positive-output converters, multiple negative output converters, and re-configurable multiple-output converters.
Dual-Polarity Time-Multiplexed-Capacitor Converters: One embodiment of this invention is a time-multiplexed-capacitor converter capable of producing positive and negative output voltages simultaneously. In
The converter comprises a single flying capacitor 67, MOSFETs 61 through 66, and reservoir capacitors 70 and 71. Optionally MOSFETs 65 and 66 may include intrinsic drain-to-source P-N diodes 68 and 69 depending on MOSFET implementation. Operation involves a sequence of four phases—charging the flying capacitor, transferring charge to the positive output capacitor, refreshing the flying capacitor, and transferring charge to the negative output capacitor.
In greater detail, in the first phase of operation shown by circuit 80 in
In the second phase of operation shown by circuit 85 in
The third phase of operation shown by circuit 90 in
In the fourth and final phase of operation shown by circuit 95 in
The entire cycle then repeats itself as shown in flow chart 99 of
During transition {circle around (1)} the converter is reconfigured for charge transfer to the positive output, i.e. to state 111. In charge transfer condition 111, capacitor 67 stacked atop battery 101 with its negative terminal Vx tied to the positive terminal of battery 101, charges capacitor 70 to a voltage +2Vbatt.
In one embodiment of this invention, the converter is next reconfigured in transition {circle around (2)} back into charging state 110. The charging state 110 then repeats until capacitor 67 charges to a voltage Vbatt replenishing any charge lost during state 111.
After the capacitor is refreshed, the converter is again reconfigured during transition {circle around (3)} into charge transfer state 112. During this state, charge flying capacitor 67 is connected below ground with its positive terminal Vy connected to the negative terminal of battery 101. In this configuration, charge transfer from flying capacitor 67 to output capacitor 71 drives the negative output to a voltage equal to −Vbatt.
The converter is then reconfigured in transition {circle around (4)} back into charging state 110. The charging state 110 then repeats until capacitor 67 charges to a voltage Vbatt replenishing any charge lost during state 112.
The entire then repeats in sequence {circle around (1)} charge {circle around (2)} positive transfer {circle around (3)} charge {circle around (4)} negative transfer and then repeating {circle around (1)}, {circle around (2)}, {circle around (3)}, {circle around (4)}, {circle around (1)}, etc. . . . The voltage waveforms for this time multiplexed sequence is illustrated in the graphs of
From time t0 to t1 corresponding to state 110, flying capacitor 67 is charged whereby Vy charges to Vcc as shown by curve 121 and Vx remains near ground shown by curve 131. During this cycle Vout1 sags below a value of 2Vcc until it reaches its minimum voltage at time t1. In tandem, Vout2 also sags 151 to a lower, i.e. less negative, voltage than −Vcc.
Meanwhile Vfly charges during interval 145 till it reaches a voltage Vcc where it remains through the rest the state 110 until t1.
During interval t1 to t2 corresponding to state 111, Vx is biased to Vcc during the entire cycle 132 and Vy is forced to 2Vcc as flying capacitor 67 “flies up” and transfers its charge to the positive output's filter capacitor 70. As a result Vout1 is refreshed in transition 142 while Vfly decays in corresponding 147.
From time t2 to t3 the circuit returns to state 110, flying capacitor 67 is replenished as whereby Vy charges to Vcc as shown by curve 124 and Vx remains near ground shown by curve 133. During this cycle Vout1, now fully charged, first begins to sag 143. In tandem, Vout2 continues to sags 151 to a lower, i.e. less negative, voltage than −Vcc. Meanwhile Vfly charges during interval 148 till it reaches a voltage Vcc where it remains 149 through the rest the state 110 until t3.
During interval t3 to t4 corresponding to state 112, Vy is biased to ground during the entire cycle 125 and Vx is forced to −Vcc as flying capacitor 67 flies down and transfers its charge to the negative output's filter capacitor 71. As a result −Vout2 is refreshed in transition 152 stabilizing at −Vcc 153 while Vfly decays in corresponding 150. At t4, −Vout2 begins another cycle of decay as the cycle repeats itself.
In an alternative embodiment of this invention also shown in the state diagram of
In a related embodiment of this invention, circuit 200 of
As shown in the equivalent circuit 255 of
In the next phase shown by schematic 260 in
In a preferred embodiment, in the third phase of operation the charge pump returns the charging condition 255 of
In the fourth and final phase shown by schematic 265 in
The operation of fractional dual-output time-multiplexed-capacitor converter 200 with a +1.5Vbatt positive output and a −0.5Vbatt negative output can be summarized in flow chart 299 of
Positive Multiple Output Time-Multiplexed-Capacitor Converters: In another embodiment of this invention, circuit 300 of
As shown in the equivalent circuit 330 of
In the next phase shown by schematic 335 in
Optionally P-N diodes 313 and 314 intrinsic to MOSFETs 307 and 309 may be included depending on device construction, but must be oriented with their cathodes connected to the Vout1 terminal. In this phase of operation, all other MOSFETs remain off including 308 and 310. Because Vout2 is also positive, MOSFETs 308 and 310 must not include intrinsic diodes across their source to drain terminals. In one embodiment of this invention, a special body-bias-generator circuit is employed to eliminate the presence of the intrinsic diodes.
In a preferred embodiment, in the third phase of operation the charge pump returns the charging condition 330 of
In the fourth and final phase shown by schematic 340 in
A necessary element of charge pump 300 or any a multiple positive-output time-multiplexed-capacitor charge pump, the charge transfer MOSFETs connecting the flying capacitors to any output except for the most positive one must be free from any source-to-drain parasitic diodes or diode conduction. Methods for eliminating source-to-drain diode conduction as illustrated by
In summary, operation of fractional dual-output time-multiplexed-capacitor converter 300 with a +1.5Vbatt and a +0.5Vbatt positive output is shown in flow chart 369 of
Method to Eliminate Unwanted Source-Drain Diodes: One key feature of a time-multiplexed-capacitor dual-positive output converter is that only the MOSFETs connecting the flying capacitors to the most positive output may include intrinsic source-to-drain diodes. Specifically in converter 300, MOSFETs 308 and 310 connected to Vout2 do not include intrinsic P-N junctions parallel to their source drain terminals, while MOSFETs 307 and 309 connected to Vout1, the most positive output voltage, do. Specifically, with their cathodes connected to the highest output voltage Vout1, diodes 313 and 314 can never become inadvertently become forward biased except in the second phase 335 when capacitor 315 of Vout1 is being charged. If diodes were present across 308 and 310, the charge pump voltage would be limited (Vout2+Vf), where Vf is the forward biased voltage of the P-N diodes, and would not function or otherwise be able to produce its higher output voltage +1.5Vbatt.
Eliminating the P-N diode across MOSFETs 308 and 310 requires a special technique incompatible with conventional source-to-body shorted MOSFETs. These methods include employing an N-channel MOSFET with a grounded body connection, employing a P-channel MOSFET with its body tied to the highest positive voltage Vout2, or in a preferred embodiment to integrate a special “body bias generator” circuit with either a P-channel or an N-channel MOSFET that switches source-to-drain diode polarities to maintain reverse bias.
Such a method is illustrated in circuit 350 of
Whenever VCP>Vout2, P-channel MOSFET 352A is conducting and 352B is off, connecting the body terminal VB of PMOS 308 to VCP and shorting out diode 351A. Configured in this way, diode 351B is electrically connected in parallel to the source drain terminals of P-channel 308. Since, the anode of diode 351B is permanently connected to VOUT2 biasing its cathode to the more positive VCP potential reverse biases diode 351B and no diode conduction will occur. In the context of converter 300, the VCP>Vout2 condition occurs whenever flying capacitor 311 is charged, PMOS 304 is conducting and NMOS 305 is off, regardless of the state of MOSFET 307, a state occurring whenever the flying capacitor is in one of its charge transfer cycles.
Conversely, Whenever VOUT2>VCP, P-channel MOSFET 352B is conducting and 352A is off, connecting the body terminal VB of PMOS 308 to VOUT2 and shorting out diode 351B. Configured in this way, diode 351A is electrically connected in parallel to the source drain terminals of P-channel 308. Since, the anode of diode 351A is permanently connected to VCP biasing its cathode to the more positive VCP potential reverse biases diode 351A and no diode conduction will occur. In the context of converter 300, the Vout2>VCP condition occurs whenever flying capacitor 311 is charging, PMOS 304 is off and NMOS 305 is conducting, regardless of the state of MOSFET 307, a state occurring whenever the flying capacitor is in one of its charging cycles.
So using the BBG circuit technique, regardless of the polarity applied across P-channel MOSFET 308, the body terminal VB is biased so that no source-drain diode conduction occurs. With diode's 351A and 351B not conducting, current flow from flying capacitor 311 to output reservoir capacitor 316 is controlled by the gate voltage of MOSFET 308 and not by the forward biasing of P-N junction diodes. In contrast to MOSFET 307 with its intrinsic P-N diode 313, MOSFET 308 therefore has no source-to-drain diode. Whenever charge pump 350 is in charge transfer mode, i.e. with capacitor 311 charged and PMOS 304 conducting, current can be steered to either VOUT1 and capacitor 315, or VOUT2 and capacitor 316 depending on the gate control of MOSFETs 307 and 308. Current steering is fundamental to implementing a time multiplexed charge pump.
In circuit 350, if both MOSFETs 307 and 308 remain off, charge transfer to any output can only occur by the forward biasing of diode 313. The maximum voltage of node VCP is therefore limited to VCP≦(Vout1+Vf), where Vf is the forward biased voltage of P-N diode 313. In a multiple positive-output time-multiplexed charge pump, only the highest most-positive voltage output can include a source-to drain diode. Any MOSFET connected to an output voltage VOUT2 lower, i.e. less positive, than the highest output VOUT1 must employ the BBG circuit to eliminate unwanted diode conduction.
As shown in circuit 350, P-channel 307 includes a parallel source-to-drain diode 313 while PMOS 308 does not. In an alternative embodiment diode 313 could also be eliminated by employing a body-bias-generator circuit for P-channel MOSFET 307 similar to the one used to drive the body of P-channel 308.
Another approach is to employ an N-channel MOSFET in place of P-channel 308 and optionally in place of P-channel 307. Using an N-channel MOSFET in place of a P-channel to eliminate the unwanted source-to-drain parallel diode may be implemented in one of two ways, either by permanently grounding the N-channel MOSFET's body terminal or by using a body-bias generator technique.
In circuit 355 of
In an alternative implementation N-channel MOSFET 361 is used to replace P-channel 308. As shown, the body of N-channel 361 is not grounded and its potential VB may float to a more positive voltage. Cross-coupled N-channel MOSFETs 363A and 363B along with intrinsic diodes 362A and 362B form a body-bias generator circuit to bias the N-channel body voltage VB so that no P-N diode conduction occurs. All three N-channel MOSFETs 361, 362A, and 362B are biased at the same potential, a voltage determined by the switching action of N-channel MOSFETs 363A and 363B. Body bias operation is similar to that of the aforementioned BBG circuit except that N-channel MOSFETs conduct with positive gate voltages where as the P-channel MOSFETs in circuit 350 turn-on only for negative gate-to-source bias potentials.
As such, during the charge transfer phase when VCP>Vout2, N-channel 363B is turned on shorting-out intrinsic diode 362B and forcing VB=Vout2, the more negative of the two applied potentials. At the same time, N-channel MOSFET 363A remains off. With the cathode of diode 362A biased to a more positive potential VCP than its body-connected anode biased at VB=Vout2, then diode 362A remains reversed biased and non-conducting.
Conversely during the charging phase for flying capacitor 311 when Vout2>VCP, N-channel MOSFET 363B is turned off and N-channel 363A conducts, shorting-out intrinsic diode 362A and forcing VB=VCP, the more negative of the two applied potentials. With the cathode of diode 362B biased to a more positive potential VOUT2 than its body-connected anode biased at VB=VCP, then diode 362B remains reversed biased and non-conducting. So no matter which polarity is applied across the source-drain terminals of MOSFET 361, no P-N diode conduction occurs.
While circuit 360 represents the N-channel circuit counterpart to the P-channel BBG circuit shown in schematic 350, monolithic integration of N-channel version 360 into an integrated circuit requires special consideration. Specifically, most common CMOS integrated circuit processes employ a P-type substrate and a self-isolating N-type well. P-channel MOSFETs are fabricated in the N-well while N-channel are formed in the common P-type substrate or in a P-well formed in and shorted to said substrate. To implement circuit 360, however, the P-type body of N-channels 361, 362A and 362B must be isolated from their surrounding P-type substrate so that VB can float and is not hard-wired to ground. With a P-type body region separate from a grounded substrate, circuit 360 will function for any body voltages when VB≧0.
Schematically, this isolation is represented by back-to-back P-N diodes 364 and 365 where the anode of diode 364 represents the isolated P-type floating region, well, or tub, the anode of diode 365 represents the P-type substrate or epitaxial layer, and the common cathode of diodes 364 and 365 describe the N-type isolation at potential VISO surrounding the floating P-type region. Under normal operation VB≧VISO≧0, meaning that diode 364 is forward biased and VISO will unless otherwise forced float to a positive potential approximately equal to VB, and thereby reverse bias isolation diode 365.
Multiple Negative Output Time-Multiplexed-Capacitor Converters: In another embodiment of this invention, circuit 370 of
As in prior fractional charge pump circuits, operation of converter 370 first involves charging flying capacitors 379 and 380 through conducting MOSFETs 371, 372 and 303. Since the flying capacitors are series connected each one charges to a voltage Vbatt/2. All other MOSFETs remain off and all diodes remain reversed biased during this cycle. Output capacitors 382 and 383 must supply the current to any loads (not shown) during this charging phase.
In the next phase shown by schematic 385 in
In a preferred embodiment, in the third phase of operation the charge pump returns the charging condition where capacitors 379 and 380 are each charged to Vbatt/2. The circuit then continues into the fourth operating phase shown by equivalent circuit 386 of
In the fourth and final phase shown by schematic 386 in
A necessary element of charge pump 370 or any a multiple negative-output time-multiplexed-capacitor charge pump the charge transfer MOSFETs connecting the flying capacitors to any output except for the most negative one must be free from any source-to-drain parasitic diodes or diode conduction. Methods for eliminating source-to-drain diode conduction are similar to those illustrated by
In summary, operation of fractional dual-output time-multiplexed-capacitor converter 370 with a −Vbatt and a −0.5Vbatt negative output is shown in flow chart 389 of
In converter 370, the charge transfer from the flying capacitors to VOUT1 shown in circuit 385 involves paralleling capacitors 379 and 380. In circuit 386, during charge transfer to VOUT2, the capacitors are series connected. In this regard, the parallel combination in circuit phase 385 delivers more charge to output capacitor 382 than the series arrangement of circuit 386 is capable of delivering to VOUT2. This means the −0.5Vbatt supply output VOUT1 is capable of delivering higher output currents than the −Vbatt supply output VOUT2.
In another embodiment of this invention illustrated in circuit 390 of
After charging both capacitors to Vbatt in the first phase of operation, output capacitor 382 is charged during a second phase of operation by the parallel combination of flying capacitors 379 and 380 and through conducting MOSFETs 374, 375, 376 and 377 to a voltage VOUT1→−Vbatt.
After a third phase when the flying capacitors are refreshed, MOSFETs 374, 372 and 378 are turned on forming a series combination of capacitors 379 and 380, where the positive terminal of capacitor 379 is connected to ground, the positive terminal of capacitor 380 is connected to the negative terminal of capacitor 379 through conducting MOSFET 372, and where the negative terminal of capacitor 380 is connected to output capacitor 383 which charges to VOUT2→−2Vbatt.
Circuit 390 can therefore be operated in two different ways. If the flying capacitors are charged to Vbatt/2, time multiplexing facilitates two output voltages, namely −Vbatt/2 and −Vbatt. If the flying capacitors are instead charged to Vbatt, time multiplexing facilitates two higher output voltages, namely −Vbatt and −2Vbatt. Because the converter is producing two outputs of the same polarity, MOSFETs 376 and 377 must be free of any parasitic source-to-drain diodes.
Reconfigurable Multi-Output Time-Multiplexed Fractional Charge Pumps: The time-multiplexed-capacitor charge pump can be scaled for supplying several different voltages simultaneously, and can be electronically reconfigured to produce a different set of voltages. For example,
The circuit topology of converter 400 comprises two H-bridges, one for each flying capacitor, a MOSFET for connecting the flying capacitors in series, and two MOSFET “triplets” used for control charge transfer to the converters three voltage outputs V1, V2, and V3. In greater detail, capacitor 410 is biased at node voltages Vz and Vy where node Vz is driven by a push-pull buffer comprising Vbatt-connected MOSFET 401 and grounded MOSFET 402, and where Vy is driven by a push-pull buffer comprising Vbatt-connected MOSFET 405 and grounded MOSFET 406. Together MOSFETs 401, 402, 405 and 406 form an H-bridge driving capacitor 410.
Similarly, capacitor 411 is biased at node voltages Vx and Vw where node Vx is driven by a push-pull buffer comprising Vbatt-connected MOSFET 403 and grounded MOSFET 404, and where Vw is driven by a push-pull buffer comprising Vbatt-connected MOSFET 407 and grounded MOSFET 408. Together MOSFETs 403, 404, 407 and 408 form an H-bridge driving capacitor 411. Node Vx of capacitor 411 is also connected to node Vy of capacitor 410 by MOSFET 409.
Charge-transfer MOSFETs 412, 413, and 414 together form a triplet connecting node Vz of flying capacitor 410 to outputs V1, V2 and V3 respectively. Similarly, charge-transfer MOSFETs 415, 416, and 416 together form a triplet connecting node Vx of flying capacitor 411 to outputs V1, V2 and V3 respectively. Outputs V1, V2 and V3 correspond to filter capacitors 424, 425, and 426 respectively.
Operation of the MOSFET array can better be interpreted as a series of multiplexer switches, although the MOSFETs may in some circumstances be used to control capacitive charging currents. This functional interpretation of charge pump 400 is illustrated in circuit 430 of
MOSFETs 401 and 402 comprise 1P3T switch 431 which in operation selects one of three inputs, Vbatt when MOSFET 401 is on, ground when MOSFET 402 is in its on state, or an open circuit when neither MOSFETs 401 or 402 are conducting. The output of multiplexer switch 431 biases node Vz on flying capacitor 410. A second 1P3T switch 432 comprises MOSFETs 405 and 406, and in operation biases node Vy on capacitor 410. In a similar configuration for biasing capacitor 411, MOSFETs 403 and 404 comprise 1P3T multiplexer switch 433 biasing node Vx on flying capacitor 411. A second 1P3T switch 434 comprises MOSFETs 407 and 408, and in operation biases node Vw on capacitor 411. MOSFET 409 is included for connecting capacitors 410 and 411 in series when needed.
The output of the node voltages Vz and Vx are selected and time multiplexed to supply energy to one of several outputs V1, V2 or V3, transferring charge from flying capacitors 410 and 411 to output capacitors 424, 425, and 426. SP4T switch 435 is formed from the MOSFET triplet comprising devices 412, 413 and 414. SP4T switch 436 is formed from the MOSFET triplet comprising devices 415, 416 and 417. In a preferred embodiment each MOSFET triplet has only one device conducting at a time. The no-connect or NC switch position corresponds to the state where all three MOSFETs are off.
Operation is similar to the previous examples except that there are a greater number of combinations of inputs and outputs possible, primarily due to the flexible reconfigurable MOSFET matrix. Operation involves charging the flying capacitors, transferring charge to output V1 and its capacitor 424, refreshing the flying capacitors, transferring charge to output V2 and its capacitor 425, refreshing the flying capacitors again, transferring charge to output V3 and its capacitor 426, then repeating the entire sequence again.
Charging of the flying capacitors can be achieved in many ways using converter 400. A few of these combinations are illustrated in
In equivalent circuit 460, capacitors 410 and 411 are each charged to a voltage Vbatt/2 where MOSFET 401 is on, Vz=Vbatt, MOSFET 409 is on, Vy=Vx, MOSFET 408 is on, and Vw=0. All other MOSFETs are off. This condition corresponds to having multiplexers 431 in its Vbatt position, multiplexers 432 and 433 in its NC position, and multiplexer 434 in its grounded position. The flying capacitors are therefore charged in series with one other and equal in voltage to one-half the battery input voltage.
In both charging circuits 450 and 460, the positively charged capacitor plates are connected to Vz and Vx. The conditions Vz>Vy and Vx>Vw are defined herein as positive polarity charging. The MOSFET matrix and multiplexer can also charge capacitors in inverted polarity. In schematic 470, node Vz and Vx are biased to ground by conducting MOSFETs 402 and 404 while Vy and Vw are biased to Vbatt by on-state MOSFETs 405 and 407. As shown, flying capacitors 410 and 411 are charged in parallel but opposite in polarity relative to condition 450, i.e. they are charged to −Vbatt. MOSFET 409 and all other devices remain off during charging.
Circuit 480 represents the fractional inverted charging condition where Vz is biased to ground by on MOSFET 402; Vw is biased to Vbatt by conducting MOSFET 407, and on-state MOSFET 409 forces Vx=Vy. Being series connected, each flying capacitor charges to half the battery voltage but relative to circuit 460, in inverted polarity, i.e. the capacitors are charge to a bias of −Vbatt/2. Other charging conditions, e.g. where flying capacitor 410 is charge to a positive polarity while flying capacitor 411 is charged in its inverted polarity, also exist but are not included in the drawings.
By charging the flying capacitors to the battery input bias Vbatt, time multiplexed converter 400 can output two positive voltages and one negative voltage simultaneously, where the voltages comprise 3Vbatt, 2Vbatt and −Vbatt.
Conducting MOSFETs 414 and 417 transfer their charge to capacitor 426 corresponding to output voltage of 0.5Vbatt. All other MOSFETs including MOSFET 409 remain off. Because Vout3 is not the most positive output voltage, MOSFETs 414 and 417 must utilize BBG circuitry 420 and 423 to prevent unwanted diode conduction. The corresponding flow algorithm 559 for the fractional triple-output time-multiplexed capacitor charge pump is shown in
Algorithmic Considerations in Time-Multiplexed-Capacitor Charge Pumps: Regardless of the voltage, polarity, and number of outputs, time multiplexing of a charge pump follows a simple algorithm 700 shown in
The dotted lines and arrows in flow chart 700 represent an alternative flow where the flying capacitors are not refreshed between charge transfers but instead charge several output capacitors before returning to refresh the flying capacitors. Specifically in such an algorithm, the converter charges the flying capacitors, transfers charge from the flying capacitors to a first output at voltage V1, then following transition 704 transfers charge from the flying capacitors to a second output at voltage V2, followed by transition 705 transferring charge from the flying capacitors to a third output at voltage V3, and only thereafter returns by transition 706 to refresh the flying capacitors.
While either algorithm, the theoretical number of converted voltages may be adapted for “n” outputs. One limitation of this approach is output ripple increases in proportion with “n”, the number of outputs—the greater the number of outputs, the greater the output ripple of any given output will be. Also any algorithm that doesn't regularly refresh the flying capacitors will suffer more voltage sag on the flying capacitors, which in turn further degrades ripple. Conversely, refreshing the flying capacitors more often reduces the frequency by which a given output's filter capacitor is refreshed.
In one embodiment of this invention, ripple is minimize by matching the algorithm to the output's ripple requirements, i.e. choosing an algorithm where the outputs charged last or the least often power loads that tolerate the highest degree of ripple. In the dotted line algorithm of state diagram 700 comprising transitions 704, 705, and 706, for example, the flying capacitors exhibit their greatest voltage sag during charge transfer to the V3 output capacitor, the last output to be recharged before the flying capacitors are refreshed by transition 706. As such the ripple specification for V3 should be worse than V2 and the load and specification should be matched accordingly. In comparison, the V1 output, the first charge transfer after refreshing the flying capacitors, will exhibit the lowest ripple. Ripple may be also be reduced by increasing the size of the output capacitors, but with the disadvantage of some incremental cost.
One compromise to the tradeoff between voltage sag in the flying capacitors versus recharge rate of a specific output voltage is shown in
As is often the case in electronic systems not every power supply must meet strict ripple and regulation requirements, often because some electrical loads are tolerant to noise or do not exhibit significant current transients. In the event that some outputs exhibit larger load current transients than others, the algorithm can be adjusted to re-charge noisy and changeable outputs more often. Such an algorithm is represented in flow chart 740 of
In an alternate algorithm 760 shown in
The disadvantage of all the aforementioned algorithms is they redistribute energy from the flying capacitors to the various multiplexed outputs without any consideration of load conditions. Such algorithms exhibit “blind distribution” of the converter's energy allocation. While it is true that the various voltage outputs will not transfer charge from the flying capacitors to their output capacitor unless it is needed, a fixed time is none-the-less allocated to do so. Meanwhile other outputs experiencing large load current transients and voltage deviations cannot react and are not allocated longer transfer times in order to react more quickly. Conversely, however, variable charge transfer times for each output will result in variable frequency operation and a varying noise spectrum—an undesirable characteristic in many electronic systems, especially those related to communication.
A fixed frequency algorithmic method remedies this problem whereby, in an alternative embodiment of the invention, a time-multiplexed-capacitor multiple output charge pump uses feedback to dynamically adjust the converter's algorithm to respond to rapid charge in the load condition of specific voltage outputs. Algorithm 780 shown in
The conditional test 781 determines whether another charge pump cycle of charging the flying capacitors and transferring charge to the V1 capacitor is needed or if normal operation may resume, where the V2 output capacitor is to be charged in alternating sequence with the V1 output. This conditional test requires monitoring of the V1 output voltage either by using an analog comparator or by using digital control fed by an analog-to-digital converter, herein referred to as by the acronym ADC or A/D.
Conditional test 782 insures that V2 occasionally is re-charged even during a V1 load transient. Counter 783 counts the number of times the flying capacitors transfer charge to the V1 output. So long that the counter does not exceed some pre-defined value “n”, which may for example be 2, 3, or many more times, then the charge pump will continue to refresh the flying capacitors and transfer its charge to the V1 output capacitor. If the count does, however, exceed “n” then the converter is diverted to re-charge V2, even though V1 has not yet reached its defined tolerance range. Each time that a charge transfer to V2 occurs, the counter is reset to zero by step 784 and the entire cycle repeated.
Under normal operation, algorithm 780 charges the V1 and V2 output capacitors in alternating fashion. While compatible with variable frequency operation, algorithm 780 works equally well with fixed frequency charge pump operation. In the event of a V1 load transient, the system adapts to deliver more charge to the critical output by incrementing the charge transfer to V1 by some integer number of cycles. In a preferred embodiment this adaptive response still occurs at a fixed clock rate. Algorithm 780 evaluates the condition of V1 every charging cycle.
The algorithm 780 can be similarly modified for three or more output voltages V1, V2, and V3 as shown in circuit 790 of
If two voltages require feedback for improved response time, a second comparator 799 can be added, but consideration must be given to the hierarchical priority given to each voltage output in the algorithm. For example if the highest priority is given to V1 and re-charging capacitor 792, then V2 and V3 will exhibit slower transient response times, which may be offset in part by using higher capacitance filter capacitors 793 and 794. Alternatively comparator 797 can be time multiplexed to monitor both V1 and V2 outputs on a sample rather than a continuous basis. The approach where an algorithm constantly or frequently requests physical information, in this case the charge pump's output voltages, on a regular basis is known as a “polled” system.
Since many of the algorithms described contain “if-then-else” decisions, another option is to implement the priority hierarchy and multiplexing algorithm using firmware implemented in a microprocessor based system.
Basic operation of triple output charge pump 811 remains under the control of microprocessor 814 which monitors the voltages on outputs V1 and V2 on a sample basis and adjusts the algorithm dynamically to improve transient response. Analog multiplexer facilitates monitoring two different outputs from one A/D converter 821 and to report the digital information into digital inputs of microprocessor 814. Both microprocessor 814 and charge pump 811 are powered from voltage regulator 815 and are synchronized to a common clock switching at frequencies and m·φ respectively. The multiplier m can be 0.001 meaning the charge switches at a rate three orders-of-magnitude less than the processor.
The interrupt circuit reduces the overhead needed for monitoring the voltage conditions of V1 and V2 outputs. Rather than forcing the microprocessor to constantly monitor the output of A/D converter 821, comparator 823 generates an interrupt whenever Vmux, the sample of either V1 or V2 outputs, drops outside a specified range. By turning on MOSFET 824, the INT interrupt pin on the microprocessor is pulled down, and invokes an event-driven interrupt. Only during the interrupt service routine, does the microprocessor need to look at or analyze the output of A/D converter 821.
The concept of an interrupt driven change in the control algorithm is illustrated in the exemplary flow chart 850 of
To prevent degradation of other regulated outputs other than the priority outputs V1 and V2 during the ISR routine 852, initiation of an interrupt clears a counter 856 and increments it by one each time through the loop as shown by operation 857. When the counter finally exceeds n times as determined by conditional 855, the algorithm jumps from the ISR loop 852 to charge V2 and V3 without resetting the interrupt. Once the charge transfer to V3 has occurred the interrupt detect 858 will determine that V1 is not yet compliant with its tolerance range and the converter will jump back to ISR tasks 852.
The algorithm can be adjusted in numerous ways depending on the mix of positive and negative supply voltages produced by the multiple output charge pump.
Regulating Multiple Charge-Pump Voltages; Charge pumps do not regulate voltage, but instead produce a time varying output that represents some fixed multiplier of the input voltage. The time-multiplexed-capacitor multiple output charge pump is no different in this regard. Moreover charge pumps are only efficient when the load voltage operates near the charge pump's nX multiple.
One common way to eliminate voltage variation in a charge pump's output is to combine it with a low drop-out linear regulator or LDO. Like conventional charge pumps, time-multiplexed-capacitor multiple output charge pump disclosed herein can also be combined with LDOs used to provide either pre-regulation to the charge pump, to provide post regulation, or both.
For example in system 880 of
V1=n1·Vy
V2=n2·Vy
V3=n3·Vy
Multiples of n include −2×, −1×, −0.5×, +0.5×, +1.5×, +2×, and +3×. For a lithium ion battery Vy is likely 3V or 2.7V in order to maximize operation over the full battery discharge life of 4.2V down to 3V.
In an alternative embodiment, system 900 of
While the intermediate voltages V1, V2 and V3 are given by fixed fractional or integer multiples n1, n2, and n3, the output voltages V5, V6 and V7 are determined by the LDO circuit and not the charge pump with one caveat, that the LDO's input must be higher than its output. In other words, the voltages the input to LDO 909 must be higher than its output so that V1>V5, the input to LDO 910 must be higher than its output so that V2>V6. and the input to LDO 911 must be higher than its output so that V3>V7.
In some instances not every output needs dedicated regulation. One solution to that scenario shown in schematic 940 of
As another embodiment of this invention, a time-multiplexed-capacitor charge pump can produce multiple independent outputs having the same voltage. Such a need arises when the same supply voltage is used for multiple purposes, e.g. for power, digital, analog and RF circuitry. To avoid noise and interference the supplies can be separated. For example, in circuits 880, 900 or 940, it is possible for V1=V2 while V1≠V3 using the disclosed time-multiplexing charge pump methods described herein.
For example in
So by successively charging the outputs V1 and V2 with the same bias, two independent outputs operating of the same voltage can generated, so that V1=Vbatt and V2=Vbatt but V1 and V2 are completely independent supplies.
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