1. Field of Invention
The present invention relates to a multiple-output DC-DC converter. More particularly, the present invention relates to a multiple-output, single-inductor boost DC-DC converter.
2. Description of Related Art
A voltage regulator (converter) is provided for taking an input voltage and providing a multiple of outputs of different voltage values. In general, a DC to DC voltage regulator may be used to convert a DC input voltage to either a higher or a lower DC output voltage. DC to DC converters with step-up/step-down characteristics are often required in applications where the input voltage and the output voltage requirements are incompatible. Many electronic systems require multiple output voltages from a single power source Vin. Vin may change over a wide range. For example, in an electronic system using 4 cells of alkaline battery connected in series, the battery pack voltage may drop from 6.6V, with new cells, to 3.6V when the battery is almost fully discharged. Further, one output Vo1 requires a constant 5V while another output Vo2 requires a constant 15V. For Vo1, the converter circuit needs to lower the input voltage when the input voltage is higher than 5V, but the converter need to raise the input voltage if the input voltage becomes lower than 5V.
One approach to achieve the voltage step up/down capability is to use a π-bridge buck-boost converter, as shown in
The π-bridge buck-boost converter requires two transistors and two diodes. Circuit topology is complicated and efficiency is low due to the extra rectifier loss on D1 and D2. For the π-bridge buck-boost converter, a sophisticated control circuit is required in order to regulate a stable output voltage over a wide range of input voltage.
Further, portable electronic applications typically require small but high-efficiency power converters. Oftentimes, such applications also require the power converters provide multiple outputs. To date, however, multiple-output power converters typically require multiple inductors or multiple transformer windings, one for each output, wherein each inductor or transformer winding utilizes a relatively large amount of circuit area. A conflict is thus presented in providing multiple-output power converters which are small in size.
There is a need for a multiple output DC-DC converter having the ability to provide two or more output voltages from one input voltage and use only one inductor.
One of the aspects of the invention is to provide a simple, high efficiency DC-DC converter to deliver multiple output voltages. One output voltage is higher than the input voltage, while other output voltages may require step-up conversions when the input voltage is relatively low or step-down conversions when the input voltage is relatively high.
One of the aspects of the invention is to provide a DC-DC regulator with minimum number of inductors, transistors and diodes.
One of the aspects of the invention is to provide a DC-DC converter with easy control and high efficiency.
To achieve the above and other aspects, one embodiment of the invention provides a power converter using a single inductor for providing multiple power outputs at least including a first output and a second output. The second output is higher than both the first output and a power source. The power converter includes: a main power switch for regulating the inductor current; a first switch for regulating the inductor current flow to the first output; a reference voltage; a first control loop, generating a first error signal in response to the first output and the reference voltage; a second control loop, generating a second error signal in response to the second output and the reference voltage; and a control logic, for controlling the operation states of the main power switch and the first switch in response to the first and second error signals. The second output does not require a switch and the power converter delivers power to the first and second outputs during the same switching cycle.
Another embodiment of the invention provides a method of charging a plurality of loads during the same switching cycle using a single inductor. The inductor is energized. Power energized in the inductor is sequentially delivered to a first one of the loads and not to any other loads, and further sequentially delivered power to a second one of the loads and not to any other loads. A last power-delivered load is used to reset the inductor current within the same switching cycle.
Still another embodiment of the invention provides a voltage regulation system for providing output boost regulation for two loads in a same switching cycle. The voltage regulation system includes: a power source; an inductor, having a first terminal electrically connected to the power source and a second terminal; a main power switch, having an input terminal electrically connected to the second terminal of the inductor, an output terminal and a gate terminal; a first switch, having an input terminal electrically connected to the second terminal of the inductor, an output terminal and a gate terminal; a first rectifier, having an input terminal electrically connected to the output terminal of the first switch and an output terminal for connecting to a first load; a second rectifier, having an input terminal electrically connected to the second terminal of the inductor and an output terminal for connecting to a second load; and voltage feedback loops and control logic, modulating the conduction duty cycle of the main power switch and the first switch based on voltages on the second load and the first load respectively. The second load, whose voltage resets the inductor current, does not require a series switch.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
FIGS. 1A˜1D illustrate conventional converters and voltage transfer ratio thereof.
FIGS. 4A˜4C illustrate timing and waveform diagrams of the embodiment when Vin=5V, Vin=4V, and Vin=6.6V are respectively demonstrated.
Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The multiple-output boost DC-DC converter has the ability to deliver a step up/down output as long as there is step-up output to reset the inductor current. Further, the power delivered to the first output, from light load to heavy load, is completely under the control of its regulation loop.
A first terminal of the inductor L1 is coupled to the power source Vin and a second terminal of the inductor L1 is coupled to first terminals (drain terminals) of the power switches Q1 and Q2 and to an anode terminal of the diode D2. The main power switch Q1 has an input terminal coupled to the inductor, an output terminal coupled to a first terminal of a sense resistor R1 and a gate terminal coupled to the gate driver. The sense resistor R1 has a second terminal tied to ground. The sense resistor R1 senses the current flowing through the power switch Q1.
The power switch Q2 has an input terminal coupled to the inductor, a gate terminal coupled to the gate driver and an output terminal coupled to the anode terminal of the diode D1. The cathode terminal of the diode D1 is coupled to a first terminal of the voltage-divider R2-R3, to the output capacitor Co1 and to the load RL1. The voltage-divider resistors R2 and R3 are serially connected and another terminal of R3 is tied to ground. Another terminal of the output capacitor Co1 is also tied to ground. The load RL1 is coupled across the output capacitor Co1. The output capacitor Co1 is required to reduce the voltage ripple on load RL1.
The cathode terminal of the diode D2 is coupled to a first terminal of the voltage-divider R4-R5, to the output capacitor Co2 and to the load RL2. The voltage-divider resistors R4 and R5 are serially connected and another terminal of R5 is tied to ground. Another terminal of the output capacitor Co2 is also tied to ground. The load RL2 is coupled across the output capacitor Co2. The output capacitor Co2 is required to reduce the voltage ripple on load RL2.
The gate driver includes two flip-flops 33 and 35. The set input terminal S of the flip-flop 33 receives a clock signal CK generated from an oscillator 37. The reset input terminal R of the flip-flop 33 receives an output signal from a comparator CMP2. The output terminal Q of the flip-flop 33 is coupled to the gate terminal of the power switch Q1 for controlling ON/OFF states of Q1. The set input terminal S of the flip-flop 35 also receives the clock signal CK generated from the oscillator 37. The reset input terminal R of the flip-flop 35 receives an output signal from a comparator CMP1. The output terminal Q of the flip-flop 35 controls ON/OFF states of the power switch Q2 via the level shifter 31. The configuration of the level shifter 31 is not specially limited.
The oscillator 37 generates the clock signal CK with a frequency of, for example but not limited by, 1 MHz to the flip-flops 33 and 35. The oscillator 37 also generates a reference triangular wave Ramp to the comparator CMP1.
The bandgap reference voltage generator 39 generates a reference voltage Vref to the error amplifiers EA1 and EA2. A proportion of Vo1, VR3, is derived via the voltage divider R2-R3, where VR3=Vo1*R3/(R2+R3). A proportion of Vo2, VR5, is derived via the voltage divider R4-R5, where VR5=Vo2*R5/(R4+R5). The error amplifier EA1 has a positive input terminal receiving Vref and a negative input terminal coupled to VR3. The output of the error amplifier EA1, Vea1, modulates the on-time (conduction) time of the power switch Q2. In other words, EA1 regulates the power flowing into Vo1. The error amplifier EA2 has a positive input terminal receiving Vref and a negative input terminal coupled to VR5. The output of the error amplifier EA2, Vea2, modulates the on-time (conduction) time of the power switch Q1. In other words, EA2 indirectly regulates the power flowing into Vo2. The oscillator 37 outputs the clock signal CK to the flip-flops 33 and 35 for turning on the power switches Q1 and Q2.
Please refer to both
As shown in
After Q1 is ON, the inductor current flows into the power switch Q1 and then to ground via the resistor R1. Because a current flows through the resistor R1, a voltage Vsen is occurred. Since voltage VR5 is coupled to the negative input of the error amplifier EA2, it outputs an error voltage Vea2 in response to the difference between VR5 and Vref. On the other hand, the comparator CMP2 outputs a pulse for resetting the flip-flop 33 when Vsen rises above the Vea2 level. So, a logic low signal from the output terminal of the flip-flop 33 shuts down the power switch Q1. Basically, the control loop responds to the status of VR5. If VR5 is lower than Vref, then Vea2 increases, thus allowing longer duty cycle of Q1.
After T1, the inductor current flows into Vo1 via Q2 and D1. Since Vin=Vo1=5V, the inductor current remains constant. The error amplifier EA1 outputs an error voltage Vea1 in response to the difference between VR3 and Vref. On the other hand, comparator CMP1 output a pulse for resetting the flip-flop 35 when the ramp signal rises above the Vea1 level. So, a logic low signal from the output terminal of the flip-flop 35, via the level shifter 31, shuts down the power switch Q2 at T2.
At T2, both Q1 and Q2 shut down and the inductor current now flows into Vo2. The inductor current is decreased at a rate of (Vin−Vo2)/L1=−10V/L1. The inductor reaches zero at T3.
Briefly speaking, at T0, both Q1 and Q2 turn on. From T0 to T1, energy is delivered and accumulated in the inductor L1 and not delivered to Vo1 and Vo2 yet. At T1, Q1 turns off while Q2 remains on, so power begins to flow into Vo1 but not to Vo2 yet. When sufficient power is delivered to Vo1, Q2 turns off at T2. Now, power is delivered to Vo2 but not to Vo1. When all remaining power is delivered to Vo2 at T3, the inductor current reaches zero and no power is delivered to Vo1 and Vo2. From the above description, it is clear that Vea1 determines the conduction time of Q2, while Vea2 determines the conduction time of Q1.
The second switching cycle in
As described above, the converter delivers to all output voltages during a same switching cycle. And as long as there exists an output voltage higher than the input voltage, the converter has certain capability to step down Vin to Vo1, as shown in situation depicted by
Each output voltage has a feedback loop and an error amplifier to create its own error voltage. The voltage feedback loop and control logic 51 also includes a bandgap reference voltage generator and an oscillator. The gate drivers and level shifters 52 include flip-flops for the main power switch and the high-side power switches and level shifters for the high-side power switches. The operation and inductor current waveforms of the DC-DC converter according to the second embodiment are similar to the first embodiment and the details thereof are omitted for simplicity.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing descriptions, it is intended that the present invention covers modifications and variations of this invention if they fall within the scope of the following claims and their equivalents.