Patent Application
20080080103
In
In some embodiments, VOUT4 may be less than VOUT3, each of VOUT3 and VOUT4 may less than each of VOUT1 and VOUT2, and VSOURCE may be greater than each of VOUT1, VOUT2, VOUT3, and VOUT4. In other embodiments, one or more of VOUT3 and VOUT4 may greater than on or more of VOUT1 and VOUT2, and VSOURCE may be less than one or more of VOUT1, VOUT2, VOUT3, and VOUT4.
As described above, one of the VOUT, and VOUT2 may be provided to die 130 as the supply voltage VIN. In some embodiments, before VIN is provided to die 130, a startup circuit 139 may be used by die 130 to receive VSTART to provide an initial supply voltage to output control circuit 137 and converter circuit 138 during a mode, such as a startup or reset mode, of apparatus 100. In some embodiments, when VIN is provided to die 130 from output circuit 120, die 130 may stop using VSTART and start using VIN as the supply voltage for its circuitry including output control circuit 137 and converter circuit 138.
Output control circuit 137 may respond to a sense voltage VSENSE, at a sense node 132 or connection 132. VSENSE, is related to VOUT1 such that VSENSE1 may carry feedback information of VOUT1. For example, VSENSE1 may be substantially equal to VOUT1 or may be proportional to VOUT1. In some embodiments, at least a portion of connection 132 may be outside die 130 and outside output circuit 120. For example at least a portion of connection 132 may be a conductive trace on a circuit board where die 130 may output circuit 120 may reside. In
In some embodiments, the voltage value of VOUT1 may be determined by the duty cycle of CTL1 and the voltage value of VSOURCE. In some embodiments, CTL1 may be a periodic signal having frequency. The duty cycle of CTL1 may be and the ratio of the on-time over the cycle time (the inverse of the frequency) of CTL1. Within each cycle of CTL1, the on-time of CTL1 may correspond to a time interval when CTL1 has a high signal level, and the off-time interval of CTL1 may correspond to a time interval when CTL1 has a low signal level.
As shown in
In some embodiments, output control circuit 137 may include a signal generator, such as pulse width modulation (PWM) circuitry or other type of circuitry, to provide CTL1 and CTL2 with duty cycles such that the voltage value of VOUT1 and VOUT2 may be determined by the duty cycle of CTL1 or CLT2 and VSOURCE, as described above.
In
In some embodiments, VSOURCE may have range of about 8 volts to about 20 volts, VOUT1 may be about 3.3 volts, VOUT2 may be about five volts, VOUT3 may be in a range of about 1.5 volts to about 1.8 volts, and VOUT4 may be in a range of about 0.35 volt to about 1.05 volts. In other embodiments, the voltage values of
In
As described above, one of VOUT5, VOUT6, VOUT7 (e.g., VOUT5) may be provided to die 330 as the supply voltage VIN. In some embodiments, before VIN is provided to die 330, a startup circuit 339 may be used by die 330 to receive VSTART to provide an initial supply voltage to output control circuit 337 and converter circuit 338 during a mode, such as a startup or reset mode, of apparatus 300.
As shown in
Output unit 340 of output circuit 320 includes transistors 341 and 342, an inductor 343, and a capacitor 344 to generate VOUT5. Control signals CTL1A and CTL1B may be used to selectively turn on and off transistors 341 and 342 such that node 345 may be either coupled to source node 311 and decoupled from a supply node 346 (e.g., ground) or decoupled from source node 311 and coupled to supply node 346. For example, transistor 341 may be selectively turned on and transistor 342 may be selectively turned off to couple node 345 to source node 311 and decoupled node 345 from supply node 346. In another example, transistor 341 may be selectively turned off and transistor 342 may be selectively turned on to decouple node 345 from source node 311 and couple node 345 to supply node 346. Transistors 341 and 342 may be turned on and off based on the frequencies of the CTL1A and CTL1B signals such that node 345 may have many switching cycles. The switching cycles at node 345 may correspond to the frequency of the CTL1A or CTL1B. In some embodiments, CTL1A and CLT1B may have the same frequency but may have opposite phase (e.g., 180 degrees out of phase). In other embodiments, CTL1A and CLT1B may be complementary signals.
Selectively turning on and off transistors 341 and 342 using CTL1A and CTL1B and the action of L-C network (formed by inductor 343 and capacitor 344) may convert VSOURCE into VOUT5 When transistors 341 and 342 are selectively turned on an off, inductor 343 and capacitor 344 may go through an energizing interval and de-energizing interval in each cycle of CTL1 or CTL1B. The energizing interval may happen during each time node 345 is coupled to source node 311 and decoupled from supply node 346. The de-energizing interval may happen during each time node 345 is decoupled from source node 311 and coupled to supply node 346. During the energizing interval, voltage from source node 311 may be transferred to node 345. During the de-energizing interval, the transfer of voltage from source node 311 to node 345 may be suspended and the voltage from node 345 may be transferred to output node 321 as VOUT5. The voltage value of VOUT5 may be determined by the duty cycle of CTL1A or CTL1B and VSOURCE.
VOUT6 and VOUT7 may be generated in a similar fashion by units 350 and 359 of output circuit 320. For example, output unit 350 may include transistors 351 and 352, an inductor 353, and a capacitor 354 to generate VOUT6 based on VSOURCE. The value of VOUT6 may be determined by the duty cycle of CTL2A or CTL2B and VSOURCE. In some embodiments, CTL2A and CLT2B may have the same frequency but may have opposite phase. Output unit 359 may use control signal CTL3 and VSOURCE to generate VOUT7. The value of VOUT7 may be determined by duty cycle of CTL3 and VSOURCE.
VSENSE5, VSENSE6, and VSENSE7 at sense nodes or connections 332, 336, and 349 may provide feedback information of VOUTS, VOUT6, and VOUT7, respectively, to die 330. In some embodiments, based on VSENSE5, VSENSE6, and VSENSE7, die 330 may control VOUT5, VOUT6, and VOUT7, for example, by keeping VOUT5, VOUT6, and VOUT7 within their voltage ranges. In some embodiments, die 330 may change the timing of the CTL1A, CTL1B, CTL2A, CTL2B, or CTL3, based on VSENSE5, VSENSE6, and VSENSE7, to control VOUT5, VOUT6, or VOUT7. For example, when VSENSE5 is at a value indicating that VOUT5 may be at or outside a lower limit of the voltage range of VOUT5, die 330 may activate CTL1A sooner (in comparison with when VOUT5 is within the voltage range) so that transistor 341 may be turned on sooner to increase the voltage value of VOUT5 to keep VOUT5 within its voltage range. Die 330 may use VSENSE6 and VSENSE7 in a similar fashion to control VOUT6 and VOUT7.
In some embodiments, two or more of the inductors of output circuit 320 (e.g., inductors 343 and 353) may be arranged such that at least one portion of output circuit 320 may be part of a multi-phase converter arrangement. For example, in a multi-phase converter arrangement in some embodiments, output nodes 321 and 322 may be the same output node (i.e., tied together), one of the capacitors 344 and 354 and one of the VSENSE5 and VSENSE6 may be omitted. In other embodiments, the inductors of output circuit 320 (e.g., inductors 343 and 353) may form transformer structures.
Output control circuit 337 includes a control unit 360 and drive units 361, 362 and 363. Drive units 361, 362 and 363 may include circuitry, e.g., buffers, to appropriately drive CTL1A, CTL1B, CTL2A, CTL2B, and CTL3. In some embodiments, control unit 360 may include PWM circuitry 365 to generate CTL1A, CTL1B, CTL2A, CTL2B, and CTL3. In some embodiments, control unit 360 may include a comparator circuitry to compare each of VSENSE5, VSENSE6, and VSENSE7 with one or more known voltages to keep VOUT5, VOUT6, and VOUT7 within their voltage ranges.
Converter circuit 338 includes a control unit 370 and drive units 371, 372 and 373 to provide CTL4A, CTL4B, CTL5A, CTL5B, and CTL6 to corresponding output units 380, 390, and 399. Drive units 371, 372 and 373 may include circuitry, e.g., buffers, to appropriately drive CTL4A, CTL4B, CTL5A, CTL5B, and CTL6. Converter circuit 338 may include PWM circuitry 375 to generate CTL4A, CTL4B, CTL5A, CTL5B, and CTL6. Control unit 370 may receive VSENSE8, VSENSE9, and VSENSE10, which may carry feedback information of VOUT8, VOUT9, and VOUT10, respectively. In some embodiments, converter circuit 338 and the combination of output control circuit 337 and output circuit 320 may operate similar fashions.
In
In some embodiments, control unit 370 controls the transfer of power from supply node 331 to switch node 385 by controlling the switching cycles at switch node 385. The switching cycles at switch node 385 may correspond to the frequency of the CTL4A or CTL4B. In some embodiments, CTL4A and CLT4B may be periodic signals with the same frequency but may have opposite phase. Each switching cycle at switch node 385 may include an energizing interval and a de-energizing interval. During the energizing interval, control unit 370 may couple switch node 385 to supply node 331 through transistor 381 to transfer power from supply node 331 to switch node 385. During the de-energizing interval, control unit 370 may decouple switch node 385 from supply node 331 to suspend the transfer of power from supply node 331 to switch node 385 and transfer power from switch node 385 to die output node 333. By coupling switch node 385 to and decoupling switch node 385 from supply node 331 in each switching cycle using CLT4A and CTL4B, control unit 370 may generate VOUT8 based on VIN and the duty cycle of CLT4A or CTL4B. Switch node 385 may be coupled to supply node 331 through transistor 381 when transistor 381 is turned on, and decoupled from supply node 331 when transistor 381 is turned off. Switch node 385 is coupled to supply node 346 through transistor 382 when transistor 382 is turned on, and decoupled from supply node 346 when transistor 382 is turned off.
Control unit 370 may be configured such that it may provide CLT4A and CTL4B in a fashion that only one of the transistors 381 and 382 may be turned on at a time. In some embodiments, control unit 370 may be configured such that it may provide CLT4A and CTL4B in a fashion that may turn off both transistors 381 and 382 before it turns on one of the transistors (e.g., either 381 or 382) to avoid contention at switch node 385.
In some embodiments, control unit 370 may include a comparator with a switching hysterisis control circuitry such that control unit 370 maintains the states (on state or off state) of transistors 381 and 382 when VSENSE8 indicates that the voltage value of VOUT8 is within the voltage range of VOUT8. In the embodiments with the switching hysterisis control circuitry, control unit 370 may change the states of transistors 381 and 382 only when VSENSE8 reaches the lower voltage value of the voltage range of VOUT8 or the upper voltage value of the voltage range of the voltage range of VOUT8. For example, control unit 370 may turn on transistor 381 when VSENSE8 reaches the lower voltage value of the voltage range of VOUT8 and turn on transistor 382 when VSENSE8 reaches the upper voltage value of the voltage range of VOUT8.
Output units 390 and 399 may generate VOUT9 and VOUT10 in a fashion similar to that of output unit 380. For example, output unit 390 may include transistors 391 and 392, a switch node 395, an inductor 393, and a capacitor 394 to generate VOUT9. Control signals CTL5A and CTL5B may be used by output unit 390 to turn on and off transistor 391 and 392. Control signal CTL6 may be used by output unit 399. Output units 390 and 399 may also use VSENSE9 and VSENSE10 to control VOUT9 and VOUT10 in a fashion similar to that of output unit 380.
In some embodiments, two or more of the inductors of converter circuit 338 (e.g., inductors 383 and 393) may be arranged such that at least one portion of converter circuit 338 may include a multi-phase converter arrangement. For example, in a multi-phase converter arrangement in some embodiments, output nodes 333 and 334 may be the same die output node (i.e., tied together), one of the capacitors 384 and 394 and one of the VSENSE8 and VSENSE9 may be omitted. In these embodiments, drive units 371 and 372, and output units 380 and 390 may form a part of the multi-phase converter arrangement to drive the voltage signal at the die output node of the multi-phase converter arrangement. In other embodiments, the inductors of converter circuit 338 (e.g., inductors 383 and 393) may form transformer structures.
In some embodiments, output control circuit 337 and converter circuit 338 may be configured to operate at different frequencies. For example, output control circuit 337 and converter circuit 338 may be configured to operate at different frequency such that each of CTL4A, CTL4B, CTL5A, CTL5B, and CTL6 may have a higher frequency than each of CTL1A, CTL1B, CTL2A, CTL2B, and CTL3. Thus, in some embodiments, converter circuit 338 may switch transistors (e.g., transistors 381, 382, 391, and 392) at a higher frequency than output control circuit 337 switching transistors (e.g., transistors 341, 342, 351, and 352) of output circuit 320. Thus, in some embodiments, apparatus 300 may include a hybrid converter having both a relatively high-frequency or high-speed switching converter (e.g., converter circuit 338) and a relatively low-frequency or low-speed switching controller (e.g., output control circuit 337) to convert a voltage source (e.g., VSOURCE) into multiple output voltages (e.g.,VOUT5 through VOUT10).
In some situations, a source voltage such as VSOURCE may be relatively high such that high-speed conventional converters may be unable to convert the source voltage into multiple output voltages because of high-voltage limitation. For example, some circuit elements, such as on-die switching transistors on the dice of the conventional converters, may be unable to withstand the high voltage of the source voltage, thereby limiting the value of the source voltage that conventional high-speed converters may use. In other situations, multiple separate low-speed conventional converters may be used to convert a high voltage source into multiple output supply voltages. Multiple separate low-speed conventional converters may occupy more space on a circuit board. Therefore, the use of multiple separate low-speed conventional converters may be limited by board space.
Apparatus 300, however, may overcome both the high-voltage limitation of high-speed integrated converters and space limitation of low-speed conventional converters. For example, the low-speed switching of output control circuit 337 of die 330 of
In some embodiments, V1OUT or V2OUT may correspond to at least one of VOUT1 and VOUT2 of
In
Processing unit 410 may process data transferred to and from other components via bus 460. Processing unit 410 may include a general-purpose processor or an application specific integrated circuit (ASIC). Processing unit 410 may be a single core processing unit or a multiple-core processing unit.
In some embodiments, voltage regulator 402 may include an embodiment of apparatus 100 of
Since voltage regulator 402 may include an embodiment of apparatus 100 or apparatus 300, voltage regulator 402 may include a hybrid voltage regulator with both a high-speed converter and a low-speed output control circuit in a single die, such as those described in
System 400 may include computers (e.g., desktops, laptops, hand-helds, servers, Web appliances, routers, etc.), wireless communication devices (e.g., cellular phones, cordless phones, pagers, personal digital assistants, etc.), computer-related peripherals (e.g., printers, scanners, monitors, etc.), entertainment devices (e.g., televisions, radios, stereos, tape and compact disc players, video cassette recorders, camcorders, digital cameras, MP3 (Motion Picture Experts Group, Audio Layer 3) players, video games, watches, etc.), and the like.
In method 500 of
The individual activities of method 500 do not have to be performed in the order shown or in any particular order. Some activities may be repeated, and others may occur only once. Various embodiments may have more or fewer activities than those shown in
The above description and the drawings illustrate some embodiments of the invention to enable those skilled in the art to practice the embodiments of the inventions. Other embodiments may incorporate structural, logical, electrical, process, and other changes. In the drawings, like features or like numerals describe substantially similar features throughout the several views. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Therefore, the scope of various embodiments of the invention is determined by the appended claims, along with the full range of equivalents to which such claims are entitled.
The Abstract is provided to comply with 37 C.F.R. ยง 1.72(b) requiring an abstract that will allow the reader to quickly ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
