Claims
- 1. A multiple processor integrated circuit comprises:
a plurality of processing units; cache memory; memory controller operably coupled to system memory; internal bus operably coupled to the plurality of processing units, the cache memory and the memory controller; packet manager operably coupled to the internal bus; node controller operably coupled to the internal bus; first configurable packet-based interface; second configurable packet-based interface; and switching module operably coupled to the packet manager, the node controller, the first configurable packet-based interface, and the second configurable packet-based interface, wherein the multiple processor integrated circuit is configured, in accordance with first configuration information, to provide a tunnel, a bridge, or a tunnel-bridge hybrid for packets transceived via the first configurable packet-based interface, and wherein the multiple processor integrated circuit is configured, in accordance with second configuration information, to provide the tunnel, the bridge, or the tunnel-bridge hybrid for packets transceived via the second configurable packet-based interface.
- 2. The multiple processor integrated circuit of claim 1 further comprises:
header register section operable to store first header information of the first configuration information and to store second header information of the second configuration information, wherein the first header information indicates the tunnel, the bridge interface, or the tunnel-bridge hybrid processing of the packets transceived via the first configurable packet-based interface and wherein the second header information indicates the tunnel, the bridge, or the tunnel-bridge hybrid processing of the packets transceived via the second configurable packet-based interface.
- 3. The multiple processor integrated circuit of claim 1 further comprises:
the first configurable packet-based interface is configured to provide at least one of a HyperTransport (HT) input/output port and a System Packet Interface (SPI) input/output port; and the second configurable packet-based interface is configured to provide at least one of the HyperTransport (HT) input/output port and the System Packet Interface (SPI) input/output port.
- 4. The multiple processor integrated circuit of claim 1 further comprises:
the first and the second configurable packet-based interfaces applying a set of ordering rules for the packets when the multiple processor integrated circuit is configured to provide the tunnel, the bridge, or the tunnel-bridge hybrid for packets transceived via the first or second configurable packet-based interfaces; and the node controller applying the set of ordering rules for the packets as being received via a single input/output port regardless of whether the packets were received via the first or the second configurable packet-based interface, wherein the set of ordering rules includes non-post commands to a destination are issued in order.
- 5. The multiple processor integrated circuit of claim 1, wherein providing the tunnel processing of the packets further comprises:
forwarding a downstream packet received from a downstream node while maintaining node identity; interpreting an upstream packet received from an upstream node to determine a destination of the upstream packet; when the multiple processor integrated circuit is the destination of the upstream packet, processing the upstream packet; and when the multiple processor integrated circuit is not the destination of the upstream packet, forwarding the upstream packet to the downstream node.
- 6. The multiple processor integrated circuit of claim 1, wherein providing the bridge processing of the packets further comprises:
interpreting a secondary packet received from a secondary chain to determine a destination of the secondary packet; when the multiple processor integrated circuit is the destination of the secondary packet, processing the secondary packet; when the multiple processor integrated circuit is not the destination of the secondary packet, altering header information of the secondary packet to identify the multiple processor integrated circuit as a source of the secondary packet to produce a readdressed secondary packet; forwarding the readdressed secondary packet on to a primary chain; interpreting a primary packet received via a primary chain to determine a destination of the primary packet; when the multiple processor integrated circuit is the destination of the primary packet, processing the secondary packet; when the multiple processor integrated circuit is not the destination of the primary packet, identifying a node of the secondary chain as the destination of the primary packet; altering header information of the primary packet to identify the node as the destination of the primary packet to produce a readdressed primary packet; and providing the readdressed primary packet on the secondary chain.
- 7. The multiple processor integrated circuit of claim 1, wherein providing the tunnel-bridge hybrid processing of the packets further comprises:
interpreting a packet of the packets received from a chain to determine a destination of the packet; when the multiple processor integrated circuit is the destination of the packet, processing the packet; and when the multiple processor integrated circuit is not the destination of the packet, forwarding the packet on to the chain.
- 8. The multiple processor integrated circuit of claim 7, wherein the forwarding the packet on to the chain further comprises:
determining an address of the destination of the packet; comparing the address with an address range associated with a link supporting the chain; when the address is within the address range, issuing the packet on the link; and when the address is not within the address range, issuing the packet on a default link.
- 9. The multiple processing integrated circuit of claim 8, wherein the issuing the packet further comprises:
maintaining order of the packets regardless of identity of a destination node.
- 10. The multiple processor integrated circuit of claim 7 further comprises:
interpreting the packet to determine whether the packet is part of a request or a response; when the packet is part of the request, determining the destination of the packet based on an address contained within the packet; and when the packet is part of the response, determining the destination of the packet based on a unit identification code.
- 11. The multiple processor integrated circuit of claim 1 further comprises:
at least one of the first configurable packet-based interface, the second packet-based interface, the node controller, and the packet manager providing at least one of the tunnel processing of the packets, the bridge processing of the packets, and the tunnel-bridge hybrid processing of the packets.
- 12. A packet-based interface comprises:
input/output module operably coupled to amplify inbound data and to drive outbound packets; media access control module operably coupled to the input/output module, wherein the media access control module formats outbound data to produce the outbound packets in accordance with a packet-based protocol and formats the amplified inbound data into inbound packets in accordance with the packet-based protocol; and tunnel-bridge hybrid module operably coupled to:
interpret a packet of the inbound packets to determine a destination of the packet; when the destination of the packet is a local module of the packet-based interface, providing the packet to the local module; and when the destination of the packet is not local to the packet-based interface, forwarding the packet to the media access control module such that the packet is converted into an outbound packet.
- 13. The packet-based interface of claim 12, wherein the packet-based protocol further comprises at least one of HyperTransport (HT) and System Packet Interface (SPI).
- 14. The packet-based interface of claim 12 further comprises:
the tunnel-bridge hybrid module applying a set of ordering rules for the inbound packets, wherein the set of ordering rules includes non-post commands to a destination are issued in order.
- 15. The packet-based interface of claim 12, wherein the forwarding the packet further comprises:
determining an address of the destination of the packet; comparing the address with an address range associated with a link; when the address is within the address range, issuing the packet on the link; and when the address is not within the address range, issuing the packet on a default link.
- 16. The packet-based interface of claim 15, wherein the issuing the packet further comprises:
maintaining order of the packets regardless of identity of a destination node.
- 17. The packet-based interface of claim 12 further comprises:
interpreting the packet to determine whether the packet is part of a request or a response; when the packet is part of the request, determining the destination of the packet based on an address contained within the packet; and when the packet is part of the response, determining the destination of the packet based on a unit identification code.
- 18. A processing system comprises:
a plurality of multiple processor devices, wherein each of the plurality of multiple processor devices includes a first packet-based interface and a second packet-based interface, wherein one of plurality of multiple processor devices functions as a host for the processing system and remaining ones of the plurality of multiple processor devices function as bridges to provide peer-to-peer communication among the remaining one of the plurality of multiple processor devices.
- 19. The processing system of claim 18, each of the plurality of multiple processor devices further comprises:
a plurality of processing units; cache memory; memory controller operably coupled to system memory; internal bus operably coupled to the plurality of processing units, the cache memory and the memory controller; packet manager operably coupled to the internal bus; node controller operably coupled to the internal bus; and switching module operably coupled to the packet manager, the node controller, the first packet-based interface, and the second packet-based interface.
- 20. The processing system of claim 19 further comprises:
the first packet-based interface is configured to provide at least one of a HyperTransport (HT) input/output port and a System Packet Interface (SPI) input/output port; and the second configurable packet-based interface is configured to provide at least one of the HyperTransport (HT) input/output port and the System Packet Interface (SPI) input/output port.
- 21. The processing system of claim 19 further comprises:
the first and the second packet-based interfaces applying a set of ordering rules for the packets transceived via the first or second configurable packet-based interfaces; and the node controller applying the set of ordering rules for the packets as being received via a single input/output port regardless of whether the packets were received via the first or the second packet-based interface, wherein the set of ordering rules includes non-post commands to a destination are issued in order.
- 22. The processing system of claim 19, wherein providing the bridge processing of the packets further comprises:
interpreting a secondary packet received from a secondary chain to determine a destination of the secondary packet; when the multiple processor integrated circuit is the destination of the secondary packet, processing the secondary packet; when the multiple processor device is not the destination of the secondary packet, altering header information of the secondary packet to identify the multiple processor device as a source of the secondary packet to produce a readdressed secondary packet; forwarding the readdressed secondary packet on to a primary chain; interpreting a primary packet received via a primary chain to determine a destination of the primary packet; when the multiple processor device is the destination of the primary packet, processing the secondary packet; when the multiple processor device is not the destination of the primary packet, identifying another one of the plurality of multiple processor devices on the secondary chain as the destination of the primary packet; altering header information of the primary packet to identify the another one of the plurality of multiple processor devices as the destination of the primary packet to produce a readdressed primary packet; and providing the readdressed primary packet on the secondary chain.
- 23. A processing system comprises:
a plurality of multiple processor devices, wherein each of the plurality of multiple processor devices includes a first packet-based interface and a second packet-based interface, wherein one of plurality of multiple processor devices functions as a host for the processing system and remaining ones of the plurality of multiple processor devices function as tunnel-bridge hybrids to provide peer-to-peer communication among the remaining one of the plurality of multiple processor devices.
- 24. The processing system of claim 23, wherein each of the multiple processor devices further comprises:
a plurality of processing units; cache memory; memory controller operably coupled to system memory; internal bus operably coupled to the plurality of processing units, the cache memory and the memory controller; packet manager operably coupled to the internal bus; node controller operably coupled to the internal bus; and switching module operably coupled to the packet manager, the node controller, the first packet-based interface, and the second packet-based interface.
- 25. The processing system of claim 24, wherein the node controller further comprises:
header register section operable to store first header information and second header information, wherein the first header information indicates tunnel-bridge hybrid processing of the packets transceived via the first packet-based interface and wherein the second header information indicates the tunnel-bridge hybrid processing of the packets transceived via the second packet-based interface.
- 26. The processing system of claim 25 further comprises:
the first packet-based interface is configured to provide at least one of a HyperTransport (HT) input/output port and a System Packet Interface (SPI) input/output port; and the second packet-based interface is configured to provide at least one of the HyperTransport (HT) input/output port and the System Packet Interface (SPI) input/output port.
- 27. The processing system of claim 25 further comprises:
the first and the second packet-based interfaces applying a set of ordering rules for the packets; and the node controller applying the set of ordering rules for the packets as being received via a single input/output port regardless of whether the packets were received via the first or the second packet-based interface, wherein the set of ordering rules includes non-post commands to a destination are issued in order.
- 28. The processing system of claim 25, wherein providing the tunnel-bridge hybrid processing of the packets further comprises:
interpreting a packet of the packets received from a chain to determine a destination of the packet; when the multiple processor device is the destination of the packet, processing the packet; and when the multiple processor device is not the destination of the packet, forwarding the packet on to the chain.
- 29. The processing system of claim 28, wherein the forwarding the packet on to the chain further comprises:
determining an address of the destination of the packet; comparing the address with an address range associated with a link supporting the chain; when the address is within the address range, issuing the packet on the link; and when the address is not within the address range, issuing the packet on a default link.
- 30. The processing system of claim 29, wherein the issuing the packet further comprises:
maintaining order of the packets regardless of identity of a destination node.
- 31. The processing system of claim 28 further comprises:
interpreting the packet to determine whether the packet is part of a request or a response; when the packet is part of the request, determining the destination of the packet based on an address contained within the packet; and when the packet is part of the response, determining the destination of the packet based on a unit identification code.
Parent Case Info
[0001] The present application claims priority under 35 U.S.C. 119(e) to the following applications, each of which is incorporated herein for all purposes:
[0002] (1) provisional patent application entitled SYSTEM ON A CHIP FOR NETWORKING, having an application No. of 60/380,740, and a filing date of May 15, 2002; and
[0003] (2) provisional patent application having the same title as above, having an application No. of 60/419,032, and a filing date of Oct. 16, 2002.
Provisional Applications (2)
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Number |
Date |
Country |
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60380740 |
May 2002 |
US |
|
60419032 |
Oct 2002 |
US |