Patent Application
20080008255
Preferred features of the disclosure will now be described, for the sake of illustration only, with reference to the following figures in which:
In
The units 21, 22, 23 and 24 of the downstream path may have access to a shared buffer 51 called BufDD, which is partitioned into two sections BufDD0 and BufDD1. As described in detail below, data passes in a pipeline through the units 21, 22, 2324 by being written to the BufDD by one of these units, and then being read back from the buffer BufDD by the next unit in the pipeline. Conversely the units 21, 22, 23 and 24 may be operated simultaneously too.
Similarly, the units 42, 34, 35, 36 and 37 have access to a shared buffer 52 called BufDU, which is partitioned into two sections BufDU0 and BufDU1. Data passes along the upstream pipeline by being written to BufDU by one of the units of the pipeline, and then being read back from buffer BufDU by the next unit in the pipeline.
Furthermore, whereas in
Furthermore, in comparison to the known system, the embodiment includes a downstream buffer unit 41 and an upstream buffer unit 42. As described below, each of these buffer units 41, 42 includes a respective FIFO buffer for each of the channels. In an alternative arrangement, described below, the buffer units 41, 42 instead may include a respective ping-pong buffer for each of the channels.
In the downstream path, the units 21, 22, 23 and 24 of the embodiment each process data in respect of the channels sequentially, thereby acting as a pipeline along which data is passed. The data they generate is stored in the buffer unit 41. The unit 25 simultaneously (or with time multiplexing) reads data from the all four buffers of the buffer unit 41, and after appropriate filtering, interpolation and decimation, passes this data in respect of all four channels to the analogue front-end interface 1. In the downstream path, data in respect of all four channels after being processed by different signal processing modules passes simultaneously (or with time multiplexing) through the units 31, 32, 33, and is written simultaneously into the respective buffers of the buffer unit 42. Data is then read out of the buffer unit 42 channel-by-channel sequentially, and processed sequentially by the units 34, 35, 36, 37.
The embodiment is preferably arranged to be able to operate a number of different communication standards, with different ones of the channels using different ones of the standards. To handle cases including ADSL2(+) without excessively complex rate adaptation, the embodiment is designed to operate at a symbol rate on each channel of 4312.5 Hz (that is a timeslot duration T of about 231.9). Suppose that the maximum symbol rate required of any channel is f1, and that the operating frequency of the hardware modules is given by f2. Then, the number of channels C is such that Cf1/f2 is no greater than the number of cycles required by each of the hardware units 21, 22, 23, 24, 34, 35, 36, 37 to perform its processing in respect of a single symbol. Note that for state of the art designs, the processing of the functional blocks 21, 22, 23, 24, 34, 35, 36, 37 could be distributed over either or single or multiple hardware engines or processor cores. DMT system require symbol based processing whereas the state of art processors or hardware engines are capable of computing a complete IFFT, FFT symbol over a fraction of a complete symbol period.
The scheduling of the downstream path of the embodiment is shown in
Subsequently, the data generated for channel 0 is transmitted by the unit 25 and the interface 1 over the channel 0. This transmission may for example begin during the third sub-timeslot. However, more typically, the buffer associated with channel 0 is large enough to store more than one symbol, and is arranged to store more than one symbol's worth of samples at any one time. The data generated for channel 0 in the second sub-timeslot of
Similarly, data in respect of channel 1 is processed by the units 21, 22 during the second sub-timeslot, by the units 23 and 24 during the third timeslot, and transmitted by the unit 25 at some time after the end of the 3rd sub-timeslot.
The scheduling of the other downstream channels follows this principle mutis mutandis. Note that at all times HPF unit 25 is simultaneously (or with time multiplexing) reading data from the downstream buffer 41 and transmitting it over all four channels.
The scheduling of the upstream path of the embodiment is shown in
Similarly, data in respect of channel 1, accumulated in the buffer of the buffer unit 42 corresponding to channel 1, is processed by the units 35, 36 during the second sub-timeslot, and by the unit 37 during the third timeslot.
The scheduling of the other upstream channels follows this principle. Note that at all times the units 31, 32, 33 are simultaneously transferring upstream data received over all four channels, and storing it in the upstream buffer 42. We now turn to considering the case in which the channels are not required to transmit at their maximum capacity.
Consider a case in which ND=64 symbols have to be transmitted in NT timeslots. In other words, in a time period of NT timeslots only NE symbols have to be processed. NT=64(1+rCE). To slow down the processing in respect of any given channel, certain units of the DMT processor (units 21, 22, 23, 24 in the upstream direction, and units 34, 35, 36, 37 in the downstream direction) are idle in respect of certain ones of the timeslots corresponding that channel. Assuming a timeslot numbering starting from 0, Table 1 illustrates one suitable allocation of which timeslots are unused during a period of NT in order to produce each of the 15 possible values of rCE. The corresponding values of ICE are given for N values of 4096 and 2048.
The decision of whether to be idle in respect of a given timeslot may be made dynamically, rather than being controlled based on predefined unused timeslots. This can be done by the downstream and upstream rate converter (RC) logic units 43, 44.
One way in which this can be done, considering firstly the downstream direction, is the case that the buffers in the buffer unit 41 are each circular FIFO buffers. The PAR unit 23 writes a complete symbol into the FIFO in a burst at a fixed time, while samples are extracted from the unit 25 at a constant rate. The writing of the data into the FIFO buffer is done between memory reads. In other words, the memory write and memory read are time multiplexed. Alternatively the memory read and writes could also be sequential. Each FIFO buffer has a write pointer (W) for writing data from the PAR unit 23, and a read pointer (R) used by the HPF unit 25. Based on the values of W and R, the embodiment can determine if the FIFO buffer has enough data to transmit. Let S=66N/64 where N is the symbol size of 4K or 2K, and let L be the size of the buffer, which in the downstream direction is preferably at least 2 times S. Just before a timeslot in which the QT unit 21 is about to start work on a data for a given channel, the RC logic unit 43 determines whether (W−R+L) mod L>2S. If so, then there is still sufficient data in the FIFO to be transmitted in two timeslots, and the RC logic unit 43 sends control signals to ensure that the QT unit 21 does not start processing. Conversely, if (W−R+L) mod L≦2S, then the logic unit 43 controls the QT unit 21 to start operation, and the subsequent modules follow. This mechanism adapts to the different data rate automatically without having to predefine the unused frame timeslots. Note that instead of the RC logic unit 43 controlling the QT unit 21, it may alternatively send control signals to the PMS-TC section 3, ensuring that data is not input into the section 2 in respect of that channel in the given timeslot.
For a timing advance adjustment by an amount TA, the write pointer is adjusted such that the new value is (W−TA+L) mod L. Some unsent data in the FIFO buffer would then be overwritten. TA cannot be more than one symbol, so the corruption is less than one symbol. During the timing advance adjustment there is no need to check if the FIFO buffer has sufficient space. The unused frame timeslot is dynamically adjusted by checking the value of (W−R+L)mod L in the next timeslot.
A similar mechanism can be applied in the upstream direction in the case that the buffer unit 42 includes a FIFO buffer. The RC logic unit 44 only instructs the units 34, 35, 36, 37 to commence operation in the case that the buffer unit 44 stores sufficient data, as determined by the positions of the pointer.
Alternatively, as mentioned above, the buffer units 41, 42 may be implemented with ping-pong buffers instead of FIFO buffers. There may be a ping-pong buffer for each of the channels inside each of the buffer units 41, 42. The ping-pong buffer has two sections. In the downstream direction, at any given time one of the sections is being read to generate data to transmit on the corresponding channel, while the other section of the buffer is available to receive data in respect of the next symbol for that channel. In the upstream direction, at any given time one of the sections is receiving data from the corresponding channel, while the other section of the buffer is available to transmit data to be processed. Once a symbol has been fully transmitted/received, the two buffer sections swap roles.
Suppose, for example, that the buffer unit 42 for the upstream (RX) direction is implemented using ping pong buffers. In this case, when the units 34, 35 are about to start processing data in respect of a given channel, the rate converter logic unit 44 checks that there is sufficient data in the ping pong buffers for that channel. If there is insufficient data, the logic unit 44 sends control signals to ensure that data is not copied into the BufDU 52 and the FFT unit 35 is inhibited. Conversely, if there is sufficient data, data is copied from the filled buffer into BufDU 52 and the FFT unit 35 begins work. Note that at any one time, both buffers are not full. Alternatively the ping-pong buffers could also be implemented as FIFO buffers.
In the ADSL standard, the cyclic extension or cyclic suffix/prefix is not transmitted during an initial training period, and the embodiment is able to cope with the consequent data rate adaptation. When a cyclic extension is present, each symbol is processed in exactly one timeslot, as explained above. However, during the initial training period when the cyclic extension is not enabled, the symbol period is equal to the timeslot. Hence, in the TX (downstream) direction, symbols are processed in a every timeslot. Similarly, in the RX-direction, the rate converter checks per timeslot if there is sufficient data in the ping-pong buffer to perform the FFT processing. When there is sufficient data, the data in the ping-pong buffer is copied into BufDU.
Although only a single embodiment of the invention has been described in detail, many variations are possible within the scope of the disclosure as will be clear to a skilled reader.
For example, the units of the embodiment may be differently arranged from the embodiment of
Furthermore, whereas in the embodiment described above the system generates/receives data for/from four channels, other embodiments of the invention may service a number of channels which is different from four.
In a further example, although in the embodiment described above the system performs rate adaptation using idle frames (i.e. periodically stopping processing for a channel which has a symbol rate below the maximum), in alternative arrangements the system may be capable of accelerating the processing when necessary. For example, it may be able in a given timeslot to generate/receive selectively either one or two symbols. In each timeslot, it may dynamically determine how many symbols should be generated/received for each of the channels.
Furthermore, while the description above is in terms of a DMT receiver and/or transmitter, it may be adapted to apply to an OFDM receiver and/or transmitter.
It is therefore intended that the foregoing detailed description be regarded as illustrative rather than limiting, and that it be understood that it is the following claims, including all equivalents, that are intended to define the spirit and scope of this invention.
