Patent Application
20060115275
The present invention relates to fiber optic communication; more particularly, the present invention relates to optical transceivers.
Optical transceivers (or transponders) operating at line rates of ten (10 Gb/s) have developed rapidly over the past few years. These transponders are currently available in a wide variety of form factors, such as Xenpak and X2, which are low cost and scalable. An advantage of choosing a standard form factor transponder is to have the choice of selecting between multiple suppliers. Another advantage is to apply the same line card design to target different applications while hiding the transponder technology difference away from end users.
From a customers' point of view, it is desirable to have one transponder capable of operating for several different applications rather than having to use different transponders for multiple applications. An ideal situation would be to have one transponder work in several close but different line rates. However, conventional transponder designs can operate at only one fixed data rate from one module (e.g., SONET (9.953 Gb/s), 10 G Ethernet (10.3 Gb/s), or 10 G Fiber Channel (10.5 Gb/s), etc.). Such limitation gives costumer less flexibility procuring parts and causes higher inventory costs.
The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention. The drawings, however, should not be taken to limit the invention to the specific embodiments, but are for explanation and understanding only.
According to one embodiment, a multiple rate optical transponder is disclosed. Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
Network processor 110 processes data packets. In particular, processor 110 receives packets from a switch fabric device (not shown), processes the packets and forwards the packets to another network (e.g., an optical network) based upon control information received from control processor 120. Further, processor 110 receives data from an optical network and forwards the data to the switch fabric device. Control processor 120 processes control information, such as control commands.
MAC 130 controls media access of transmitting and receiving packets to and from line card 100. Transponder 150 transmits and receives optical data.
Optical interfaces 202 are coupled to optical fibers, and are implemented to transmit optical data from transponder 150 via the fibers, as well as to receive optical data from the fibers. Transceiver 210 includes a receiver component and a transmitter component used to transmit/receive optical data. The receiver component includes active components that are implemented to receive optical data from one or more optical fibers.
The active components convert a received optical input signal into an electrical signal that is forwarded to MAC 130. The transmitter component receives electrical signals and converts the signals to optical output signals that are transmitted via the optical fibers.
According to one embodiment, transceiver 210 is coupled to electrical interface 230 via a management data interface (MDIO) 205.
Microcontroller 220 is implemented to operate control systems that set control parameters for transceiver 210. In one embodiment, the control parameters may vary over time and temperature. In a further embodiment, microcontroller 220 also provides a two-wire interface 207 (e.g., I2C) so that control parameters can be set and status registers can be read from card 100 where monitor values are stored.
Electrical interface 230 provides I/O data transfer to card 100. In addition, interface 230 provides various clocking channels, control and monitoring channels, as well as DC power and ground connections. According to one embodiment, interface 230 is a seventy (70) pin connector that plugs perpendicularly into the plane of card 100. However, in other embodiments, interface 230 may be implemented as other types of connectors, or can take the form of a board-edge connection that mate to a socket in the plane of the card 100.
Clocks 240 and 250 are clocks that provide the reference clock to transceiver 210 for transmitting and receiving data at transponder 150. According to one embodiment, clocks 240 and 250 enable transponder 150 to operate at two or more data rates while maintaining high optical and electrical output quality at each data rate transponder 150 operates. For instance, clock 240 may provide a first data rate, while clock 250 provides a second data rate.
According to one embodiment, clock 240 operates according to a data rate designed for SONET operation (e.g., 9.953 Gb/s), while clock 250 operates at a data rate implemented in 10 G Ethernet (e.g., 10.3 Gb/s) designs. However, in other embodiments, it is apparent that either clock 240 or 250 may implant other data rates, such as 10.5 Gb/s for 10 G Fiber Channel designs.
In one embodiment, a clock selection line is coupled to both clocks 240 and 250 to transmit a select signal to clocks 240 and 250. The select signal indicates which clock is to provide the data rate for transponder 150. An inverter is coupled to the input of clock 250 to invert the select signal. Thus, when the select signal is a high logic value (e.g., logic 1) clock 250 is de-activated, while clock 240 provides the data rate. Conversely, if the select signal is a low logic value (e.g., logic 0) clock 250 is the active clock, while clock 240 is de-activated.
According to one embodiment, the select signal is generated via hardware. In such an embodiment, the select signal value is selected by controlling the input voltage on a vendor specific pin from electrical interface 230.
According to one embodiment, software control enables an end user to make a temporary choice in data rate. In such an embodiment, the data rate may switch back to the original selection after a power cycle. Note that in other embodiments, that the embodiments of
Whereas many alterations and modifications of the present invention will no doubt become apparent to a person of ordinary skill in the art after having read the foregoing description, it is to be understood that any particular embodiment shown and described by way of illustration is in no way intended to be considered limiting. Therefore, references to details of various embodiments are not intended to limit the scope of the claims which in themselves recite only those features regarded as the invention.
