Dave Bursky, Shrik systems with one-chip decoder, EPROM, and RAM, Jul. 28, 1988, p. 91.* |
Altera 1996 Data Book, “FLEX 10K Embedded Programmable Logic Family,” Jun. 1996, pp. 29-90. |
Altera 1999 Device Data Book, “APEX 20K Programmable Logic Device Family,” May 1999, pp. 23-88. |
“AT&T's Orthogonal ORCA Targets the FPGA Future,” 8029 Electronic Engineering, 64, No. 786, Jun. 1992, pp. 9-10. |
AT&T Microelectronics Data Sheet, “Optimized Reconfigurable Cell Array (ORCA) Series Field-Programmable Gate Arrays,” Mar. 1994, pp. 1-100. |
AT&T Microelectronics Preliminary Data Sheet, “Optimized Reconfigurable Cell Array (ORCA) 2C Series Field-Programmable Gate Arrays,” Apr. 1994,. 1-104. |
Bennett, P.S. et al., “BiMOS Technology in Gate Arrays with Configurable RAM,” Proc. of 7th International Conf. on Custom and Semicustom ICs, Nov. 3-5, 1987, London, U.K., pp. 54/1-7. |
Brinkman, “Evolution of the Logic Cell Array,” Elektronica, vol. 38, No. 17, Sep. 7, 1990, pp. 43-53. |
Britton, et al., “Optimized Reconfigurable Cell Array Architecture for High-Performance Field Programmable Gate Arrays,” in IEEE 1993 Custom Integrated Circuits Conference. |
Brown, S. et al., “FPGA and CPLD Architectures: A Tutorial,” IEEE Design & Test of Computers, vol. 13, No. 2, Jun. 1, 1996, pp. 42-57. |
Bursky, Dave, “Shrink Systems with One-Chip Decoder, EPROM, and RAM,” Electronic Design, Jul. 28,1988, pp. 91-94. |
Bursky, “Combination RAM/PLD Opens New Application Options,” Electronic Design, May 23, 1991, pp. 138-140. |
Bursky, Dave, “FPGA Advances Cut Delays, Add Flexibility,” 2328 Electronic Design, 40, No. 20, Oct. 1, 1992, pp. 35-43. |
Bursky, Dave, “Denser, Faster FPGAs Vie for Gate-Array Applications,” 2328 Electronic Design, 41, No. 11, May 27, 1993, pp. 55-75. |
Casselman, “Virtual Computing and The Virtual Computer,” IEEE, Jul. 1993, p. 43. |
Cliff, et al., “A Dual Granularity and Globally Interconnected Architecture for a Programmable Logic Device,” in IEEE 1993 Custom Integrated Circuits Conference. pp. 3.1-3.5. |
Conner, “PLD Architectures Require Scrutiny,” in Electrical Digest News, Sep. 29, 1989. |
Furtek, Frederick et al. “Labyrinth: A Homogenous Computational Medium,” in IEEE 1990 Custom Integrated Circuits Conference: 31.1.1-31.1.4. |
Hallau, “More Than Mere Gate Logic,” in Electronik, vol. 40, No. 15, Jul. 23, 1991, pp. 95-99. |
Hsieh et al., “Third Generation Architecture Boosts Speed and Density of Field Programmable Gate Arrays,” Proc. of IEEE CICC Conf., May 1990, pp. 31.2.1 to 31.2.7. |
Intel Preliminary Datasheet, “iFX780: 10ns FLEXlogic FPGA with SRAM Option,” Nov. 1993, pp. 2-24 to 2-46. |
Kautz, “Cellular Logic in Memory Arrays,” IEEE Trans. on Computers, vol. C-18, No. 8, Aug. 1969, pp. 719-727. |
Kawana, Keiichi et al., “An Efficient Logic Block Interconnect Architecture for User-Reprogrammable Gate Array,” IEEE 1990 Custom Integrated Circuits Conf., May 1990, CH2860-5/90/0000-0164, pp. 31.3.1 to 31.3.4. |
Landry, Steve, “Application -Specific ICs, Relying on RAM, Implement Almost Any Logic Function,” Electronic Design, Oct. 31, 1985, pp. 123-130. |
Larsson, T, “Programmable Logic Circuits: The Luxury Alternatives are Coming Soon,” Elteknik-med-Aktuell Electronik, No. 4, Feb. 25-Mar. 9, 1988, pp. 37-38, (with English abstract). |
Ling, X.-P. and H. Amano, “WASMII: A Data Driven Computer on a Virtual Hardware,” Proc. of IEEE Field Prog. Custom Computing Machines Conf., Napa, California, Apr. 1993, pp. 33-42. |
Manning, Frank B. “An Approach to Highly Integrated Computer Maintained Cellular Arrays,” IEEE Trans. on Computers, vol. C-26, No. 6, Jun. 1977, pp. 536-552. |
Marple, “An MPGA Compatible FPGA Architecture,” in IEEE 1992 Custom Integrated Circuits Conference. |
Masumoto, Rodney T., “Configurable On-Chip RAM Incorporated into High Speed Logic Array,” IEEE Custom Integrated Circuits Conference, Jun. 1985, CH2157-6/85/0000-0240, pp. 240-243. |
Miyahara, et al., “A Composite CMOS Gate Array with 4K RAM and 128K ROM,” in Proceeding of the IEEE 1985 Custom Integrated Circuits Conference, pp. 248-251. |
Nelson, Rick, “Embedded Memory Enhances Programmable Logic for Complex, Compact Designs,” EDN Electrical Design News, vol. 41, No. 23, Nov. 7, 1996, pp. 91-106. |
New IEEE Standard Dictionary of Electrical and Electronics Terms, 5th Edition, Jan. 15, 1993, p. 974. |
Ngai, Kai-Kit Tony, “Field-Reconfigurable Memory (FRM),” Slide Presentation at University of Toronto, Canada, Jun. 1993, Slide Nos. 1-14. |
Ngai, Kai-Kit Tony, “An SRAM-Programmable Field-Reconfigurable Memory,” Manuscript Thesis, The University of Toronto Library, Aug. 18, 1994, pp. 1-68. |
Patil, Suhas S. et al., “A Programmable Logic Approach for VLSI,” IEEE Trans. on Computers, vol. C-28, No. 9, Sep. 1979, pp. 594-601. |
Plus Logic “FPSL5110 Intelligent Data Buffer” Product Brief, Plus Logic, Inc., San Jose, California, Oct. 1990, pp. 1-6. |
Prince, et al., Semiconductor Memories, 2nd Ed., 1991, pp. 149-151, 157-160, and 371-375. |
Quenot et al., “A Reconfigurable Compute Engine for Real-Time Vision Automata Prototyping,” Proc. of IEEE FCCM Conf., Napa, California, Feb. 1994, pp. 91-100. |
Quinnell, Richard A., “FPGA Family Offers Speed, Density, On-Chip RAM, and Wide-Decode Logic,” EDN Dec. 6, 1990, pp. 62-64. |
Ramatschi, “Field-Programmable Integrated Circuits,” in Elecktronik Praxis, vol. 25, No. 19, Oct. 4, 1990, pp. 52-59. |
Reddy, S. et al., “A High Density Embedded Array Programmable Logic Architecture,” Proc. of the IEEE 1996 Custom Integrated Circuits Conf. (CICC), San Diego, California, May 5-8, 1996, pp. 251-254. |
Sano, et al., “A 20ns CMOS Functional Gate Array with a Configurable Memory,” in Proceedings of the 1983 IEEE International Solid State Circuits Conference. |
Satoh, Hisayasu et al., “A 209K-Transistor ECL Gate Array with RAM,” IEEE Jor. of Solid State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1275-1279. |
Seitz, “Concurrent VLSI Architectures,” IEEE Trans. on Computers, vol. C-33, No. 12, Dec. 1984, pp. 1247-1265. |
Shubat, Alexander et al., “A Family of User-Programmable Peripherals with a Functional Unit Architecture,” IEEE J. of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, pp. 515-529. |
Smith, Daniel, “Intel's FLEXlogic FPGA Architecture,” IEEE 1063-6390/93, 1993 pp. 378-384. |
Spandorfer, “Synthesis of Logic Functions on Array of Integrated Circuits,” Final Report prepared for Air Force Cambridge Research Laboratories, Office of Aerospace Research, United States Air Force, 1965. |
Stone, Harold S. “A Logic in Memory Computer,” IEEE Trans. on Computers, Jan. 1970, pp. 73-78. |
Sugo, et al., “An ECL 2.8ns 16K RAM with 1.2K Logic Gate Array,” IEEE International Solid-State Circuits Conference, Feb. 21, 1986, pp. 256-257. |
Takechi, et al., “A CMOS 12K-Gate Array with Flexible 10Kb Memory,” in Proceedings of the 1984 IEEE International Solid-State Circuits Conference, p. 258. |
Weiss, “FPGA Targets Dynamically Reloadable Logic,” in Electrical Digest News, Mar. 17, 1994. |
Weiss, “Intel CPLD Combines Flash Memory, SRAM-Based Logic,” in Electrical Digest News, Apr. 28, 1994. |
Xilinx, Corporation Data Sheet, “Virtex™ 2.5 V Field Programmable Gates Arrays,” Jan. 28, 2000, pp. 1-72. |
Xilinx Inc., “The Programmable Logic Data Book,” 1993. |
Xilinx Inc., “The Programmable Logic Data Book,” 1994, pp. 2-5 to 2-102. |