Multiple VDD clock buffer

Abstract

A clock buffer circuit can include a low voltage drive circuit that receives a clock signal and provides a low voltage drive at a first power supply potential to a load. A boost drive circuit can provide a high voltage drive at a second power supply potential greater than the first power supply potential to the load. The boost drive circuit can provide the high voltage drive in response to a pulse signal generated in response to a transition of a clock input signal. A pulse generator circuit may generate the pulse signal to have a predetermined width to enable the high voltage drive until the load is charged essentially to the first power supply potential.

Description

TECHNICAL FIELD

The present invention relates generally to clock buffers, and more particularly to clock buffer circuits operating at low voltages.

BACKGROUND OF THE INVENTION

Many semiconductor devices operate using a clock signal. This clock signal must be distributed throughout the device with as little skew as possible. One way to reduce skew is through a clock tree.

Referring now to FIG. 1, a conventional clock tree is set forth in a schematic diagram and designated by the general reference character 100. Clock tree 100 has a clock input at beginning point 140. The clock signal may be buffered by buffer circuits 110 at each T-junction 120 before being provided to circuitry at the tree ends 150. To avoid unduly cluttering the figure, buffer circuits 110 are only shown at various T-junctions 120 to illustrate a complete propagation path of a clock signal to an endpoint 150. However, it is understood that buffer circuits 110 are provided on each side of a T-junction 120. Clock tree 100 is designed such that the propagation path of a clock signal from beginning point 140 to each endpoint 150 are essentially matching. Furthermore, the delay of each buffer circuit 110 must be small to minimize the clock insertion delay from beginning point 140 to each endpoint 150.

Each buffer circuit 110 can essentially be a pair of inverters. Referring now to FIG. 2, a conventional buffer circuit is set forth in a circuit schematic diagram and designated by the general reference character 200. Conventional buffer circuit may receive a clock signal CLKIN at terminal 210 and may provide a clock signal CLKOUT at terminal 220. Buffer circuit 200 may be used as buffer circuit 110 in clock tree 100 of FIG. 1.

Buffer circuit 200 may include inverters (INV202 and INV204). Load network L202 is shown to essentially model the load of the conductive branches in the tree network of FIG. 1.

Inverter INV202 receives clock signal CLKIN at input terminal 210 and provides an output at node N212. Inverter INV204 has an input connected to node N212 and provides an output at node N214. Load L202 is connected between node N214 and output terminal 220. Input terminal 210 can be a T-junction 120 in clock tree 100 of FIG. 1 where a buffer circuit 110 and output terminal 220 can be a subsequent T-junction 120 where the next buffer circuit 110 is located.

Inverter INV202 is a complementary metal oxide semiconductor (CMOS) inverter including an n-channel metal oxide semiconductor field effect transistor (MOSFET) N202 and p-channel MOSFET P202. N-channel MOSFET N202 has a gate terminal connected to input terminal 210, a source terminal connected to ground VSS, a drain terminal connected to node N212, and a body terminal connected to receive a back bias potential Vbn. P-channel MOSFET P202 has a gate terminal connected to input terminal 210, a source terminal connected to a power supply potential VDD, a drain terminal connected to node N212, and a body terminal connected to receive a back bias potential Vbp.

Inverter INV204 is a CMOS inverter including an n-channel MOSFET N204 and p-channel MOSFET P204. N-channel MOSFET N204 has a gate terminal connected to node N212, a source terminal connected to ground VSS, a drain terminal connected to node N214, and a body terminal connected to receive a back bias potential Vbn. P-channel MOSFET P204 has a gate terminal connected to node N212, a source terminal connected to a power supply potential VDD, a drain terminal connected to node N214, and a body terminal connected to receive a back bias potential Vbp.

Load L202 includes resistors (R202, R204, and R206) and capacitors (C202 and C204). Resistor R202 has a first terminal connected to node N212 and a second terminal commonly connected to a first terminal of resistor R204 and a second terminal of capacitor C202. Resistor R204 has a second terminal commonly connected to a first terminal of resistor R206 and a second terminal of capacitor C204. Resistor R206 has a second terminal connected to output terminal 220. Capacitors (C202 and C204) each have a first terminal connected to ground potential VSS.

A drawback to the conventional buffer circuit 200 is that as voltages decrease, for example, from 1 volt to 0.6 volt, the propagation delay of the clock signal can increase by a factor of 3.

Referring now to FIG. 6, a waveform diagram of simulation results is set forth. The waveform diagram of FIG. 6 illustrates the conventional buffer circuits as well as an embodiment of the present invention. In the waveform diagram of FIG. 6, signal 614 represents the clock signal CLKOUT for three series connected conventional buffer circuits 200 operating at 1.0 volts and signal 618 represents the clock signal CLKOUT for three series connected conventional buffer circuits 200 operating at 0.6 volts. As illustrated in FIG. 6, at midpoints (i.e. the trip points of a hypothetical following stage) in transitions of signal 614 and signal 618, conventional buffer circuit 200 is about 3 times slower at 0.6 volts as compared to 1.0 volts.

In view of the above, it would be desirable to provide a buffer circuit that can provide a lower signal swing voltage without substantial propagation delays. In this way, power may be reduced without the penalty of substantial propagation delays.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a conventional clock tree.

FIG. 2 is a schematic diagram of a conventional buffer circuit.

FIG. 3 is a schematic diagram of a buffer circuit according to a first embodiment.

FIG. 4 is a waveform diagram of simulation results.

FIG. 5 is a waveform diagram of simulation results.

FIG. 6 is a waveform diagram of simulation results.

FIG. 7 is a waveform diagram of simulation results.

FIG. 8 is a schematic diagram of a buffer circuit according to an embodiment.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show clock buffer circuits and methods constructed with insulated gate field effect transistors (IGFETs), for example IGFETs of complementary conductivity types (n-channel and p-channel types). In particular, the embodiments may include implementations using IGFETs having substantially lower absolute value of threshold voltage V_T, e.g. about 0.4 volts for n-channel IGFETs and about −0.4 volts for p-channel IGFETs as compared to about 0.6 volts and −0.6 volts, respectively. Such low threshold voltage IGFETs may comprise DDC technology, as but one example. DDC transistors are particularly advantageous for the embodiments herein based on the ability to reliably set threshold voltage with substantially reduced variation compared with conventional planar CMOS transistors. DDC transistors are also amenable to be designed with reduced threshold voltage, based upon, among other device design attributes, there being a heavily doped region and structure below a substantially undoped channel. Further discussion regarding transistor structure and methods of implementation is provided in U.S. Pat. No. 8,273,617 entitled ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME, which disclosure is incorporated by reference herein in its entirety.

Referring now to FIG. 3, a buffer circuit according to a first embodiment is shown in a schematic diagram, and designated by the general reference character 300. Buffer circuit 300 may receive a clock signal CLKIN at input terminal 310 and may provide a clock signal CLKOUT at output terminal 320. Buffer circuit 300 may be used as buffer circuit 110 in clock tree 100 of FIG. 1.

Buffer circuit 300 may include a low voltage drive circuit 330, a pulse generator circuit 340, and a boost drive circuit 350. Load network L302 is shown to essentially model the load of the conductive branches in the tree network of FIG. 1.

Low voltage drive circuit 330 receives clock signal CLKIN at input terminal 310 and provides an output at node N30. Pulse generator circuit 340 may receive clock signal CLKIN at input terminal 310 and may provide an output at node N32. Boost drive circuit 350 may receive the output of pulse generator circuit 340 at node N32 and may provide an output at node N30. Load L302 is connected between node N32 and output terminal 320. Input terminal 310 can be a T-junction 120 in clock tree 100 of FIG. 1 where a buffer circuit 110 and output terminal 320 can be a subsequent T-junction 120 where the next buffer circuit 110 is located, as but one example.

Low voltage drive circuit 330 may include logic gates (G332 and G334). Logic gate G332 may receive clock signal CLKIN at input terminal 310 and may provide an output to an input of logic gate G334. Logic gate G334 may provide an output to node N30. Logic gates (G332 and G334) may be inverters, as just one example.

Logic gate G332 can include an n-channel IGFET N332 and a p-channel IGFET P332. N-channel IGFET N332 may have a gate terminal commonly connected to a gate terminal of p-channel IGFET P332 to receive clock signal CLKIN. N-channel IGFET N332 may have a source terminal connected to a ground potential Vss and a drain terminal commonly connected to a drain terminal of p-channel IGFET P332 to provide an output. N-channel IGFET N332 may have a body terminal connected to a back bias potential Vbn. P-channel IGFET P332 may have a source connected to a first power supply potential VDD1. P-channel IGFET P332 may have a body terminal connected to a back bias potential Vbp.

Logic gate G334 can include an n-channel IGFET N334 and a p-channel IGFET P334. N-channel IGFET N334 may have a gate terminal commonly connected to a gate terminal of p-channel IGFET P334 to receive the output provide by commonly connected drain terminals of p-channel IGFET P332 and n-channel IGFET N332 of logic gate G332. N-channel IGFET N334 may have a source terminal connected to a ground potential Vss and a drain terminal commonly connected to a drain terminal of p-channel IGFET P334 to provide an output at node N32. N-channel IGFET N334 may have a body terminal connected to a back bias potential Vbn. P-channel IGFET P334 may have a source connected to a first power supply potential VDD1. P-channel IGFET P334 may have a body terminal connected to a back bias potential Vbp.

Pulse generator circuit 340 can include logic gates (G342, G344, G346, and G348). Logic gate G342 can receive clock signal CLKIN at input terminal 310 as an input and may provide an output. Logic gate G344 may receive the output from logic gate G342 as an input and provides an output. Logic gate G346 may receive the output from logic gate G344 and provides an output. Logic gate G348 receives clock signal CLKIN at input terminal 310 and the output from logic gate G346 as inputs and provides an output to node N32. Logic gates (G342, G344, and G346) may be inverters and logic gate G348 may be a NAND gate, as particular examples.

Logic gate G342 can include an n-channel IGFET N342 and a p-channel IGFET P342. N-channel IGFET N342 may have a gate terminal commonly connected to a gate terminal of p-channel IGFET P342 to receive clock signal CLKIN. N-channel IGFET N342 may have a source terminal connected to a ground potential Vss and a drain terminal commonly connected to a drain terminal of p-channel IGFET P342 to provide an output. N-channel IGFET N342 may have a body terminal connected to a back bias potential Vbn. P-channel IGFET P342 may have a source connected to a first power supply potential VDD1. P-channel IGFET P342 may have a body terminal connected to a back bias potential Vbp.

Logic gate G344 can include an n-channel IGFET N344 and a p-channel IGFET P344. N-channel IGFET N344 may have a gate terminal commonly connected to a gate terminal of p-channel IGFET P344 to receive the output provide by commonly connected drain terminals of p-channel IGFET P342 and n-channel IGFET N342 of logic gate G342. N-channel IGFET N344 may have a source terminal connected to a ground potential Vss and a drain terminal commonly connected to a drain terminal of p-channel IGFET P344 to provide an output. N-channel IGFET N344 may have a body terminal connected to a back bias potential Vbn. P-channel IGFET P344 may have a source connected to a second power supply potential VDD2. P-channel IGFET P344 may have a body terminal connected to a back bias potential Vbp.

Logic gate G346 can include an n-channel IGFET N346 and a p-channel IGFET P346. N-channel IGFET N346 may have a gate terminal commonly connected to a gate terminal of p-channel IGFET P346 to receive the output provide by commonly connected drain terminals of p-channel IGFET P344 and n-channel IGFET N344 of logic gate G344. N-channel IGFET N346 may have a source terminal connected to a ground potential Vss and a drain terminal commonly connected to a drain terminal of p-channel IGFET P346 to provide an output. N-channel IGFET N346 may have a body terminal connected to a back bias potential Vbn. P-channel IGFET P346 may have a source connected to a second power supply potential VDD2. P-channel IGFET P346 may have a body terminal connected to a back bias potential Vbp.

Logic gate G348 can include n-channel IGFETs (N348 and N349) and p-channel IGFETs (P348 and P349). N-channel IGFET N348 may have a gate terminal commonly connected to a gate terminal of p-channel IGFET P348 to receive the output provided by commonly connected drain terminals of p-channel IGFET P346 and n-channel IGFET N346 of logic gate G346. N-channel IGFET N348 may have a source terminal connected to a ground potential Vss and a drain terminal commonly connected to a source terminal of n-channel IGFET N349. N-channel IGFET N349 may have a gate terminal commonly connected to a gate terminal of p-channel IGFET P349 to receive clock signal CLKIN from input terminal 310. N-channel IGFET N349 may have a drain terminal commonly connected to the source terminals of P-channel IGFETs (P348 and P349) to provide an output signal to node N32. The output signal provided at node N32 may be a pulse output signal. P-channel IGFETs (P348 and P349) may each have a source terminal connected to a third power supply potential VDD3. N-channel IGFETs (N348 and N349) may each have a body terminal connected to a back bias potential Vbn. P-channel IGFETs (P348 and P349) may each have a body terminal connected to a back bias potential Vbp.

Boost drive circuit 350 can include a p-channel IGFET P350. P-channel IGFET P350 can have a source terminal connected to third power supply potential VDD3, a gate connected to receive the pulse output signal from pulse generator circuit 340 on node N32. P-channel IGFET P350 may have a drain terminal connected to provide an output at node N30. P-channel IGFET P350 may have a body terminal connected to a back bias potential Vbp.

Load network L302 includes resistors (R302, R304, and R306) and capacitors (C302 and C304). Resistor R302 has a first terminal connected to node N30 and a second terminal commonly connected to a first terminal of resistor R304 and a second terminal of capacitor C302. Resistor R304 has a second terminal commonly connected to a first terminal of resistor R306 and a second terminal of capacitor C304. Resistor R306 has a second terminal connected to output terminal 320. Capacitors (C302 and C304) each have a first terminal connected to ground potential VSS.

First power supply potential VDD1 may be about 0.6 volts, second power supply potential VDD2 may be about 0.8 volts, and third power supply potential VDD3 may be about 1.0 volts.

The operation of buffer circuit 330 will now be explained. The operation will be described through one full cycle of clock signal CLKIN beginning with clock signal CLKIN at a low logic level.

Initially, clock signal CLKIN may be at a low logic level. Logic gate G332 in low voltage drive circuit 330 can receive the low logic level and provide a high logic level (at a first power supply potential VDD1) to the input of logic gate G334. With the input of logic gate G334 at a high logic level, logic gate G334 may provide a low logic level to node N32. This low logic level will propagate through load network L302 to provide a clock signal CLKOUT at a low logic level. Also at this time, pulse generator circuit 340 receives the clock signal CLKIN as inputs to logic gates (G342 and G348). Under this condition, the output of logic gate G342 is a high logic level. With the output of logic gate G342 at a high logic level (at a first power supply potential VDD1), the output of logic gate G344 is a low logic level and the output of logic gate G346 is a high logic level. With the output of logic gate G346 at a high logic level, N-channel IGFET N348 in logic gate G348 is turned on and P-channel IGFET P348 is turned off. Also, at this time, with clock signal CLKIN at a low logic level, p-channel IGFET P349 can be turned on and n-channel IGFET N349 is turned off. With P-channel IGFET P349 turned on, pulse generator circuit 340 provides a logic high signal to node N32. With node N32 at a logic high level (at a third power supply potential VDD3), p-channel IGFET P350 in boost drive circuit 350 is turned off.

Next, as clock signal CLKIN transitions from a low logic level to a high logic level, logic gate G332 can provide an output that transitions from a high logic level to a low logic level. At this time, n-channel IGFET N334 in logic gate G334 of low voltage drive circuit 330 can turn off and n-channel IGFET P334 may turn on. In this way, node N30 may be electrically connected to first power supply potential VDD1 and may begin to rise. It is noted that load network L302 may prevent node N30 and subsequently clock signal CLKOUT from instantaneously rising to a high logic level. However, also at this time, logic gate 348 receives the low to high logic level transitioning clock signal CLKIN. As clock signal transitions from the low to high logic levels, p-channel IGFET P349 turns off and n-channel IGFET N349 turns on in logic gate 348. As noted earlier, at this time n-channel IGFET N348 is turned on. With n-channel IGFETs (N348 and N349) turned on, node N32 transitions from a logic high level to a logic low level. In this way, p-channel IGFET P350 in boost drive circuit 350 turns on and provides low impedance path from node N30 to third power supply potential VDD3.

With third power supply potential VDD3 at a potential (1 volt), the clock line modeled by load network L302 can be driven to a desired potential (in this case about 0.6 volts) via a boost drive circuit 350 operating at a higher potential and the transition time of clock signal CLKOUT may be greatly decreased.

Also, at this time, the low to high transitioning clock signal CLKIN can propagate through logic gates (G342, G344, and G346) of pulse generating circuit 340. As clock signal CLKIN transitions to a high logic level, the output of logic gate G342 transitions to a low logic level. With the output of logic gate G342 at a low logic level, the output of logic gate G344 transitions to a high logic level (second supply potential VDD2). With the output of logic gate G344 at a high logic level, the output of logic gate G346 transitions to a low logic level. It is noted that the propagation time of a clock signal CLKIN through logic gates (G342, G344, and G346) can be set to a predetermined time. Thus, after this predetermined time after clock signal CLKIN transitions to a high logic level, logic gate G348 in pulse generator circuit 340 receives the low logic level from logic gate G346. Upon receiving the low logic level from logic gate G348, n-channel IGFET N348 turns off and p-channel IGFET P348 turns on. With p-channel IGFET P348 turned on, node N32 transitions back to a high logic level (third supply potential VDD3). With node N32 at a high logic level, p-channel IGFET P350 in boost drive circuit 350 turns off thereby providing a high impedance path between load L302 and third power supply potential VDD3.

It is noted that it may be preferable to set the predetermined propagation time for the clock signal CLKIN to propagate through logic gates (G342, G344, and G346) to provide a pulse width for the output pulse provided on node N32 by pulse generating circuit to a time sufficient to allow boost drive circuit 350 to provide the low impedance path to third power supply potential VDD3 to essentially provide a high logic level of about 0.6 volts to clock signal CLKOUT without substantially overshooting the desired high logic level of about 0.6 volts. In this way, clock signal transition time may be minimized without unduly wasting charge.

After p-channel IGFET P350 in boost drive circuit 350 is turned off, p-channel IGFET P334 in logic gate G334 of low voltage drive circuit 330 can remain on to provide a low impedance path between load L302 and first power supply potential VDD1. In this way, low voltage drive circuit may correct any overshoot or undershoot of the desired high logic potential of about 0.6 volts and act as a low current keeper of the desired about 0.6 volts.

After a time, clock signal CLKIN can transition from the high logic level to a low logic level. In response to the high to low logic level transition of clock signal CLKIN, the output of logic gate G332 of low voltage drive circuit 330 transitions from a low logic level to a high logic level (first power supply potential VDD1). In response to the low to high logic level transition of the output of logic gate G332, n-channel IGFET N334 of logic gate G334 turns on and p-channel IGFET P334 turns off. In this way, a low impedance path is provided from the load L302 to ground potential Vss through n-channel IGFET N334 and clock signal CLKOUT may be driven back to a low logic level.

Also at this time, in response to clock signal CLKIN transitioning from the high logic level to a low logic level, p-channel IGFET P349 in logic gate G348 in pulse generator circuit 340 turns on and n-channel IGFET N349 turns off. In this way, the high logic level (third power supply potential VDD3) is maintained on node N32. A short time later, the clock signal CLKIN propagates through the logic gates (G342, G344, and G346) and the output of logic gate G346 transitions from a low logic level to a high logic level (third power supply potential VDD3). At this time n-channel IGFET N348 turns back on and p-channel IGFET 348 turns back off to return to the original conditions and one full clock cycle has occurred.

The pulse generated on node N32 can have a first edge and a second edge. The boost drive circuit may provide a low impedance path between the third power supply potential VDD3 and node N30 in response to the first edge and may provide a high impedance path between the third power supply potential VDD3 and node N30 in response to the second edge.

The commonly connected gates of p-channel IGFET P332 and n-channel IGFET N332 in low voltage drive circuit 330 may be a low voltage drive circuit input terminal. The commonly connected gates of p-channel IGFET P342 and n-channel IGFET N342 in pulse generator circuit 340 may be a pulse generator circuit input terminal. The gate of p-channel IGFET P350 in boost drive circuit 350 may be a boost drive circuit input terminal.

Referring now to FIG. 4, a waveform diagram of simulation results is set forth. The waveform diagram of FIG. 4 illustrates simulation results of three buffer circuits 300 connected in series, as well as simulation results of three conventional buffer circuits 200 connected in series having a power supply potential VCC of 0.6 volt.

Waveform 402 represents clock signal CLKOUT after a first stage of buffer circuit 300, waveform 404 represents clock signal CLKOUT after a second stage of buffer circuit 300, and waveform 406 represents clock signal CLKOUT after a third stage of buffer circuit 300. Waveform 408 represents clock signal CLKOUT after a first stage of conventional buffer circuit 200, waveform 410 represents clock signal CLKOUT after a second stage of conventional buffer circuit 200, and waveform 412 represents clock signal CLKOUT after a third stage of conventional buffer circuit 200.

As illustrated in FIG. 4, at midpoints (i.e. the trip points of a following stage) in transitions of waveform 406 and waveform 412, buffer circuit 300 is about 3 times faster than conventional buffer circuit 200.

Referring now to FIG. 5, a waveform diagram of simulation results is set forth. The waveform diagram of FIG. 5 illustrates simulation results of three buffer circuits 300 connected in series, as well as simulation results of three conventional buffer circuits 200 connected in series having a power supply potential VCC of 1.0 volt.

Waveform 502 represents clock signal CLKOUT after a first stage of buffer circuit 300, waveform 504 represents clock signal CLKOUT after a second stage of buffer circuit 300, and waveform 506 represents clock signal CLKOUT after a third stage of buffer circuit 300. Waveform 508 represents clock signal CLKOUT after a first stage of conventional buffer circuit 200, waveform 510 represents clock signal CLKOUT after a second stage of conventional buffer circuit 200, and waveform 512 represents clock signal CLKOUT after a third stage of conventional buffer circuit 200.

As illustrated in FIG. 5, at midpoints (i.e. the trip points of a following stage) in transitions of waveform 506 and waveform 512, buffer circuit 300 is about ten percent faster than conventional buffer circuit 200.

Referring now to FIG. 6, a waveform diagram of simulation results is set forth. The waveform diagram of FIG. 6 illustrates simulation results of three buffer circuits 300 connected in series, as well as simulation results of three conventional buffer circuits 200 connected in series having a power supply potential VCC of 0.6 volt, and simulation results of three conventional buffer circuits 200 connected in series having a power supply potential VCC of 0.6 volt.

Waveform 602 represents clock signal CLKOUT after a first stage of buffer circuit 300, waveform 604 represents clock signal CLKOUT after a second stage of buffer circuit 300, and waveform 606 represents clock signal CLKOUT after a third stage of buffer circuit 300. Waveform 608 represents clock signal CLKOUT after a first stage of conventional buffer circuit 200 operating at a power supply potential VCC of 1.0 volt, waveform 610 represents clock signal CLKOUT after a second stage of conventional buffer circuit 200 operating at a power supply potential VCC of 1.0 volt, and waveform 612 represents clock signal CLKOUT after a third stage of conventional buffer circuit 200 operating at a power supply potential VCC of 1.0 volt. Waveform 614 represents clock signal CLKOUT after a first stage of conventional buffer circuit 200 operating at a power supply potential VCC of 0.6 volt, waveform 616 represents clock signal CLKOUT after a second stage of conventional buffer circuit 200 operating at a power supply potential VCC of 0.6 volt, and waveform 618 represents clock signal CLKOUT after a third stage of conventional buffer circuit 200 operating at a power supply potential VCC of 0.6 volt.

Referring now to FIG. 7, a waveform diagram of simulation results is set forth. The waveform diagram of FIG. 7 illustrates simulation results buffer circuit 300 of FIG. 3.

Waveform 702 represents clock signal CLKIN. Waveform 704 represents the pulse generated at node N32. Waveform 706 represents the output signal at node N30 at the input to load L302. Waveform 708 represents the output signal at the commonly connected node of resistors (R302 and R304) and capacitor C302 in load L302. Waveform 710 represents clock signal CLKOUT.

As illustrated in FIG. 7, an overshoot may occur at node N30 (waveform 706), however, charge sharing across the load L302 may attenuate the signal to produce a clock signal CLKIN at about 0.6 volt, which is the target.

Also, as illustrated in FIG. 7, the negative pulse generated at node N32 (waveform 704) transitions from 1 volt to 0 volt (i.e. ground potential) and thus provides a ground potential VSS to a gate terminal of p-channel IGFET P350 which has a source terminal connected to the third supply potential (about 1.0 volt). In this way, boost drive circuit 350 provides a greater current drive to achieve the huge speed improvement as compared to the conventional buffer circuit 200 operating at 0.6 volt.

The pulse width at node N32 (waveform 704) may be designed to provide a predetermined pulse width such that clock signal CLKOUT may be provided having a magnitude of about 0.6 volt. This may be achieved by designing gates (G342, G344, and G346) to provide a predetermined propagation delay. Gates (G342, G344, and G346) may be conceptualized as a delay stage providing a predetermined delay.

Referring now to FIG. 8, a buffer circuit according to another embodiment is shown in a schematic diagram, and designated by the general reference character 800. Buffer circuit 800 may be used as buffer circuit 110 in clock tree 100 of FIG. 1.

Buffer circuit 800 may include essentially the same constituents as buffer circuit 300 of FIG. 3. Buffer circuit 800 may differ from buffer circuit 300 in that low voltage drive circuit 330 may receive the output provided by gate G344 in pulse generator circuit 340 at node N802 as an input instead of clock signal CLKIN. In this way, p-channel IGFET P334 may be delayed in turning on and a current path between the boost drive circuit 350 and low voltage drive circuit 330 may be reduced or eliminated. Conceptually, in buffer circuit 800, low drive circuit 330 may receive a delayed clock signal as an input at node N802. Delayed clock signal may be provided by delaying clock signal CLKIN with a first predetermined propagation delay of gates (G342 and G344) in pulse generator circuit 340. The pulse width of pulse signal at node N32 may be determined by a second predetermined propagation delay of gates (G342, G444, and G346).

Node N802 can be conceptualized as a low voltage drive circuit input terminal and gates (G342 and G344) can be conceptualized as a delay circuit that provides a delayed clock signal to the low voltage drive circuit input terminal (node N802).

The appearance of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The term “to couple” or “electrically connect” as used herein may include both to directly and to indirectly connect through one or more intervening components. While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art. Accordingly, the specifications and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A buffer circuit, comprising: a low voltage drive circuit operating at a first supply potential, the low voltage drive circuit coupled to receive a clock input signal at a low voltage drive circuit input terminal and directly connected to provide a clock output signal at an output node; anda boost drive circuit operating at a second supply potential greater than the first supply potential, the boost drive circuit coupled to receive a pulse signal and provide a low impedance path between the second supply potential and the output node in response to the pulse signal to drive the output node.

2. The buffer circuit of claim 1, wherein the boost drive circuit includes a first p-channel insulated gate field effect transistor (IGFET) having a source terminal coupled to the second power supply potential, a drain terminal coupled to the output node, and a gate terminal coupled to receive the pulse signal, the IGFET further including a heavily doped region and structure below a substantially undoped channel and the first supply potential is less than or equal to about 0.6 volt.

3. The buffer circuit of claim 2, further including: a pulse generator circuit coupled to receive the clock input signal and provide the pulse signal.

4. The buffer circuit of claim 3, wherein: the pulse signal has a predetermined pulse width having a first edge that enables the boost drive circuit to provide the low impedance path and a second edge that disables the low impedance path when a load coupled to the output node is charged to about the first supply potential.

5. The buffer circuit of claim 3, wherein: the pulse generator circuit provides a propagation delay path for the clock input signal, the propagation delay path essentially sets the predetermined pulse width.

6. The buffer circuit of claim 5, wherein: the propagation delay path includes first, second, and third logic gates coupled in series, the first logic gate operates at the first supply potential, the third logic gate operates at the second supply potential, and the second logic gate operates at a third supply potential, the third supply potential has a potential between the first supply potential and the second supply potential.

7. The buffer circuit of claim 3, wherein: the pulse generator circuit includes a delay circuit coupled between the clock input signal and the low voltage drive circuit input terminal, the delay circuit is coupled to receive the clock input signal and provide a delayed clock signal to the low voltage drive input terminal.

8. The buffer circuit of claim 1, wherein: the pulse signal has a first logic level at essentially the second supply potential and a second logic level at essentially a ground potential, the boost drive circuit provides the low impedance path between the second supply potential and the output node in response to the pulse signal being at the second logic level and provides a high impedance path between the second supply potential and the output node in response to the pulse signal being at the first logic level.

9. A buffer circuit, comprising: a low voltage drive circuit operating at a first supply potential, the low voltage drive circuit coupled to receive an input signal at a low voltage drive circuit input terminal and directly connected to provide an output signal at an output node;a boost drive circuit operating at a second supply potential greater than the first supply potential, the boost drive circuit coupled to receive a pulse signal at a boost drive circuit input terminal and provide a low impedance path between the second supply potential and the output node in response to the pulse signal to drive the output node; anda pulse generator circuit coupled to receive the input signal at a pulse generator circuit input terminal and provide the pulse signal.

10. The buffer circuit of claim 9, wherein: the boost drive circuit includes a first p-channel insulated gate field effect transistor (IGFET) having a source terminal coupled to the second power supply potential, a drain terminal coupled to the output node, and a gate terminal coupled to the boost drive circuit input terminal, wherein the IGFET is comprised of a transistor having a substantially undoped channel with a heavily doped region a distance below the surface, the heavily doped region being of a dopant level sufficient to set the depletion width for the IGFET when a voltage is applied to the gate and the first supply potential is less than or equal to about 0.6 volt.

11. The buffer circuit of claim 9, wherein: the input signal is a clock signal.

12. The buffer circuit of claim 9, wherein: the low voltage drive circuit includes a first low voltage drive circuit logic gate having an input coupled to the low voltage drive circuit input terminal; anda second low voltage drive circuit logic gate having an input coupled to receive an output from the first low voltage drive circuit logic gate, the second low voltage drive circuit logic gate has an output coupled to the output node.

13. The buffer circuit of claim 12, wherein: the first and second low voltage drive circuit logic gates are inverters.

14. The buffer circuit of claim 9, wherein: the pulse generator circuit includes a first delay stage, the first delay stage has an input coupled to the pulse generator input terminal; anda pulse generator circuit logic gate operating at the second supply potential, the pulse generator circuit logic gate has a first input coupled to the pulse generator input terminal and a second input coupled to receive an output from the first delay stage and coupled to provide the pulse signal.

15. The buffer circuit of claim 14, wherein: the pulse generator circuit logic gate is a NAND logic gate.

16. The buffer circuit of claim 14, wherein: the pulse signal has a predetermined pulse width having a first edge that enables the boost drive circuit to provide the low impedance path and a second edge that disables the low impedance path when a load coupled to the output node is charged to about the first supply potential.

17. The buffer circuit of claim 16, wherein: the first delay stage provides a propagation delay path for the input signal, the propagation delay path essentially sets the predetermined pulse width.

18. The buffer circuit of claim 17, wherein: the first delay stage further includes a first delay stage logic gate operating at the first supply potential, the first delay stage logic gate has an input coupled to the pulse generator circuit input terminal;a second delay stage logic gate operating at a third supply potential, the second delay stage logic gate has an input coupled to an output of the first delay stage logic gate;a third delay stage logic gate operating at the second supply potential, the third delay stage logic gate has an input coupled to an output of the second delay stage logic gate and an output coupled to the second input terminal of the pulse generator circuit logic gate; andthe third supply potential is greater than the first supply potential and less than the second supply potential.

19. The buffer circuit of claim 18, wherein: the first, second, and third delay stage logic gates are inverters.

20. The buffer circuit of claim 18, wherein: the low voltage drive circuit is coupled to receive the output of the second delay stage logic gate at the low voltage drive circuit input terminal.