The disclosure relates to a multiplex gate driving circuit, and more particularly to a multiplex gate driving circuit for driving a liquid crystal display (LCD) panel.
Generally, the LCD panel usually comprises a visible zone and an invisible zone and the gate on array (GOA) are integrated on the invisible zone. The invisible zone comprises the gate driver for sequentially generating a plurality of gate driving signals. The visible zone is a thin film transistor array comprising plural gate lines. The gate driving signals are sequentially provided to the gate lines, and thus the pixels connected to the gate lines are sequentially turned on.
As shown in
Please refer to
Therefore, the disclosure provides a multiplex gate driving circuit whose driving stage has less number of transistors, thereby reducing the area of the invisible zone of the LCD panel.
In accordance with an aspect, the disclosure provides a multiplex gate driving circuit. The multiplex gate driving circuit includes m shift registers and n driving stages. The m shift registers are used for receiving a clock signal and sequentially generating m master signals. The m master signals are non-overlapped positive pulses with a first width. An x-th shift register of the m shift registers generates an x-th master signal. The n driving stages are used for respectively receiving n slave signals and sequentially generating n gate driving signals. A duty cycle of each slave signal is equal to 1/n. A phase difference between every two adjacent slave signals is equal to 360/n degrees. Each of the n slave signals includes plural positive pulses. An i-th driving stage of the n driving stages includes an n-type transistor and a p-type transistor. The n-type transistor has a control terminal receiving an i-th slave signal of the n slave signals, a first terminal receiving the x-th master signal and a second terminal generating an i-th gate driving signal of the n gate driving signals. The p-type transistor has a control terminal receiving the i-th slave signal, a first terminal connected with the second terminal of the n-type transistor and a second terminal receiving an inverted power-off control signal.
In accordance with another aspect, the disclosure provides a multiplex gate driving circuit. The multiplex gate driving circuit includes m shift registers and n driving stages. The m shift registers are used for receiving a clock signal and sequentially generating m master signals. The m master signals are non-overlapped positive pulses with a first width. An x-th shift register of the m shift registers generates an x-th master signal. The n driving stages are used for respectively receiving n slave signals and sequentially generating n gate driving signals. A duty cycle of each slave signal is equal to 1/n. A phase difference between every two adjacent slave signals is equal to 360/n degrees. Each of the n slave signals includes plural negative pulses. An i-th driving stage of the n driving stages includes an n-type transistor and a p-type transistor. The p-type transistor has a control terminal receiving an i-th slave signal of the n slave signals, a first terminal receiving the x-th master signal and a second terminal generating an i-th gate driving signal of the n gate driving signals. The n-type transistor has a control terminal receiving the i-th slave signal, a first terminal connected with the second terminal of the p-type transistor and a second terminal receiving an inverted power-off control signal.
In accordance with another aspect, the disclosure provides a multiplex gate driving circuit. The multiplex gate driving circuit includes m shift registers and n driving stages. The m shift registers are used for receiving a clock signal and sequentially generating m master signals. The m master signals are non-overlapped negative pulses with a first width. An x-th shift register of the m shift registers generates an x-th master signal. The n driving stages are used for respectively receiving n slave signals and sequentially generating n gate driving signals. A duty cycle of each slave signal is equal to 1/n. A phase difference between every two adjacent slave signals is equal to 360/n degrees. Each of the n slave signals includes plural positive pulses. An i-th driving stage of the n driving stages includes an n-type transistor, a p-type transistor and an inverter. The n-type transistor has a control terminal receiving an i-th slave signal of the n slave signals and a first terminal receiving the x-th master signal. The inverter has an input terminal connected with a second terminal of the n-type transistor and an output terminal generating an i-th gate driving signal of the n gate driving signals. The p-type transistor has a control terminal receiving the i-th slave signal, a first terminal connected with the second terminal of the n-type transistor and a second terminal receiving a power-off control signal.
In accordance with another aspect, the disclosure provides a multiplex gate driving circuit. The multiplex gate driving circuit includes m shift registers and n driving stages. The m shift registers are used for receiving a clock signal and sequentially generating m master signals. The m master signals are non-overlapped negative pulses with a first width. An x-th shift register of the m shift registers generates an x-th master signal. The n driving stages are used for respectively receiving n slave signals and sequentially generating n gate driving signals. A duty cycle of each slave signal is equal to 1/n. A phase difference between every two adjacent slave signals is equal to 360/n degrees. Each of the n slave signals includes plural negative pulses. An i-th driving stage of the n driving stages includes an n-type transistor, a p-type transistor and an i-th inverter. The p-type transistor has a control terminal receiving an i-th slave signal of the n slave signals and a first terminal receiving the x-th master signal. The inverter has an input terminal connected with a second terminal of the p-type transistor and an output terminal generating an i-th gate driving signal of the n gate driving signals. The n-type transistor has a control terminal receiving the i-th slave signal, a first terminal connected with the second terminal of the p-type transistor and a second terminal receiving a power-off control signal.
In accordance with another aspect, the disclosure provides a multiplex gate driving circuit. The multiplex gate driving circuit includes m shift registers and n driving stages. The m shift registers are used for receiving a clock signal and sequentially generating m master signals. The m master signals are non-overlapped negative pulses with a first width. An x-th shift register of the m shift registers generates an x-th master signal. The n driving stages are used for respectively receiving n slave signals and sequentially generating n gate driving signals. A duty cycle of each slave signal is equal to 1/n. A phase difference between every two adjacent slave signals is equal to 360/n degrees. Each of the n slave signals includes plural negative pulses. An i-th driving stage of the n driving stages includes an n-type transistor, a p-type transistor and an inverter. The p-type transistor has a control terminal receiving the x-th master signal and a first terminal receiving an i-th slave signal of the n slave signals. The inverter has an input terminal connected with a second terminal of the p-type transistor and an output terminal generating an i-th gate driving signal of the n gate driving signals. The n-type transistor has a control terminal receiving the x-th master signal, a first terminal connected with the second terminal of the p-type transistor and a second terminal receiving a power-off control signal.
The disclosure will now be described more specifically with reference to the following embodiments. It is to be noted that the following descriptions of the embodiments are presented herein for purpose of illustration and description only. It is not intended to be exhaustive or to be limited to the precise form disclosed.
In response to the start signal START, the first shift register 410 is triggered to generate the first master signal S1 and issues a first notification signal N1 to the second shift register 420. In response to the first notification signal, the second shift register 420 is triggered to generate the second master signal S2 and issues a second notification signal N2 to the first shift register 410 and the third shift register 430. In response to the second notification signal N2, the first shift register 410 stops generating the first master signal S1, and the third shift register 430 issues the third master signal S3.
From the above discussion, in response to the (x−1)-th notification signal Nx−1 from the (x−1)-th shift register, the x-th shift register generates the x-th master signal Sx and issues the x-th notification signal Nx to the x−1)-th shift register or the (x+1)-th shift register, the transmission direction is depends on the start signal trigs from up or down. In response to the x-th notification signal, the (x+1)-th shift register stops generating the (x−1)-th master signal Sx−1, and the (x+1)-th shift register generates the (x+1)-th master signal Sx+.
Moreover, for creating the gate driving signals, the master signals S1˜Sm and the slave signals P1˜Pn may have diverse forms (e.g. positive pulses or negative pulses) by employing proper configurations of the shift registers and the driving stages. Hereinafter, the master signals S1˜Sm and the slave signals P1˜Pn in various forms will be illustrated with reference to
In
In
In
In
In this embodiment, the first driving module 41 of the multiplex gate driving circuit 400 generates six gate driving signal Y1˜Y6 according to the first master signal S1 and the six slave signals P1˜P6. The operating principles of other driving modules are similar to those of the first driving module, and are not redundantly described herein. Please refer to
The x-th driving module 520 comprises a shift register 530 and three driving stages 551˜55n (n=3). The shift register 530 comprises a bidirectional input circuit 532 and a shift unit 534. Since the x-th driving module 520 has three driving stages, three slave signals P1˜P3 are respectively received by the three driving stages. It is noted that if the x-th driving module 520 has n driving stages, n slave signals are respectively received by the n driving stages.
The first driving stage 551 comprises a transistor TP1, a transistor TN1 and an inverter INV1. The first slave signal P1 is received by the source terminal of the transistor TP1. The x-th master signal Sx is received by the gate terminal of the transistor TP1. The drain terminal of the transistor TN1 is connected with the drain terminal of the transistor TP1. The x-th master signal Sx is also received by the gate terminal of the transistor TN1. The power-off control signal POFF is received by the source terminal of the transistor TN1. An input terminal of the inverter INV1 is connected with the drain terminal of the transistor TP1. The gate driving signal Y3x−2 is outputted from an output terminal of the inverter INV1. Similarly, the second slave signal P2 is received by the second driving stage 552, and the third slave signal P3 is received by the third driving stage 553. The connecting relationship is not redundantly described herein.
The bidirectional input circuit 532 comprises a transistor TN4 and a transistor TN5. A first voltage U2D (e.g. a high logic-level voltage) is received by the drain terminal of the transistor TN4. The (x−1)-th notification signal Nx−1 from the (x−1)-th driving module (not shown) is received by the gate terminal of the transistor TN4. The drain terminal of the transistor TN5 is connected with the source terminal of the transistor TN4. The (x+1)-th notification signal Nx+1 from the (x+1)-th driving module (not shown) is received by the gate terminal of the transistor TN5. A second voltage D2U (e.g. a low logic-level voltage) is received by the source terminal of the transistor TN5. Moreover, a control signal C is outputted from the source terminal of the transistor TN4. Obviously, if the (x−1)-th notification signal Nx−1 is in the high level state, the control signal C is in the high level state; but if the (x+1)-th notification signal Nx+1 is in the high level state, the control signal C is in the low level state.
The shift unit 534 comprises a transistor TN6, a transistor TN7, a transistor TN8, a transistor TN9, a NAND gate and an inverter INV4. The control signal C is received by the gate terminal of the transistor TN6. A clock signal CK is received by the drain terminal of the transistor TN6. The control signal C is received by the gate terminal of the transistor TN7. The source terminal and the drain terminal of the transistor TN7 are connected to the source terminal of the transistor TN6. The control signal C is also received by the drain terminal of the transistor TN8. The source terminal of the transistor TN8 is connected with the source terminal of the transistor TN7. The drain terminal of the transistor TN9 is connected with the source terminal of the transistor TN7. A third voltage Vss (e.g. a low logic-level voltage) is received by the source terminal of the transistor TN9. The control signal C is also received by the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected with the gate terminal of the transistor TN8 and gate terminal of the transistor TN9. A first input terminal of the NAND gate is connected with the source terminal of the transistor TN7. The power-off control signal POFF is received by a second input terminal of the NAND gate. The x-th master signal Sx is outputted from the output terminal of the NAND gate. Moreover, the x-th notification signal Nx is outputted from the source terminal of the transistor TN7.
Please refer to
Moreover, at an arbitrary time spot t5 when the power-off control signal POFF is changed from the high level state to the low level state, all of the gate driving signal Y3x−2, Y3x−2 and Y3x are switched to the high level state. Consequently, no image sticking phenomenon occurs in the thin film transistor array of the visible zone of the conventional LCD panel.
The x-th driving module 560 comprises a shift register 530 and three driving stages 561˜56n (n=3). The shift register 530 is identical to that of the first example, and is not redundantly described herein. Since the x-th driving module 560 has three driving stages, three slave signals P1˜P3 are respectively received by the three driving stages. It is noted that if the x-th driving module 560 has n driving stages, n slave signals are respectively received by the n driving stages.
The first driving stage 561 comprises a transistor TP1, a transistor TN1 and an inverter INV1. The first slave signal P1 is received by the gate terminal of the transistor TN1. The x-th master signal Sx is received by the drain terminal of the transistor TN1. The source terminal of the transistor TP1 is connected with the source terminal of the transistor TN1. The first slave signal P1 is also received by the gate terminal of the transistor TP1. The power-off control signal POFF is received by the drain terminal of the transistor TP1. An input terminal of the inverter INV1 is connected with the source terminal of the transistor TP1. The gate driving signal Y3x−2 is outputted from an output terminal of the inverter INV1. Similarly, the second slave signal P2 is received by the second driving stage 562, and the third slave signal P3 is received by the third driving stage 563. The connecting relationship is not redundantly described herein.
Please refer to
Moreover, at an arbitrary time spot t5 when the power-off control signal POFF is changed from the high level state to the low level state, all of the gate driving signal Y3x−2, Y3x−1 and Y3x are switched to the high level state. Consequently, no image sticking phenomenon occurs in the thin film transistor array of the visible zone of the conventional LCD panel.
The x-th driving module 570 comprises a shift register 530 and three driving stages 571˜57n (n=3). The shift register 530 is identical to that of the first example, and is not redundantly described herein. Since the x-th driving module 570 has three driving stages, three slave signals P1˜P3 are respectively received by the three driving stages. It is noted that if the x-th driving module 570 has n driving stages, n slave signals are respectively received by the n driving stages.
The first driving stage 571 comprises a transistor TP1, a transistor TN1 and an inverter INV1. The first slave signal P1 is received by the gate terminal of the transistor TP1. The x-th master signal Sx is received by the source terminal of the transistor TP1. The drain terminal of the transistor TN1 is connected with the drain terminal of the transistor TP1. The first slave signal P1 is also received by the gate terminal of the transistor TN1. The power-off control signal POFF is received by the source terminal of the transistor TN1. An input terminal of the inverter INV1 is connected with the drain terminal of the transistor TP1. The gate driving signal Y3x−2 is outputted from an output terminal of the inverter INV1. Similarly, the second slave signal P2 is received by the second driving stage 572, and the third slave signal P3 is received by the third driving stage 573. The connecting relationship is not redundantly described herein.
Please refer to
Moreover, at an arbitrary time spot t5 when the power-off control signal POFF is changed from the high level state to the low level state, all of the gate driving signal Y3x−2, Y3x−1 and Y3x are switched to the high level state. Consequently, no image sticking phenomenon occurs in the thin film transistor array of the visible zone of the conventional LCD panel.
The x-th driving module 590 comprises a shift register 580 and three driving stages 591˜59n (n=3). The shift register 580 comprises a bidirectional input circuit 582 and a shift unit 584. Since the x-th driving module 590 has three driving stages, three slave signals P1˜P3 are respectively received by the three driving stages. It is noted that if the x-th driving module 590 has n driving stages, n slave signals are respectively received by the n driving stages.
The first driving stage 591 comprises a transistor TP1, a transistor TN1 and an inverter INV1. The first slave signal P1 is received by the gate terminal of the transistor TN1. The x-th master signal Sx is received by the drain terminal of the transistor TN1. The source terminal of the transistor TP1 is connected with the source terminal of the transistor TN1. The first slave signal P1 is also received by the gate terminal of the transistor TP1. The power-off control signal POFF is received by the drain terminal of the transistor TP1. An input terminal of the inverter INV1 is connected with the source terminal of the transistor TP1. The gate driving signal Y3x−2 is outputted from an output terminal of the inverter INV1. Similarly, the second slave signal P2 is received by the second driving stage 592, and the third slave signal P3 is received by the third driving stage 593. The connecting relationship is not redundantly described herein.
The bidirectional input circuit 582 comprises a transistor TN4 and a transistor TN5. A first voltage U2D (e.g. a high logic-level voltage) is received by the drain terminal of the transistor TN4. The (x−1)-th notification signal Nx−1 from the (x−1)-th driving module (not shown) is received by the gate terminal of the transistor TN4. The drain terminal of the transistor TN5 is connected with the source terminal of the transistor TN4. The (x+1)-th notification signal Nx+1 from the (x+1)-th driving module (not shown) is received by the gate terminal of the transistor TN5. A second voltage D2U (e.g. a low logic-level voltage) is received by the source terminal of the transistor TN5. Moreover, a control signal C is outputted from the source terminal of the transistor TN4. Obviously, if the (x−1)-th notification signal Nx−1 is in the high level state, the control signal C is in the high level state; but if the (x+1)-th notification signal Nx+1 is in the high level state, the control signal C is in the low level state.
The shift unit 584 comprises a transistor TN6, a transistor TN7, a transistor TN8, a transistor TN9, an inverter INV4 and an inverter INV5. The control signal C is received by the gate terminal of the transistor TN6. A clock signal CK is received by the drain terminal of the transistor TN6. The control signal C is received by the gate terminal of the transistor TN7. The source terminal and the drain terminal of the transistor TN7 are connected to the source terminal of the transistor TN6. The control signal C is also received by the drain terminal of the transistor TN8. The source terminal of the transistor TN8 is connected with the source terminal of the transistor TN7. The drain terminal of the transistor TN9 is connected with the source terminal of the transistor TN7. A third voltage Vss (e.g. a low logic-level voltage) is received by the source terminal of the transistor TN9. The control signal C is also received by the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected with the gate terminal of the transistor TN8 and gate terminal of the transistor TN9. The input terminal of the inverter INV5 is connected with the source terminal of the transistor TN7. The x-th master signal Sx is outputted from the output terminal of the inverter INV5. Moreover, the x-th notification signal Nx is outputted from the source terminal of the transistor TN7.
Please refer to
Moreover, at an arbitrary time spot t5 when the power-off control signal POFF is changed from the high level state to the low level state, all of the gate driving signal Y3x−2, Y3x−1 and Y3x are switched to the high level state. Consequently, no image sticking phenomenon occurs in the thin film transistor array of the visible zone of the conventional LCD panel.
The x-th driving module 600 comprises a shift register 580 and three driving stages 601˜60n (n=3). The shift register 580 is identical to that of the fourth example, and is not redundantly described herein. Since the x-th driving module 600 has three driving stages, three slave signals P1˜P3 are respectively received by the three driving stages. It is noted that if the x-th driving module 600 has n driving stages, n slave signals are respectively received by the n driving stages.
The first driving stage 601 comprises a transistor TP1, a transistor TN1 and an inverter INV1. The first slave signal P1 is received by the gate terminal of the transistor TP1. The x-th master signal Sx is received by the source terminal of the transistor TP1. The drain terminal of the transistor TN1 is connected with the drain terminal of the transistor TP1. The first slave signal P1 is also received by the gate terminal of the transistor TN1. The power-off control signal POFF is received by the source terminal of the transistor TN1. An input terminal of the inverter INV1 is connected with the drain terminal of the transistor TP1. The gate driving signal Y3x−2 is outputted from an output terminal of the inverter INV1. Similarly, the second slave signal P2 is received by the second driving stage 602, and the third slave signal P3 is received by the third driving stage 603. The connecting relationship is not redundantly described herein.
Please refer to
Moreover, at an arbitrary time spot t5 when the power-off control signal POFF is changed from the high level state to the low level state, all of the gate driving signal Y3x−2, Y3x−1 and Y3x are switched to the high level state. Consequently, no image sticking phenomenon occurs in the thin film transistor array of the visible zone of the conventional LCD panel.
The x-th driving module 620 comprises a shift register 610 and three driving stages 621˜62n (n=3). The shift register 610 comprises a bidirectional input circuit 612 and a shift unit 614. Since the x-th driving module 620 has three driving stages, three slave signals P1˜P3 are respectively received by the three driving stages. It is noted that if the x-th driving module 620 has n driving stages, n slave signals are respectively received by the n driving stages.
The first driving stage 621 comprises a transistor TP1, a transistor TN1 and an inverter INV1. The first slave signal P1 is received by the gate terminal of the transistor TN1. The x-th master signal Sx is received by the drain terminal of the transistor TN1. The source terminal of the transistor TP1 is connected with the source terminal of the transistor TN1. The first slave signal P1 is also received by the gate terminal of the transistor TP1. The power-off control signal POFF is received by the drain terminal of the transistor TP1. An input terminal of the inverter INV1 is connected with the source terminal of the transistor TP1. The gate driving signal Y3x−2 is outputted from an output terminal of the inverter INV1. Similarly, the second slave signal P2 is received by the second driving stage 622, and the third slave signal P3 is received by the third driving stage 623. The connecting relationship is not redundantly described herein.
The bidirectional input circuit 612 comprises a transistor TN and a transistor TP5. A first voltage
The shift unit 614 comprises a transistor TN4, a transistor TP6, a transistor TP7, a transistor TP8 and an inverter INV4. The control signal C is received by the gate terminal of the transistor TP6. A clock signal CK is received by the source terminal of the transistor TP6. The control signal C is also received by the gate terminal of the transistor TN4. The source terminal and the drain terminal of the transistor TN4 are connected to the drain terminal of the transistor TP6. The control signal C is also received by the source terminal of the transistor TP7. The drain terminal of the transistor TP7 is connected with the source terminal of the transistor TN4. The source terminal of the transistor TP8 is connected with the source terminal of the transistor TN4. A third voltage Vcc (e.g. a high logic-level voltage) is received by the drain terminal of the transistor TP8. The control signal C is also received by the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected with the gate terminal of the transistor TP7 and gate terminal of the transistor TP8. Moreover, the x-th notification signal Nx and the x-th master signal Sx that have the same voltage level are outputted from the source terminal of the transistor TN4.
Please refer to
Moreover, at an arbitrary time spot t5 when the power-off control signal POFF is changed from the high level state to the low level state, all of the gate driving signal Y3x−2, Y3x−1 and Y3x are switched to the high level state. Consequently, no image sticking phenomenon occurs in the thin film transistor array of the visible zone of the conventional LCD panel.
The x-th driving module 630 comprises a shift register 610 and three driving stages 631˜63n (n=3). The shift register 610 is identical to that of the sixth example, and is not redundantly described herein. Since the x-th driving module 630 has three driving stages, three slave signals P1˜P3 are respectively received by the three driving stages. It is noted that if the x-th driving module 630 has n driving stages, n slave signals are respectively received by the n driving stages.
The first driving stage 631 comprises a transistor TP1, a transistor TN1 and an inverter INV1. The first slave signal P1 is received by the gate terminal of the transistor TP1. The x-th master signal Sx is received by the source terminal of the transistor TP1. The drain terminal of the transistor TN1 is connected with the drain terminal of the transistor TP1. The first slave signal P1 is also received by the gate terminal of the transistor TN1. The power-off control signal POFF is received by the source terminal of the transistor TN1. An input terminal of the inverter INV1 is connected with the drain terminal of the transistor TP1. The gate driving signal Y3x−2 is outputted from an output terminal of the inverter INV1. Similarly, the second slave signal P2 is received by the second driving stage 632, and the third slave signal P3 is received by the third driving stage 633. The connecting relationship is not redundantly described herein.
Please refer to
Moreover, at an arbitrary time spot t5 when the power-off control signal POFF is changed from the high level state to the low level state, all of the gate driving signal Y3x−2, Y3x−1 and Y3x are switched to the high level state. Consequently, no image sticking phenomenon occurs in the thin film transistor array of the visible zone of the conventional LCD panel.
The x-th driving module 650 comprises a shift register 640 and three driving stages 651˜65n (n=3). The shift register 640 comprises a bidirectional input circuit 642 and a shift unit 644. Since the x-th driving module 650 has three driving stages, three slave signals P1˜P3 are respectively received by the three driving stages. It is noted that if the x-th driving module 650 has n driving stages, n slave signals are respectively received by the n driving stages.
The first driving stage 651 comprises a transistor TP1 and a transistor TN1. The first slave signal P1 is received by the gate terminal of the transistor TN1. The x-th master signal Sx is received by the drain terminal of the transistor TN1. The source terminal of the transistor TP1 is connected with the source terminal of the transistor TN1. The first slave signal P1 is also received by the gate terminal of the transistor TP1. An inverted power-off control signal
The bidirectional input circuit 624 comprises a transistor TN4 and a transistor TN5. A first voltage U2D (e.g. a high logic-level voltage) is received by the drain terminal of the transistor TN4. The (x−1)-th notification signal Nx−1 from the (x−1)-th driving module (not shown) is received by the gate terminal of the transistor TN4. The drain terminal of the transistor TN5 is connected with the source terminal of the transistor TN4. The (x+1)-th notification signal Nx+1 from the (x+1)-th driving module (not shown) is received by the gate terminal of the transistor TN5. A second voltage D2U (e.g. a low logic-level voltage) is received by the source terminal of the transistor TN5. Moreover, a control signal C is outputted from the source terminal of the transistor TN4. Obviously, if the (x−1)-th notification signal Nx−1 is in the high level state, the control signal C is in the high level state; but if the (x+1)-th notification signal Nx−1 is in the high level state, the control signal C is in the low level state.
The shift unit 644 comprises a transistor TN6, a transistor TN7, a transistor TN8, a transistor TN9 and an inverter INV4. The control signal C is received by the gate terminal of the transistor TN6. A clock signal CK is received by the drain terminal of the transistor TN6. The control signal C is received by the gate terminal of the transistor TN7. The source terminal and the drain terminal of the transistor TN7 are connected to the source terminal of the transistor TN6. The control signal C is also received by the drain terminal of the transistor TN8. The source terminal of the transistor TN8 is connected with the source terminal of the transistor TN7. The drain terminal of the transistor TN9 is connected with the source terminal of the transistor TN7. A third voltage Vss (e.g. a low logic-level voltage) is received by the source terminal of the transistor TN9. The control signal C is also received by the input terminal of the inverter INV4. The output terminal of the inverter INV4 is connected with the gate terminal of the transistor TN8 and gate terminal of the transistor TN9. Moreover, the x-th notification signal Nx and the x-th master signal Sx that have the same voltage level are outputted from the source terminal of the transistor TN7.
Please refer to
Moreover, at an arbitrary time spot t5 when the power-off control signal POFF is changed from the high level state to the low level state (i.e. the inverted power-off control signal
The x-th driving module 660 comprises a shift register 640 and three driving stages 661˜66n (n=3). The shift register 640 is identical to that of the eighth example, and is not redundantly described herein. Since the x-th driving module 660 has three driving stages, three slave signals P1˜P3 are respectively received by the three driving stages. It is noted that if the x-th driving module 660 has n driving stages, n slave signals are respectively received by the n driving stages.
The first driving stage 661 comprises a transistor TP1 and a transistor TN1. The first slave signal P1 is received by the gate terminal of the transistor TP1. The x-th master signal Sx is received by the source terminal of the transistor TP1. The drain terminal of the transistor TN1 is connected with the drain terminal of the transistor TP1. The first slave signal P1 is also received by the gate terminal of the transistor TN1. An inverted power-off control signal
Please refer to
Moreover, at an arbitrary time spot t5 when the power-off control signal POFF is changed from the high level state to the low level state (i.e. the inverted power-off control signal
From the above description, the disclosure provides a multiplex gate driving circuit with plural driving modules. In comparison with the related art, each driving stage of the driving module has less number of transistors. From the first example to the seventh example, each driving stage is implemented by only four transistors (the inverter needs two transistors). In the eighth example and the ninth example, each driving stage is implemented by only two transistors. In other words, the driving stage of the multiplex gate driving circuit has less number of transistors, thereby reducing the layout area of the invisible zone of the LCD panel.
While the disclosure has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.
Number | Date | Country | Kind |
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099141463 | Nov 2010 | TW | national |