Multiplex switching

Abstract

Multiplex switching is disclosed for readily multiplexing and switching packet data without causing a delay. Bit widths of packets supplied from a plurality of input channels are unified to a previously set bit width. The packets unified in bit width are synchronized among the plurality of input channels. The synchronized packets are spread by multiplying them by orthogonal codes based on the input channels. The spread packets are multiplexed, and multiplexed packets are multiplied respectively by orthogonal codes for switching according to the input channels on which the packets delivered to output channels have been supplied, to reconstruct the packets supplied from the input channels. The packets are then delivered to the output channels.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating how packets are stored in a conventional packet transmission apparatus;

FIG. 2 is a diagram illustrating one embodiment of a multiplex switching circuit according to the present invention;

FIG. 3 is a diagram illustrating an exemplary configuration of an orthogonal code multiplex switching memory unit shown in FIG. 2;

FIG. 4 is a sequence diagram for describing a multiplex switching method in the multiplex switching circuit illustrated in FIGS. 2 and 3;

FIG. 5 is a diagram illustrating how to unify bit widths of packets which are temporarily stored in bit width conversion/synchronization FIFOs; and

FIG. 6 is a diagram illustrating how packets are processed from step 5 to step 7 in FIG. 4.

Claims

1. A multiplex switching circuit for unifying bit widths of packets supplied from a plurality of input channels to a previously set bit width, establishing synchronization among the plurality of input channels that the packets are input into, the bit widths of which have been unified, spreading the synchronized packets by multiplying the same by orthogonal codes according to the input channels, multiplexing the spread packets, multiplying the multiplexed packets by an orthogonal code for switching according to an input channel on which a packet delivered to an output channel has been supplied to reconstruct the packet, and delivering the packet to the output channel.

2. A multiplex switching circuit comprising: a bit width conversion/synchronization FIFO for unifying bit widths of packets supplied from a plurality of input channels to a previously set bit width, and for establishing synchronization among the plurality of input channels that the packets are input into, the bit widths of which have been unified;a spreading unit for spreading the packets synchronized by said bit width conversion/synchronization FIFO by multiplying the same by orthogonal codes according to the input channels;a multiplexing unit for multiplexing the packets spread by said spreading unit; anda reconstruction unit for multiplying the packets multiplexed by said multiplexing unit by an orthogonal code for switching according to an input channel on which a packet delivered to an output channel has been supplied to reconstruct the packet, to deliver the packet to the output channel.

3. The multiplex switching circuit according to claim 1, wherein said orthogonal code and said orthogonal code for switching are Gold codes.

4. The multiplex switching circuit according to claim 2, wherein said orthogonal code and said orthogonal code for switching are Gold codes.

5. The multiplex switching circuit according to claim 1, wherein said orthogonal code and said orthogonal code for switching are Walsh-Hadamard codes.

6. The multiplex switching circuit according to claim 2, wherein said orthogonal code and said orthogonal code for switching are Walsh-Hadamard codes.

7. A switching method for multiplexing packets supplied from a plurality of channels and for delivering the packets to a plurality of output channels, the method comprising steps of: unifying bit widths of packets supplied from a plurality of input channels to a previously set bit width;establishing synchronization among the plurality of input channels that the packets are input into, the bit widths of which have been unified;multiplying the synchronized packets by orthogonal codes according to the input channels;multiplexing the packets multiplied by the orthogonal codes; andmultiplying the multiplexed packets by a orthogonal code for switching according to an input channel on which a packet delivered to an output channel has been supplied.

8. The method according to claim 7, wherein said orthogonal code and said orthogonal code for switching are Gold codes.

9. The method according to claim 7, wherein said orthogonal code and said orthogonal code for switching are Walsh-Hadamard codes.