Multiplexing of DS1 traffic across wired and wireless Ethernet devices

Abstract

Apparatuses and methods for multiplexing of DS1 traffic across wired and wireless Ethernet devices. A transmitter sends data packets to a receiver through an Ethernet system. The transmitter includes a modeling module that constructs a modeled jitter buffer corresponding to a receiver jitter buffer located at the receiver. The transmitter also includes a packetizing buffer that collects data to form data packets, that inserts buffer pointers into the data packets, and that sends the data packets through the Ethernet system. A buffer pointer is determined from the modeled jitter buffer. The receiver includes an Ethernet interface module that obtains the data packets from the Ethernet system, a jitter buffer, and a depacketizer that reads a buffer pointer in the data packet and that places the data packet into a position within the receiver jitter buffer in accordance with the buffer pointer.

Description

FIELD OF THE INVENTION

The invention relates multiplexing DS1 traffic over Ethernet facilities.

BACKGROUND OF THE INVENTION

Communications systems have traditionally supported voice services separately from data services. However, voice signals are typically represented in a digital format, such as with a time division multiplexed (TDM) signal. Moreover, packet-switched data transmission is increasingly replacing circuit-switched data transmission, in which communications paths are no longer fixed but typically vary in time. Consequently, in order to efficiently utilize a packet data network, there is a market need to support both TDM signals and other types of digital signals by a packet data network.

SUMMARY

The present invention supports multiplexing of DS1 (E1and T1) traffic across wired and wireless Ethernet devices and is associated with a family of devices known as Time Division Multiplex over Internet Protocol (TDMoIP). With an aspect of the invention, LAN traffic is multiplexed along with the T1/E1 payload. The LAN traffic is managed to utilize only the available bandwidth in the connection to avoid interfering with the TDM traffic.

With another aspect of the invention, a transmitter sends data packets to a receiver through an Ethernet system. The transmitter includes a clock recovery module that recovers inherent clocking information from a signal obtained from the Ethernet system and a modeling module that constructs a modeled jitter buffer corresponding to a receiver jitter buffer located at the receiver. The transmitter also includes a packetizing buffer that collects data to form data packets, that inserts buffer pointers into the data packets, and that sends the data packets through the Ethernet system. A buffer pointer is determined from the modeled jitter buffer. The packetizing buffer may also repeat a data bit that is contained in a data packet in another data packet in order to support forward error correction.

With another aspect of the invention, a receiver receives data packets from a transmitter through an Ethernet system. The receiver includes an Ethernet interface module that obtains the data packets from the Ethernet system, a jitter buffer, and a depacketizer that reads a buffer pointer in the data packet and that places the data packet into a position within the jitter buffer in accordance with the buffer pointer. The buffer pointer is indicative of a modeled jitter.

This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the clamed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

BRIEF DESCRIPTION OF DRAWINGS

The foregoing summary of the invention, as well as the following detailed description of preferred embodiments, is better understood when read in conjunction with the accompanying drawings, which are included by way of example, and not by way of limitation with regard to the claimed invention.

FIG. 1 shows packetizing delays for various packet sizes in accordance with an embodiment of the invention.

FIG. 2 shows wire delays for various packet sizes in accordance with an embodiment of the invention.

FIG. 3 shows average protocol delays for various equipment types in accordance with an embodiment of the invention.

FIG. 4 shows a delay histogram that is supported by an embodiment of the invention.

FIG. 5 shows a delay histogram that is supported by an embodiment of the invention.

FIG. 6 shows an overall delay that is supported by an embodiment of the invention.

DETAILED DESCRIPTION

Overview

In accordance with an embodiment of the invention, a transmission system uses a unique algorithm to transport the multiplexed data streams. An algorithm is optimized for wireless Ethernet transport. Because of the potential for changing conditions that may affect wireless network throughput, the transmission system provides the capability for recovering from data loss, without propagating the errors to following frames.

A transmission system utility user interface allows the creation and management of “Interface Profiles” that contain all the management parameters necessary for optimum operation with each of a wide variety of broadband wireless links. Profiles for each of these units are made available for inclusion in the transmission system setup process.

Because the transmission system provides physical pass-through of the DS1 link, no special configuration or setup is required regardless of the format (e.g., fractional, channelized, clear channel, checksum on or off, etc.). The T1 & E1 signals are precisely repeated No special setup is needed to enable such things as fractional T1; whatever is impressed upon the T1 connection at one end appears unchanged at the other.

With an embodiment of the invention, a transmission architecture enables the transmission system's hardware to be interactive, reprogrammable and reshapable—with scalability and greater dimensionality. The transmission system may be advantageous to competitive technologies that have built-in obsolescence and delivers a far greater value than silicon-based circuitry.

The transmission system may be deployed across a networked environment using wireless broadband, wired Ethernet, or a combination. A channel look-ahead capability continuously estimates the variation of arrival time in conjunction with a programmable channel optimization capability. Consequently, the transmission system may deliver optimum reliability under changing network conditions. For example, when used with a wireless system, the transmission system provides “last mile” T1 & E1 transport across distances limited only by the selected radio's capabilities. It is an ideal, affordable solution for connecting PBX systems in remote office and campus environments. The transmission system may also supplant wire-line T1 & E1 connections to cellular towers, eliminating monthly leased landline charges as well as the associated problems.

Packetizing Machine at the Transmitting End

In accordance with an embodiment of the invention, the ‘transmitting’ transmission system receives bits over the DS1 line via a Line Interface Unit (LIU) that recovers the inherent clock from that bit stream. If the transmission system in question is configured in Mode 2 (‘sync from DS1 bit stream’), that clock is used for processing the DS1 data.

If, however, the transmission system in question is configured in Mode 1 (“the transmission system supplies DS1 clock”) or in Mode 3 (“the transmission system uses clock from other end”), the transmission system's internal clock is supplied to the connected DS1 equipment for it to use in presenting the data to the transmission system interface. Of course, in the case of Mode 3, that internal clock is carefully synchronized with the clock at the far end; that mechanism is discussed in detail in a later section.

The bits from the LIU are sent into a packetizing buffer, where they are collected until there are enough to make a full packet of ‘DS1 packet size’ bytes. Subsequently, a packet header is prepended, the buffer pointers (as will be discussed), the line indicator, and the appropriate checksums are added, and the packet is formed and presented to the Ethernet system for transmission.

The transmitter keeps a model of the jitter buffer at the receiving end, and computes where in that buffer each packet is to go. The buffer pointer is included in the DS1 header portion of each DS1 packet, so that the receiver can read it. Each packet begins just after the last byte of the previous packet, except in the case where Forward Error Correction (FEC) is enabled. In that case, each packet begins at the midpoint of the preceding one, so that two copies of each bit in the DS1 data are actually transmitted; in other words, the information is each DS1 packet is duplicated, ½ in the preceding packet and ½ in the following.

Note that this method of calculating pointers makes the DS1 system independent of changes in packet order. Further, with FEC enabled, the loss or extreme delay of any one packet out of 3 sequential ones makes no difference to the system. This makes the transmission system much less sensitive to channel errors and to widely varying channel delays, allowing for much smaller delays, at the cost of a greater data throughput requirement.

The Ethernet channel delivers packets containing DS1 data to the receiving transmission system. At the receiver, the depacketizer verifies the packet header, reads the buffer pointer, and places the packet into the jitter buffer beginning at the place specified in the pointer contained in the received packet.

There are three additional key registers in the receiver, as follows:

• • the ‘jitter buffer size’
  • the ‘read pointer’, which tells the DS1 output system where to get the next byte to be converted to DS1, and
  • the ‘level counter’, which indicates how many bytes of data have been received since system reset. This last counter is only valid during the startup sequence, from reset until DS1 data starts flowing out of the transmission system.

The startup sequence is:

• • 1. The receiver system is put into reset;
  • 2. The first packet is received from the Ethernet interface;
  • 3. The ‘read pointer’ is set to the pointer address in that packet and frozen at that point;
  • 4. The bytes in the packet are put into the jitter buffer starting at the address contained in the packet, and the ‘level counter’ is incremented as the bytes are put into the buffer;
  • 5. When the last byte in the packet has been put into the buffer, a check is made to see if the ‘level counter’ exceeds ½ of the ‘buffer size’; if it does not, the receiver keeps the ‘read pointer’ frozen at its initial state (as in step 3), and returns to step 4 for the next packet.
  • 6. When the check at the end of a packet results in the ‘level counter’ being equal to or greater than ½ the ‘jitter buffer size’, the ‘read pointer’ is freed and the DS1 output is turned on. The above procedure results in an integer number of packets in the buffer at the start of the DS1 output. When FEC is enabled, the ‘level counter’ is only incremented once for each 2 bytes received. Clock Recovery

The clock used to send bits out the DS1 interface (from the transmission system to the connected telecommunications equipment) comes from one of 4 choices:

• • Mode 1. The transmission system's internal clock is used as the reference.
  • Mode 2. The clock recovered from the DS1 line and used in the packetizing sequence is also used to transmit the bits that the transmission system receivers from the other end of the system (from its partner transmission system). In this way, the transmission system that is located at the timing source point presents consistent information to the DS1 system.
  • Mode 3. In this mode, the transmission system synchronizes its clock to the clock in use at the transmitting end, by using a sophisticated digital filtering process and information gained from the level of the jitter buffer.
  • Mode 4. In Mode 4, the transmission system uses information from an (external) out-of-band (that is, not part of the Ethernet link between the transmission system pair) signaling path, such as a GPS receiver at each end, or the Ethernet device's frame timing mechanism.

In Mode 3, the transmission system incorporates a series of unique mechanisms. First, as each TDM packet is received, the instantaneous level of the jitter buffer is recorded. Then, that measurement is inspected to see if is lies within the ‘expected’, or ‘normal’, range for the Ethernet path in use. If it is outside the ‘expected’ range, that is, if it's an ‘outlier’, it is not used in the timing calculation. Otherwise, its value is added to an averaging register.

When a large enough sample of such timing information has been collected to satisfy the next-stage filtering algorithm, the ‘sample estimator’ so collected is passed on the oscillator adjustment routing.

This scheme delivers an estimate of the ‘most probable’ buffer level, not simply the average, and therefore makes the system insensitive to a percentage of packets that take much longer arrive, so that delays such as congestion or radio errors do not cause significant variations in the recovered clock rate.

In Mode 4, the transmitting transmission system at the DS1 timing source (the transmission system that is in Mode 1 or Mode 2) counts the number of DS1 bits that it receives between timing pulses from the external circuitry (such as GPS), and sends the result in a unique packet to the receiving transmission system at the other end. As an alternative to GPS, the transmission system can generate a 1-second pulse from the DS1 data, and supply it (via the power cable) to an Ethernet device configured as Timing Master.

The receiving transmission system (which is typically equipped with a high stability clock option) uses the timing pulse (either from another GPS receiver, or from a timing slave Ethernet device) and the bit count mentioned above to precisely set the oscillator it uses for sending bits to the DS1 line.

Delay Computations

The one-way packet delay consists of 4 components, as follows:

• • The inherent processing delay in the transmission system—the time it takes for the transmission system logic;
  • The packetizing delay—time it takes to assemble a full packet of DS1 data on the transmitting end;
  • The link delay—the time it takes to transmit the packet from one transmission system unit to the other over the WAN link; and
  • The buffering delay—the (unfortunately necessary) time allowance for variations in the WAN link.

The inherent processing delay of the transmission system is less than 10 microseconds; this is insignificant when compared to the other elements in a typical system using a wireless broadband link for the WAN connection

Packetizing delay is the time it takes to assemble one packet. It is found by the formula: $\begin{array}{cc}{D}_{\mathrm{packet}}=\frac{N_{\mathrm{bytes\_per}\mathrm{\_packet}}·8}{D_{\mathrm{DS}1\mathrm{\_bits}\mathrm{\_per}\mathrm{\_second}}}& \left(\mathrm{EQ}.1\right)\end{array}$ Packet Delay=Bytes per packet*8/DS1 bits per second. Some typical sizes are shown in FIG. 1.

The link delay is of course dependent on the wireless link chosen for the WAN path. It has 3 sub-components: the delay on the Ethernet wire on the ends (twice, of course, once for each end), the ‘in the air’ delay, or propagation time, and the delay for the wireless protocol.

The wire delay is the sum of the TCP/IP overhead bits and the DS1 payload bits, all divided by the line rate. Typical values are shown in FIG. 2.

The propagation time due to the speed of light—about 5.5 microseconds per mile of path length, or 3.4 microseconds per kilometer. For a typical of path of say 10 miles or 16 Km, this delay is 55 microseconds; a negligible value when compared to the other system delays.

The protocol delay must really be separated into two more components—the average delay, and the delay variation. In fact, it is this delay variation that we must consider most carefully when the final calculation is made—that of buffering delay (commonly called jitter buffering, but properly de-jitter buffering). First and simplest, the average protocol delay is usually well understood by the manufacturer of the wireless equipment. Some typical values are shown in FIG. 3.

Delay Variation is the most complex item to evaluate in a TDOoIP network. In a wireless network in particular, there is a substantial coupling between delay variation and link reliability; the way the link responds to transmission impairments has a large effect on delay, and characteristic of that effect depends on the error mitigation strategy implemented on the link. There are basically 3 strategies in common use today, as follows:

• • Fragmentation and reassembly, with Automatic Repeat-reQuest (ARQ) covering each of the fragments. This may be implemented with or without Forward Error Correcting (FEC) coding on the fragments.
  • Internal Repeat of the entire packet, again with or without FEC. In this case, the wireless equipment itself repeats the packet if it is not received correctly.
  • Reliance on the retry mechanism of TCP/IP, usually with FEC on the packet. In this case, the (on the order of seconds) retry mechanism of IP is relied upon to provide any link reliability improvement over that of the raw radio channel, although the use of FEC (as in WiFi and WiMax) can make that fairly good.

In order to make the problem of evaluating any particular link more tractable, the transmission system includes a special tool for measuring the statistics of the link delay variation. During normal operation, the transmission system in Mode 3 or 4 takes a sample of the instantaneous link delay every 100 ms, and compiles a histogram. This histogram is available at the console port via an RS-232 or TelNet connection to a PC, and is used by the transmission system itself in making clock synchronization decisions. The date in the next section was taken with the aid of this tool.

For purposes of illustration, one examines type 1 Ethernet systems in accordance with an embodiment of the invention. FIG. 4 shows a histogram of measured values on an actual Ethernet link (backhaul, 10 Mbps). Note the ‘average’ delay of 3.75 ms, and the fairly slow dropoff as times get longer—out to 0.001% probability at about 7.5 ms (a total delay variation from the average of 7.50-3.75=3.25 ms. This is, in fact, considered a “good” link.

With an exemplary embodiment of the invention, a fragment that arrives at the receiver with errors is retransmitted 1 or 2 frames later (frames are 2.5 ms), so that the impact of an error on one of the (64 byte) fragments is to delay the entire Ethernet packet by an additional 2.5 or 5 ms. Of course, very occasionally, the retransmission may itself be lost, causing yet another 2.5 or 5 ms of delay.

In addition, there is a uniformly-distributed delay due to the framing. This delay varies (with a constant incremental probability) from 0.2 ms to 2.7 ms, giving an average value of about 1.5 ms. It is these two values taken together that make the ‘average’ 3.75 ms mentioned earlier.

FIG. 5 shows a histogram for a link in a poorer situation with respect to the histogram shown in FIG. 4. In this case, delays extend out to over 23 ms, and one suspects that there in fact some significant number of packets that are lost. One may examine the impact on a DS1 link. The average packet rate is on the order of 200 packets per second (pps); a rate of 0.001% (20 ms on this chart) is therefore an event rate one packet in 1 million, or about one packet exceeding this delay every 1⅓ hours—17 errored seconds per day, as long as the delay causes only a packet's worth of bit errors.

This is where one of the features of the transmission system comes into play—the buffer pointer to each piece of data is actually embedded in the transmitted packet, so if a packet is not received in time, the receiver still keeps sending processed information. It will of course send error bits as long as the proper packet doesn't arrive, but it won't lose clock information, and as soon as the new packet does arrive the proper information will be extracted and sent.

Forward Error Correction

If FEC is activated, each bit is sent in two different packets. The probability of two packets in sequence being delayed or lost is much lower than in the normal case.

FIG. 6 shows typical overall delays for a backhaul link that is supported by an embodiment of the invention.

As can be appreciated by one skilled in the art, a computer system with an associated computer-readable medium containing instructions for controlling the computer system can be utilized to implement the exemplary embodiments that are disclosed herein. The computer system may include at least one computer such as a microprocessor, digital signal processor, and associated peripheral electronic circuitry.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

APPENDIX
Other Factors
			Min	Min bytes
	Actual		packets in	in buffer a	Buffer		Max buffered
DS1 rate,	Payload		buffer at	average	spec		delay	Round-trip
bps	bytes	Frames	average delay	delay	bytes	starts at	variation ms	delay ms
1544000	724	1.5005	1	724	2172	1448	3.751	25.07
1544000	724	1.5005	2	1448	3620	2172	7.503	32.57
1544000	724	1.5005	3	2172	5068	2896	11.254	40.07
1544000	724	1.5005	4	2896	6516	3620	15.005	47.57
1544000	724	1.5005	5	3620	7964	4344	18.756	55.08
1544000	724	1.5005	6	4344	9412	5068	22.508	62.58
1544000	724	1.5005	7	5068	10860	5792	26.259	70.08
1544000	724	1.5005	8	5792	12308	6516	30.010	77.58
1544000	724	1.5005	9	6516	13756	7240	33.762	85.09
1544000	724	1.5005	10	7240	15204	7964	37.513	92.59
1544000	724	1.5005	11	7964	16652	8688	41.264	100.09
1544000	724	1.5005	12	8688	18100	9412	45.016	107.60
1544000	724	1.5005	13	9412	19548	10136	48.767	115.10
1544000	724	1.5005	14	10136	20996	10860	52.518	122.60
1544000	724	1.5005	15	10860	22444	11584	56.269	130.10
1544000	724	1.5005	16	11584	23892	12308	60.021	137.61
1544000	724	1.5005	17	12308	25340	13032	63.772	145.11
1544000	724	1.5005	18	13032	26788	13756	67.523	152.61
1544000	724	1.5005	19	13756	28236	14480	71.275	160.11
1544000	724	1.5005	20	14480	29684	15204	75.026	167.62
1544000	724	1.5005	21	15204	31132	15928	78.777	175.12
1544000	724	1.5005	22	15928	32580	16652	82.528	182.62
1544000	804	1.6663	1	804	2412	1608	4.166	26.98
1544000	804	1.6663	2	1608	4020	2412	8.332	35.31
1544000	804	1.6663	3	2412	5628	3216	12.497	43.64
1544000	804	1.6663	4	3216	7236	4020	16.663	51.98
1544000	804	1.6663	5	4020	8844	4824	20.829	60.31
1544000	804	1.6663	6	4824	10452	5628	24.995	68.64
1544000	804	1.6663	7	5628	12060	6432	29.161	76.97
1544000	804	1.6663	8	6432	13668	7236	33.326	85.30
1544000	804	1.6663	9	7236	15276	8040	37.492	93.63
1544000	804	1.6663	10	8040	16884	8844	41.658	101.97
1544000	804	1.6663	11	8844	18492	9648	45.824	110.30
1544000	804	1.6663	12	9648	20100	10452	49.990	118.63
1544000	804	1.6663	13	10452	21708	11256	54.155	126.96
1544000	804	1.6663	14	11256	23316	12060	58.321	135.29
1544000	804	1.6663	15	12060	24924	12864	62.487	143.62
1544000	804	1.6663	16	12864	26532	13668	66.653	151.95
1544000	804	1.6663	17	13668	28140	14472	70.819	160.29
1544000	804	1.6663	18	14472	29748	15276	74.984	168.62
1544000	804	1.6663	19	15276	31356	16080	79.150	176.95
1544000	804	1.6663	20	16080	32964	16884	83.316	185.28
1544000	1024	2.1223	1	1024	3072	2048	5.306	32.24
1544000	1024	2.1223	2	2048	5120	3072	10.611	42.86
1544000	1024	2.1223	3	3072	7168	4096	15.917	53.47
1544000	1024	2.1223	4	4096	9216	5120	21.223	64.08
1544000	1024	2.1223	5	5120	11264	6144	26.528	74.69
1544000	1024	2.1223	6	6144	13312	7168	31.834	85.30
1544000	1024	2.1223	7	7168	15360	8192	37.140	95.91
1544000	1024	2.1223	8	8192	17408	9216	42.446	106.52
1544000	1024	2.1223	9	9216	19456	10240	47.751	117.14
1544000	1024	2.1223	10	10240	21504	11264	53.057	127.75
1544000	1024	2.1223	11	11264	23552	12288	58.363	138.36
1544000	1024	2.1223	12	12288	25600	13312	63.668	148.97
1544000	1024	2.1223	13	13312	27648	14336	68.974	159.58
1544000	1024	2.1223	14	14336	29696	15360	74.280	170.19
1544000	1024	2.1223	15	15360	31744	16384	79.585	180.80
2048000	960	1.5000	1	960	2880	1920	3.750	25.82
2048000	960	1.5000	2	1920	4800	2880	7.500	33.32
2048000	960	1.5000	3	2880	6720	3840	11.250	40.82
2048000	960	1.5000	4	3840	8640	4800	15.000	48.32
2048000	960	1.5000	5	4800	10560	5760	18.750	55.82
2048000	960	1.5000	6	5760	12480	6720	22.500	63.32
2048000	960	1.5000	7	6720	14400	7680	26.250	70.82
2048000	960	1.5000	8	7680	16320	8640	30.000	78.32
2048000	960	1.5000	9	8640	18240	9600	33.750	85.82
2048000	960	1.5000	10	9600	20160	10560	37.500	93.32
2048000	960	1.5000	11	10560	22080	11520	41.250	100.82
2048000	960	1.5000	12	11520	24000	12480	45.000	108.32
2048000	960	1.5000	13	12480	25920	13440	48.750	115.82
2048000	960	1.5000	14	13440	27840	14400	52.500	123.32
2048000	960	1.5000	15	14400	29760	15360	56.250	130.82
2048000	960	1.5000	16	15360	31680	16320	60.000	138.32
2048000	1066	1.6656	1	1066	3198	2132	4.164	27.81
2048000	1066	1.6656	2	2132	5330	3198	8.328	36.14
2048000	1066	1.6656	3	3198	7462	4264	12.492	44.47
2048000	1066	1.6656	4	4264	9594	5330	16.656	52.80
2048000	1066	1.6656	5	5330	11726	6396	20.820	61.12
2048000	1066	1.6656	6	6396	13858	7462	24.984	69.45
2048000	1066	1.6656	7	7462	15990	8528	29.148	77.78
2048000	1066	1.6656	8	8528	18122	9594	33.313	86.11
2048000	1066	1.6656	9	9594	20254	10660	37.477	94.44
2048000	1066	1.6656	10	10660	22386	11726	41.641	102.77
2048000	1066	1.6656	11	11726	24518	12792	45.805	111.09
2048000	1066	1.6656	12	12792	26650	13858	49.969	119.42
2048000	1066	1.6656	13	13858	28782	14924	54.133	127.75
2048000	1066	1.6656	14	14924	30914	15990	58.297	136.08

Claims

1. A transmitter sending a data packet to a receiver through an Ethernet system, comprising: an input data interface obtaining an input data stream from a data source; a modeling module constructing a modeled jitter buffer modeling a receiver jitter buffer located at the receiver; and a packetizing buffer for: collecting data bits from the input data stream to form the data packet; inserting a buffer pointer into the data packet, the buffer pointer being determined from the modeled jitter buffer; and sending the data packet through the Ethernet system.

2. The transmitter of claim 1, the packetizing buffer repeating a data bit that is contained in the data packet in another data packet for supporting forward error correction (FEC).

3. The transmitter of claim 1, the modeling module determining statistical information descriptive of traffic performance in the Ethernet system and incorporating the statistical information into the modeled jitter buffer.

4. The transmitter of claim 1, the modeling module processing the statistical information to obtain a link delay variation of the Ethernet system.

5. The transmitter of claim 1, the data stream containing DS1 data.

6. The transmitter of claim 1, further comprising: a clock recovery module recovering clocking information from a signal; and the input data interface obtaining the input data stream in accordance with the clocking information;

7. The transmitter of claim 1, the input data interface multiplexing the input data stream with another input data stream from another data source.

8. The transmitter of claim 1, the modeling module determining a one-way packet delay from an inherent processing delay in the Ethernet system, a packetizing delay to assemble the data packet, a link delay through the Ethernet system, and a buffering delay for a variation in the Ethernet system.

9. A receiver receiving a data packet from a transmitter through an Ethernet system, comprising: an Ethernet interface module obtaining the data packet from the Ethernet system; a jitter buffer; a depacketizer reading a buffer pointer in the data packet, the buffer pointer being indicative of a modeled jitter, and placing the data packet into a position within the jitter buffer in accordance with the buffer pointer; and an output data interface extracting data bits from the jitter buffer to form an output data stream.

10. The receiver of claim 9, further comprising: a read pointer register identifying selected data bits to be included in the output data stream.

11. The receiver of claim 9, further comprising: a level counter register indicating an amount of data that has been received since a system reset.

12. The receiver of claim 9, further comprising: a jitter buffer size register indicting a size of the jitter buffer.

13. The receiver of claim 9, the depacketizer processing a repeated data bit in another data packet when a data bit is determined to be in error.

14. A method for communicating a data packet through an Ethernet system, comprising: (a) modeling, by a transmitter, a modeled jitter buffer modeling a receiver jitter buffer located at a receiver; (b) collecting data bits from an input data stream to form the data packet; (c) determining a buffer pointer from the modeled jitter buffer; (d) inserting the buffer pointer into the data packet; (e) sending the data packet through the Ethernet system to the receiver; (f) receiving, by the receiver, the data packet from the Ethernet system; (g) placing the data packet into the receiver jitter buffer in accordance with the buffer pointer, the buffer pointer being indicative of a position within the receiver jitter buffer; and (h) extracting received data bits from the receiver jitter buffer to form an output data stream.

15. The method of claim 14, (a) comprising: (a)(i) determining statistical information descriptive of traffic performance in the Ethernet system; and (a)(ii) incorporating the statistical information into the modeled jitter buffer.

16. The method of claim 14, (a) further comprising: (a)(iii) obtaining a link delay variation of the Ethernet system from the statistical information.

17. The method of claim 14, further comprising: (i) repeating a data bit that is contained in the data packet in another data packet for supporting forward error correction (FEC).

18. The method of claim 14, further comprising: (i) recovering clocking information from a signal; and (b)(i) obtaining the data bits from the input data stream to form the data packet in accordance with the clocking information.

19. The method of claim 14, the input data stream containing DS1 data.

20. The method of claim 14, further comprising: (i) managing the Ethernet system to allocate sufficient bandwidth for time division multiplex (TDM) traffic.