Claims
- 1. A circuit for improving calculation distribution in a pipelined multiplication circuit, the multiplication circuit producing a plurality of intermediate sums from a plurality of partial products generated from a first number and a second number to be multiplied together, with a sum of the plurality of partial products producing a value representative of a product of the first and second number, the circuit comprising:
- a first adding circuit for stepwise addition of a plurality of partial products disposed in columns to calculate a plurality of intermediate sums;
- a second adding circuit, having a first part, coupled to said first adding circuit, for forming a bit-area of a final product from a low-order group of said plurality of intermediate sums and a carry out of said bit-area, and a second part for forming a final product of the first and the second number from said plurality of intermediate sums; and
- a storing circuit coupled to said first and said second adding circuits, for receiving said bit-area and said carry-out from said first part of said second adding circuit and a high-order group of said plurality of intermediate sums from said first adding circuit, said high-order group not including intermediate sums from said low-order group, and for providing said bit-area, said carry-out and said high-order group to said second part of said second adding circuit.
- 2. The circuit as set forth in claim 1, wherein a pipeline processing is carried out with said first adding circuit and said second adding circuit.
- 3. The circuit as set forth in claim 1, wherein said first and second adding circuits comprise a secondary Booth's multiplication circuit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
63-261914 |
Oct 1988 |
JPX |
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Parent Case Info
This is a continuation of application Ser. No. 07/302,719, filed Jan. 27, 1989, now abandoned.
US Referenced Citations (4)
Foreign Referenced Citations (1)
Number |
Date |
Country |
58-31449 |
Feb 1983 |
JPX |
Non-Patent Literature Citations (1)
Entry |
S. Waser et al., "Real Time Processing Gains Ground with Fast Digital Multiplier", Electronics, Sep. 29, 1977, pp. 93-99. |
Continuations (1)
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Number |
Date |
Country |
Parent |
302719 |
Jan 1989 |
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