Claims
- 1. A processing system comprising:
- plural processing nodes, each node comprising a node memory having a portion of which constitutes a shared store, and a data write means for writing data to the node memory;
- data reflecting means for reflecting data written by a first data write means of a first node to the shared store of said first node and writing said data to other shared stores of other nodes independently of the data write means of all said nodes;
- a memory mapped input/output; and
- a random access memory coupled to said data reflecting means and said memory mapped input/output and storing the memory mapped input/output data.
- 2. The processing system of claim 1 further comprising:
- dedicated addresses contained within the shared store corresponding to locations in said random access memory.
- 3. The processing system of claim 2, wherein said random access memory is adapted to write data within a predetermined address range of each said shared store.
- 4. The processing system of claim 1, wherein said data reflecting means includes a data link having a bus and a bus logic control for granting data access to the bus for transmitting said data to said other shared stores.
- 5. The processing system of claim 4 further comprising:
- a data communication means for communicating data between said plurality of nodes in addition to said data reflecting means.
- 6. The processing system of claim 1, wherein said random access memory includes means for mapping data from said memory mapped input/output to the shared store of each node independently of the data write means of all said nodes.
- 7. The processing system of claim 1, wherein each processing node comprises:
- a detecting means for detecting input and output requests to the node memory.
- 8. The processing system of claim 1, wherein each node further comprises:
- comparing means associated with the shared store for determining if data has an address within a predetermined address range; and
- queuing means adapted to only queue data that is determined to have an address within said predetermined address range and to transmit said queued data via said data reflecting means.
- 9. The processing system of claim 1 further comprising:
- a plurality of control means for detecting data written by the data write means to node memories, the shared store of each node memory being associated with a control means;
- each of said control means detecting data written to its associated shared store and transmitting same to all other of the plural processing nodes via the data reflecting means.
Priority Claims (1)
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8406322 |
Oct 1984 |
GBX |
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Parent Case Info
This is a Rule 60 Divisional of application Ser. No. 07/758,893, filed Sep. 11, 1991, now U.S. Pat. No. 5,255,369, which is a continuation of Ser. No. 07/642,457, filed Jan. 17, 1991, now U.S. Pat. No. 5,072,373, which is a continuation of Ser. No. 07/401,511, filed Aug. 30, 1989, now U.S. Pat. No. 4,991,079, which is a continuation of Ser. No. 06/710,229, filed Mar. 11, 1985, abandoned.
US Referenced Citations (34)
Foreign Referenced Citations (2)
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0092895 |
Nov 1983 |
EPX |
0251686 |
Jan 1988 |
EPX |
Non-Patent Literature Citations (4)
Entry |
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Dixon, R. C., "Group Address Structure for Network Service Nodes," IBM Technical Disclosure Bulletin, vol. 26, No. 3A, Aug. 1983, pp. 1198-1200. |
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Divisions (1)
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Date |
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Parent |
758893 |
Sep 1991 |
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Continuations (3)
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642457 |
Jan 1991 |
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Parent |
401511 |
Aug 1989 |
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Parent |
710229 |
Mar 1985 |
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