This invention relates to forwarding network packets between network domains.
Packets are routed through a series of router devices, each of which stores and forwards packets on its way from a source to a destination. For example, a packet may start out as an Internet packet, be forwarded over an ATM (asynchronous transfer mode path) and then back to Ethernet onto a corporate network to its final intended recipient. As the network passes through these network domains, various header encapsulations may be added to or removed from the packet. Some connections use point-to-point protocol (PPP) whereas others use multiprotocol label switching MPLS, layer to tunneling protocol LTTP, ATM and so forth.
Referring to
The hardware-based multithreaded processor 12 also includes a central controller 20 that assists in loading microcode control for other resources of the hardware-based multithreaded processor 12 and performs other general purpose computer type functions such as handling protocols, exceptions, extra support for packet processing where the microengines pass the packets off for more detailed processing such as in boundary conditions. In one embodiment, the processor 20 is a Strong Arm® based architecture. The general purpose microprocessor 20 has an operating system. Through the operating system the processor 20 can call functions to operate on microengines 22a–22f. The processor 20 can use any supported operating system preferably a real time operating system such as, MicrosoftNT real-time, VXWorks.
The hardware-based multithreaded processor 12 also includes a plurality of function microengines 22a–22f. Functional microengines (microengines) 22a–22f each maintain a plurality of program counters in hardware and states associated with the program counters. Effectively, a corresponding plurality of sets of threads can be simultaneously active on each of the microengines 22a–22f while only one is actually operating at any one time.
In one embodiment, there are six microengines 22a–22f as shown. Each microengines 22a–22f has capabilities for processing four hardware threads. The six microengines 22a–22f operate with shared resources including memory system 16 and bus interfaces 24 and 28. The memory system 16 includes a Synchronous Dynamic Random Access Memory (SDRAM) controller 26a and a Static Random Access Memory (SRAM) controller 26b. SDRAM memory 16a and SDRAM controller 26a are typically used for processing large volumes of data, e.g., processing of network payloads from network packets. The SRAM controller 26b and SRAM memory 16b are used in a networking implementation for low latency, fast access tasks, e.g., accessing look-up tables, memory for the core processor 20, and so forth.
The six microengines 22a–22f access either the SDRAM 16a or SRAM 16b based on characteristics of the data. Thus, low latency, low bandwidth data is stored in and fetched from SRAM, whereas higher bandwidth data for which latency is not as important, is stored in and fetched from SDRAM. The microengines 22a–22f can execute memory reference instructions to either the SDRAM controller 26a or SRAM controller 16b.
Advantages of hardware multithreading can be explained by SRAM or SDRAM memory accesses. As an example, an SRAM access requested by a Thread—0, from a microengine will cause the SRAM controller 26b to initiate an access to the SRAM memory 16b. The SRAM controller controls arbitration for the SRAM bus, accesses the SRAM 16b, fetches the data from the SRAM 16b, and returns data to a requesting microengine 22a–22b. During an SRAM access, if the microengine e.g., 22a had only a single thread that could operate, that microengine would be dormant until data was returned from the SRAM. By employing hardware context swapping within each of the microengines 22a–22f, the hardware context swapping enables other contexts with unique program counters to execute in that same microengine. Thus, another thread e.g., Thread—1 can function while the first thread, e.g., Thread—0, is awaiting the read data to return. During execution, Thread—1 may access the SDRAM memory 16a. While Thread—1 operates on the SDRAM unit, and Thread—0 is operating on the SRAM unit, a new thread, e.g., Thread—2 can now operate in the microengine 22a. Thread—2 can operate for a certain amount of time until it needs to access memory or perform some other long latency operation, such as making an access to a bus interface. Therefore, simultaneously, the processor 12 can have a bus operation, SRAM operation and SDRAM operation all being completed or operated upon by one microengine 22a and have one more thread available to process more work in the data path.
The hardware context swapping also synchronizes completion of tasks. For example, two threads could hit the same shared resource e.g., SRAM. Each one of these separate functional units, e.g., the FBUS interface 28, the SRAM controller 26a, and the SDRAM controller 26b, when they complete a requested task from one of the microengine thread contexts reports back a flag signaling completion of an operation. When the flag is received by the microengine, the microengine can determine which thread to turn on.
One example of an application for the hardware-based multithreaded processor 12 is as a network processor. As a network processor, the hardware-based multithreaded processor 12 interfaces to network devices such as a media access controller device e.g., a 10/100BaseT Octal MAC 13a or a Gigabit Ethernet device 13b. In general the network process can interface to any type of communication device or interface that receives/sends large amounts of data. Communication system 10 functioning in a networking application could receive a plurality of network packets from the devices 13a, 13b and process those packets in a parallel manner. With the hardware-based multithreaded processor 12, each network packet can be independently processed. Another example for use of processor 12 is a print engine for a postscript processor or as a processor for a storage subsystem, i.e., RAID disk storage. A further use is as a matching engine. In the securities industry for example, the advent of electronic trading requires the use of electronic matching engines to match orders between buyers and sellers. These and other parallel types of tasks can be accomplished on the system 10.
The processor 12 includes a bus interface 28 that couples the processor to the second bus 18. Bus interface 28 in one embodiment couples the processor 12 to the so-called FBUS 18 (FIFO bus). The FBUS interface 28 is responsible for controlling and interfacing the processor 12 to the FBUS 18. The FBUS 18 is a 64-bit wide FIFO bus, which is currently gaining acceptance as the best bus for Media Access Controller (MAC) devices.
The processor 12 includes a second interface e.g., a PCI bus interface 24 that couples other system components that reside on the PCI 14 bus to the processor 12. The PCI bus interface 24, provides a high speed data path 24a to memory 16 e.g., the SDRAM memory 16a. Through that path data can be moved quickly from the SDRAM 16a through the PCI bus 14, via direct memory access (DMA) transfers. Additionally, the PCI bus interface 24 supports target and master operations. Target operations are operations where slave devices on bus 14 access SDRAMs through reads and writes that are serviced as a slave to target operation. In master operations, the processor core 20 sends data directly to or receives data directly from the PCI interface 24.
Each of the functional units are coupled to one or more internal buses. The processor includes an AMBA bus that couples the processor core 20 to the memory controller 26a, 26c and to an AMBA translator 30 described below. The processor also includes a private bus 34 that couples the microengine units to SRAM controller 26b, AMBA translator 30 and FBUS interface 28. A memory bus 38 couples the memory controller 26a, 26b to the bus interfaces 24 and 28 and memory system 16 including flashrom 16c used for boot operations and so forth.
Referring to
If the memory subsystem 16 is flooded with memory requests that are independent in nature, the processor 12 can perform memory reference sorting. Memory reference sorting improves achievable memory bandwidth. Memory reference sorting, as described below, reduces dead time or a bubble that occurs with accesses to SRAM. With memory references to SRAM, switching current direction on signal lines between reads and writes produces a bubble or a dead time waiting for current to settle on conductors coupling the SRAM 16b to the SRAM controller 26b.
That is, the drivers that drive current on the bus need to settle out prior to changing states. Thus, repetitive cycles of a read followed by a write can degrade peak bandwidth. Memory reference sorting allows the processor 12 to organize references to memory such that long strings of reads can be followed by long strings of writes. This can be used to minimize dead time in the pipeline to effectively achieve closer to maximum available bandwidth. Reference sorting helps maintain parallel hardware context threads. On the SDRAM, reference sorting allows hiding of pre-charges from one bank to another bank. Specifically, if the memory system 16b is organized into an odd bank and an even bank, while the processor is operating on the odd bank, the memory controller can start precharging the even bank. Precharging is possible if memory references alternate between odd and even banks. By ordering memory references to alternate accesses to opposite banks, the processor 12 improves SDRAM bandwidth.
The FBUS interface 28 supports Transmit and Receive flags for each port that a MAC device supports, along with an Interrupt flag indicating when service is warranted. The FBUS interface 28 also includes a controller 28a that performs header processing of incoming packets from the FBUS 18. The controller 28a extracts the packet headers and performs a microprogrammable source/destination/protocol hashed lookup (used for address smoothing) in SRAM. If the hash does not successfully resolve, the packet header is sent to the processor core 20 for additional processing. The FBUS interface 28 supports the following internal data transactions:
The FBUS 18 is a standard industry bus and includes a data bus, e.g., 64 bits wide and sideband control for address and read/write control. The FBUS interface 28 provides the ability to input large amounts of data using a series of input and output FIFO's 29a–29b. From the FIFOs 29a–29b, the microengines 22a–22f fetch data from or command the SDRAM controller 26a to move data from a receive FIFO in which data has come from a device on bus 18, into the FBUS interface 28. The data can be sent through memory controller 26a to SDRAM memory 16a, via a direct memory access. Similarly, the microengines can move data from the SDRAM 26a to interface 28, out to FBUS 18, via the FBUS interface 28.
Data functions are distributed amongst the microengines. Connectivity to the SRAM 26a, SDRAM 26b and FBUS 28 is via command requests. A command request can be a memory request or a FBUS request. For example, a command request can move data from a register located in a microengine 22a to a shared resource, e.g., an SDRAM location, SRAM location, flash memory or some MAC address. The commands are sent out to each of the functional units and the shared resources. However, the shared resources do not need to maintain local buffering of the data. Rather, the shared resources access distributed data located inside of the microengines. This enables microengines 22a–22f, to have local access to data rather than arbitrating for access on a bus and risk contention for the bus. With this feature, there is a 0 cycle stall for waiting for data internal to the microengines 22a–22f.
The data buses, e.g., AMBA bus 30, SRAM bus 34 and SDRAM bus 38 coupling these shared resources, e.g., memory controllers 26a and 26b are of sufficient bandwidth such that there are no internal bottlenecks. Thus, in order to avoid bottlenecks, the processor 12 has an bandwidth requirement where each of the functional units is provided with at least twice the maximum bandwidth of the internal buses. As an example, the SDRAM can run a 64 bit wide bus at 83 MHz. The SRAM data bus could have separate read and write buses, e.g., could be a read bus of 32 bits wide running at 166 MHz and a write bus of 32 bits wide at 166 MHz. That is, in essence, 64 bits running at 166 MHz which is effectively twice the bandwidth of the SDRAM.
The core processor 20 also can access the shared resources. The core processor 20 has a direct communication to the SDRAM controller 26a to the bus interface 24 and to SRAM controller 26b via bus 32. However, to access the microengines 22a–22f and transfer registers located at any of the microengines 22a–22f, the core processor 20 access the microengines 22a–22f via the AMBA Translator 30 over bus 34. The AMBA translator 30 can physically reside in the FBUS interface 28, but logically is distinct. The AMBA Translator 30 performs an address translation between FBUS microengine transfer register locations and core processor addresses (i.e., AMBA bus) so that the core processor 20 can access registers belonging to the microengines 22a–22c.
The processor core 20 includes a RISC core 50 implemented in a five stage pipeline performing a single cycle shift of one operand or two operands in a single cycle, provides multiplication support and 32 bit barrel shift support. This RISC core 50 is a standard Strong Arm® architecture but it is implemented with a five stage pipeline for performance reasons. The processor core 20 also includes a 16 kilobyte instruction cache 52, an 8 kilobyte data cache 54 and a prefetch stream buffer 56. The core processor 20 performs arithmetic operations in parallel with memory writes and instruction fetches. The core processor 20 interfaces with other functional units via the ARM defined AMBA bus. The AMBA bus is a 32-bit bi-directional bus 32.
Referring to
The network stack 72 and the application run in the processor 20 that controls the microengines, or another processor coupled to the PCI bus. The paths of receive, transmit and data forwarding represent the transport of the packets through the processor 12. The management control, signaling, and the network stack 72 usually are not involved in data forwarding. Essentially, the processor 20 receives and transmits. The processor 20 generates new packets that are transmitted over the network. The processor 20 can be involved in data forwarding in the exceptional case. This would involve very unusual packets, which may need special handling and complex processing.
For data forwarding processes, the microengines 22a–22f are used. In some instances, data forwarding may occur at the general purpose processor 20 level. The signals Init is programmer's interface for initialization of microengine code. The signal Fini is used for termination (to put control info in a known state). The microengines 22a–22f provide fast, store and forward capabilities. The engines use a multilayer generic look-up process that performs validation, classification, policing and filtering using parallel hardware supported threads of the process. Exceptions and control packets are passed to the processor 20 for processing at the network stack 72. A ternary network stack (not shown) can be located off-chip at a host via the PCI port or device port. This can be used to off-load the processor 20 or centralized management and control for one place. In some embodiments, the microengine is a compact RISC processor and can have limited instruction space. For this reason and for other reasons, it is desirable to reduce instruction code size when running multiple protocols. The network processor 12 implements a generic forwarding process that can be used to handle various protocol types (both existing and future types) without exceeding instruction storage limits.
Referring now to
Once the tables 90 are populated with forwarding information in a generally conventional manner, packet data forwarding processors can receive packets, perform table look-ups to obtain information and convert packets as required by the table entry. The control management process sets up the tables 90 with a common format for the purpose of decapsulation and encapsulation.
Referring now to
The flags get set or cleared by the management process. Signaling and setting up connections are part of the network system that will determine that a certain path through the network requires a change of the header. There can be many reasons why a header can change. Usually a header change is used when the protocol changes from one network domain to another.
Referring now to
If, however, the process did not determine that the decap and encap flags were set (116, above), it would determine 130 if the encap flag or the decap flag were set 132. If the encap flag was set, it will subtract 120 the encap flag byte count from the start offset and prepend the encap bytes to the packet. On the other hand, if the decap flag was only set 132, the process will add 134 a decap byte count to the buffer offset and, in any event, will check the next table 112. When the process determines that it is at the end of checking the tables, it will then classify and forward 136 the packet in a conventional manner. That is, the “no” condition indicates that the process can classify and forward. Forwarding the header can have the microengine take the header and send it to the processor 20 or elsewhere, so that it can get reassembled with the payload. Forwarding the header could also involve forwarding the packet, etc.
Referring now to
A process 140 to determine this offset is shown in
A typical use of a decap to layer bit is to specify a decapsulation up to the layer 3 IP header. If the packet encapsulation is a multiprotocol over an ATM network such as the RFC 1483 standard, the layer 2 header length is determined by parsing the layer to header itself using the RFC 1483 length rules. However, if the packet encapsulation is classical IP the layer 2 length is determined by following the classical IP layer length rules. The packet encapsulation may be known by the port type it came in on from the prepended custom header from that port or may be obtained from the first look-up table in the current encap field.
Rather that each network protocol defining a separate protocol conversion this technique provides a generic approach. The approach saves code space and software development time-to-market. In an alternative embodiment, this technique can be implemented as a software library routine, e.g., a generic software building block for decapsulation/encapsulation, where customers can insert their proprietary header encapsulation and a customer's vendor need not get involved with customer's proprietary protocol designs.
A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.
Number | Name | Date | Kind |
---|---|---|---|
3373408 | Ling | Mar 1968 | A |
3478322 | Evans | Nov 1969 | A |
3736566 | Anderson et al. | May 1973 | A |
3792441 | Wymore et al. | Feb 1974 | A |
3940745 | Sajeva | Feb 1976 | A |
4016548 | Law et al. | Apr 1977 | A |
4032899 | Jenny et al. | Jun 1977 | A |
4075691 | Davis et al. | Feb 1978 | A |
4130890 | Adam | Dec 1978 | A |
4400770 | Chan et al. | Aug 1983 | A |
4514807 | Nogi | Apr 1985 | A |
4523272 | Fukunaga et al. | Jun 1985 | A |
4709347 | Kirk | Nov 1987 | A |
4745544 | Renner et al. | May 1988 | A |
4788640 | Hansen | Nov 1988 | A |
4831358 | Ferrio et al. | May 1989 | A |
4866664 | Burkhardt, Jr. et al. | Sep 1989 | A |
4890218 | Bram | Dec 1989 | A |
4890222 | Kirk | Dec 1989 | A |
4991112 | Callemyn | Feb 1991 | A |
5115507 | Callemyn | May 1992 | A |
5140685 | Sipple et al. | Aug 1992 | A |
5142683 | Burkhardt, Jr. et al. | Aug 1992 | A |
5155831 | Emma et al. | Oct 1992 | A |
5155854 | Flynn et al. | Oct 1992 | A |
5168555 | Byers et al. | Dec 1992 | A |
5173897 | Schrodi et al. | Dec 1992 | A |
5251205 | Callon et al. | Oct 1993 | A |
5255239 | Taborn et al. | Oct 1993 | A |
5263169 | Genusov et al. | Nov 1993 | A |
5347648 | Stamm et al. | Sep 1994 | A |
5367678 | Lee et al. | Nov 1994 | A |
5390329 | Gaertner et al. | Feb 1995 | A |
5392391 | Caulk, Jr. et al. | Feb 1995 | A |
5392411 | Ozaki | Feb 1995 | A |
5392412 | McKenna | Feb 1995 | A |
5404464 | Bennett | Apr 1995 | A |
5404469 | Chung | Apr 1995 | A |
5404482 | Stamm et al. | Apr 1995 | A |
5404484 | Schlansker et al. | Apr 1995 | A |
5432918 | Stamm | Jul 1995 | A |
5448702 | Garcia, Jr. et al. | Sep 1995 | A |
5450351 | Heddes | Sep 1995 | A |
5452437 | Richey et al. | Sep 1995 | A |
5459842 | Begun et al. | Oct 1995 | A |
5459843 | Davis | Oct 1995 | A |
5463625 | Yasrebi | Oct 1995 | A |
5467452 | Blum et al. | Nov 1995 | A |
5485455 | Dobbins et al. | Jan 1996 | A |
5515296 | Agarwal | May 1996 | A |
5517648 | Bertone et al. | May 1996 | A |
5542070 | LeBlanc et al. | Jul 1996 | A |
5542088 | Jennings, Jr. et al. | Jul 1996 | A |
5544236 | Andruska et al. | Aug 1996 | A |
5550816 | Hardwick et al. | Aug 1996 | A |
5557766 | Takiguchi et al. | Sep 1996 | A |
5568476 | Sherer et al. | Oct 1996 | A |
5568617 | Kametani | Oct 1996 | A |
5574922 | James | Nov 1996 | A |
5581729 | Nistala et al. | Dec 1996 | A |
5592622 | Isfeld et al. | Jan 1997 | A |
5613071 | Rankin et al. | Mar 1997 | A |
5613136 | Casavant et al. | Mar 1997 | A |
5623489 | Cotton et al. | Apr 1997 | A |
5627829 | Gleeson et al. | May 1997 | A |
5630130 | Perotto et al. | May 1997 | A |
5630641 | Mori et al. | May 1997 | A |
5644623 | Gutledge | Jul 1997 | A |
5649157 | Williams | Jul 1997 | A |
5651002 | Van Seters et al. | Jul 1997 | A |
5659687 | Kim et al. | Aug 1997 | A |
5680641 | Sidman | Oct 1997 | A |
5689566 | Nguyen | Nov 1997 | A |
5699537 | Sharangpani et al. | Dec 1997 | A |
5701434 | Nakagawa | Dec 1997 | A |
5717898 | Kagan et al. | Feb 1998 | A |
5721870 | Matsumoto | Feb 1998 | A |
5740402 | Bratt et al. | Apr 1998 | A |
5742587 | Zornig et al. | Apr 1998 | A |
5742782 | Ito et al. | Apr 1998 | A |
5742822 | Motomura | Apr 1998 | A |
5745913 | Pattin et al. | Apr 1998 | A |
5751987 | Mahant-Shetti et al. | May 1998 | A |
5754764 | Davis et al. | May 1998 | A |
5761507 | Govett | Jun 1998 | A |
5761522 | Hisanaga et al. | Jun 1998 | A |
5764915 | Heimsoth et al. | Jun 1998 | A |
5768528 | Stumm | Jun 1998 | A |
5781551 | Born | Jul 1998 | A |
5781774 | Krick | Jul 1998 | A |
5784649 | Begur | Jul 1998 | A |
5784712 | Byers et al. | Jul 1998 | A |
5796413 | Shipp et al. | Aug 1998 | A |
5797043 | Lewis et al. | Aug 1998 | A |
5809235 | Sharma et al. | Sep 1998 | A |
5809237 | Watts et al. | Sep 1998 | A |
5809530 | Samra et al. | Sep 1998 | A |
5812868 | Moyer et al. | Sep 1998 | A |
5828746 | Ardon | Oct 1998 | A |
5828863 | Barrett et al. | Oct 1998 | A |
5832215 | Kato et al. | Nov 1998 | A |
5835755 | Stellwagen, Jr. | Nov 1998 | A |
5850530 | Chen et al. | Dec 1998 | A |
5854922 | Gravenstein et al. | Dec 1998 | A |
5860158 | Pai et al. | Jan 1999 | A |
5886992 | Raatikainen et al. | Mar 1999 | A |
5887134 | Ebrahim | Mar 1999 | A |
5890208 | Kwon | Mar 1999 | A |
5892979 | Shiraki et al. | Apr 1999 | A |
5898701 | Johnson | Apr 1999 | A |
5905876 | Pawlowski et al. | May 1999 | A |
5905889 | Wilhelm, Jr. | May 1999 | A |
5915123 | Mirsky et al. | Jun 1999 | A |
5918235 | Kirshenbaum et al. | Jun 1999 | A |
5928736 | Parekh | Jul 1999 | A |
5933627 | Parady | Aug 1999 | A |
5937187 | Kosche et al. | Aug 1999 | A |
5938736 | Muller et al. | Aug 1999 | A |
5940612 | Brady et al. | Aug 1999 | A |
5940866 | Chisholm et al. | Aug 1999 | A |
5946487 | Dangelo | Aug 1999 | A |
5948081 | Foster | Sep 1999 | A |
5958031 | Kime | Sep 1999 | A |
5961628 | Nguyen et al. | Oct 1999 | A |
5970013 | Fischer et al. | Oct 1999 | A |
5978838 | Mohamed et al. | Nov 1999 | A |
5983274 | Hyder et al. | Nov 1999 | A |
5995513 | Harrand et al. | Nov 1999 | A |
6012151 | Mano | Jan 2000 | A |
6014729 | Lannan et al. | Jan 2000 | A |
6023742 | Ebeling et al. | Feb 2000 | A |
6032190 | Bremer et al. | Feb 2000 | A |
6058168 | Braband | May 2000 | A |
6061710 | Eickemeyer et al. | May 2000 | A |
6067300 | Baumert et al. | May 2000 | A |
6067585 | Hoang | May 2000 | A |
6070231 | Ottinger | May 2000 | A |
6072781 | Feeney et al. | Jun 2000 | A |
6073215 | Snyder | Jun 2000 | A |
6079008 | Clery, III | Jun 2000 | A |
6085215 | Ramakrishnan et al. | Jul 2000 | A |
6085294 | Van Doren et al. | Jul 2000 | A |
6092127 | Tausheck | Jul 2000 | A |
6092158 | Harriman et al. | Jul 2000 | A |
6111886 | Stewart | Aug 2000 | A |
6112016 | MacWilliams et al. | Aug 2000 | A |
6134665 | Klein et al. | Oct 2000 | A |
6141677 | Hanif et al. | Oct 2000 | A |
6141689 | Yasrebi | Oct 2000 | A |
6141765 | Sherman | Oct 2000 | A |
6144669 | Williams et al. | Nov 2000 | A |
6145054 | Mehrotra et al. | Nov 2000 | A |
6157955 | Narad et al. | Dec 2000 | A |
6160562 | Chin et al. | Dec 2000 | A |
6170051 | Dowling | Jan 2001 | B1 |
6182177 | Harriman | Jan 2001 | B1 |
6195676 | Spix et al. | Feb 2001 | B1 |
6199133 | Schnell | Mar 2001 | B1 |
6201807 | Prasanna | Mar 2001 | B1 |
6212542 | Kahle et al. | Apr 2001 | B1 |
6212611 | Nizar et al. | Apr 2001 | B1 |
6216220 | Hwang | Apr 2001 | B1 |
6223207 | Lucovsky et al. | Apr 2001 | B1 |
6223238 | Meyer et al. | Apr 2001 | B1 |
6223274 | Catthoor et al. | Apr 2001 | B1 |
6223279 | Nishimura et al. | Apr 2001 | B1 |
6247025 | Bacon | Jun 2001 | B1 |
6256713 | Audityan et al. | Jul 2001 | B1 |
6272520 | Sharangpani et al. | Aug 2001 | B1 |
6272616 | Fernando et al. | Aug 2001 | B1 |
6275505 | O'Loughlin et al. | Aug 2001 | B1 |
6279113 | Vaidya | Aug 2001 | B1 |
6282169 | Kiremidjian | Aug 2001 | B1 |
6286083 | Chin et al. | Sep 2001 | B1 |
6289011 | Seo et al. | Sep 2001 | B1 |
6295600 | Parady et al. | Sep 2001 | B1 |
6298370 | Tang et al. | Oct 2001 | B1 |
6307789 | Wolrich et al. | Oct 2001 | B1 |
6311261 | Chamdani et al. | Oct 2001 | B1 |
6324624 | Wolrich et al. | Nov 2001 | B1 |
6338078 | Chang et al. | Jan 2002 | B1 |
6345334 | Nakagawa et al. | Feb 2002 | B1 |
6347344 | Baker et al. | Feb 2002 | B1 |
6356692 | Ido et al. | Mar 2002 | B1 |
6360262 | Guenthner et al. | Mar 2002 | B1 |
6366998 | Mohamed | Apr 2002 | B1 |
6373848 | Allison et al. | Apr 2002 | B1 |
6389449 | Nemirovsky et al. | May 2002 | B1 |
6393026 | Irwin | May 2002 | B1 |
6393483 | Latif et al. | May 2002 | B1 |
6415338 | Habot | Jul 2002 | B1 |
6424659 | Viswanadham et al. | Jul 2002 | B1 |
6426940 | Seo et al. | Jul 2002 | B1 |
6427196 | Adiletta et al. | Jul 2002 | B1 |
6430626 | Witkowski et al. | Aug 2002 | B1 |
6434145 | Opsasnick et al. | Aug 2002 | B1 |
6453404 | Bereznyi et al. | Sep 2002 | B1 |
6463072 | Wolrich et al. | Oct 2002 | B1 |
6463480 | Kikuchi et al. | Oct 2002 | B1 |
6463527 | Vishkin | Oct 2002 | B1 |
6466898 | Chan | Oct 2002 | B1 |
6477562 | Nemirovsky et al. | Nov 2002 | B1 |
6484224 | Robins et al. | Nov 2002 | B1 |
6526451 | Kasper et al. | Feb 2003 | B1 |
6529983 | Marshall et al. | Mar 2003 | B1 |
6532509 | Wolrich et al. | Mar 2003 | B1 |
6535878 | Guedalia et al. | Mar 2003 | B1 |
6552826 | Adler et al. | Apr 2003 | B1 |
6553406 | Berger et al. | Apr 2003 | B1 |
6560667 | Wolrich et al. | May 2003 | B1 |
6570850 | Gutierrez et al. | May 2003 | B1 |
6577542 | Wolrich et al. | Jun 2003 | B1 |
6584522 | Wolrich et al. | Jun 2003 | B1 |
6587906 | Wolrich et al. | Jul 2003 | B1 |
6604125 | Belkin | Aug 2003 | B1 |
6606704 | Adiletta et al. | Aug 2003 | B1 |
6625654 | Wolrich et al. | Sep 2003 | B1 |
6629236 | Aipperspach et al. | Sep 2003 | B1 |
6631422 | Althaus et al. | Oct 2003 | B1 |
6631430 | Wolrich et al. | Oct 2003 | B1 |
6631462 | Wolrich et al. | Oct 2003 | B1 |
6661794 | Wolrich et al. | Dec 2003 | B1 |
6667920 | Wolrich et al. | Dec 2003 | B1 |
6668317 | Bernstein et al. | Dec 2003 | B1 |
6671827 | Guilford et al. | Dec 2003 | B1 |
6675190 | Schabernack et al. | Jan 2004 | B1 |
6678746 | Russell et al. | Jan 2004 | B1 |
6681300 | Wolrich et al. | Jan 2004 | B1 |
6694380 | Wolrich et al. | Feb 2004 | B1 |
6792488 | Wolrich et al. | Sep 2004 | B1 |
6826615 | Barrall et al. | Nov 2004 | B1 |
6876561 | Wolrich et al. | Apr 2005 | B1 |
6895457 | Wolrich et al. | May 2005 | B1 |
6925637 | Thomas et al. | Aug 2005 | B1 |
6952824 | Hooper et al. | Oct 2005 | B1 |
6976095 | Wolrich et al. | Dec 2005 | B1 |
6983350 | Adiletta et al. | Jan 2006 | B1 |
20040039895 | Wolrich et al. | Feb 2004 | A1 |
20040054880 | Bernstein et al. | Mar 2004 | A1 |
20040071152 | Wolrich et al. | Apr 2004 | A1 |
20040073728 | Wolrich et al. | Apr 2004 | A1 |
20040073778 | Adiletta et al. | Apr 2004 | A1 |
20040098496 | Wolrich et al. | May 2004 | A1 |
20040109369 | Wolrich et al. | Jun 2004 | A1 |
20040148382 | Narad et al. | Jul 2004 | A1 |
Number | Date | Country |
---|---|---|
0 379 709 | Aug 1990 | EP |
0 464 715 | Jan 1992 | EP |
0 633 678 | Jan 1995 | EP |
0 745 933 | Dec 1996 | EP |
0 809 180 | Nov 1997 | EP |
0 959 602 | Nov 1999 | EP |
59111533 | Jun 1984 | JP |
WO 9415287 | Jul 1994 | WO |
WO 9738372 | Oct 1997 | WO |
WO 9820647 | May 1998 | WO |
WO 0116718 | Mar 2001 | WO |
WO 0116769 | Mar 2001 | WO |
WO 0116770 | Mar 2001 | WO |
WO 0116782 | Mar 2001 | WO |
WO 0117179 | Mar 2001 | WO |
WO 0148596 | Jul 2001 | WO |
WO 0148606 | Jul 2001 | WO |
WO 0148619 | Jul 2001 | WO |
WO 0150247 | Jul 2001 | WO |
WO 0150679 | Jul 2001 | WO |
WO 03030461 | Apr 2003 | WO |
Number | Date | Country | |
---|---|---|---|
20030067934 A1 | Apr 2003 | US |