Claims
- 1. A memory bank having words that are addressable by addresses and having multiple sections, the memory bank comprising:
a plurality of sections, each section representing a subdivision of a word of memory, each section having a row enable line for each row of the memory and a column enable line for each column of the memory for enabling access to a subdivision of a word of memory, each section having a section enable line for enabling access to that section; for each row of each section, row enabler logic that enables the row enable line for that row of that section only when the section enable line for that section is enabled; and for each section, column enabler logic that enables a column enable line for that section only when the section enable line for that section is enabled.
- 2. The memory bank of claim 1 wherein the memory bank is part of a multiport memory device and wherein the section enable lines are enabled based on the accessing port.
- 3. The memory bank of claim 1 wherein different rows of different sections can be simultaneously accessed to satisfy different memory access requests.
- 4. The memory bank of claim 1 wherein row and column address enable signals are buffered to accommodate row and column latencies.
- 5. The memory bank of claim 1 including configuration information storage for selectively enabling sections.
- 6. The memory bank of claim 5 wherein the memory bank is part of a multiport memory device and the selective enabling of sections is on a port-by-port basis.
- 7. A memory bank having words that are addressable by addresses and having multiple sections, the memory bank comprising:
a plurality of sections, each section representing a subdivision of a word of memory, each word of memory being accessible via an address, each section being selectively enabled so that only a portion of a word corresponding to enabled sections is accessible so that sections that are not enabled use less power than sections that are enabled.
- 8. The memory bank of claim 7 wherein the address is divided into a row portion and a column portion and the memory bank includes a row decoder and a column decoder to selectively accesses a word of the memory bank.
- 9. The memory bank of claim 8 wherein output of the row decoder and output of the column decoder only drive sections that are enabled.
- 10. The memory bank of claim 9 wherein the outputs are buffered to accommodate row and column latencies.
- 11. The memory bank of claim 7 wherein the memory bank is part of a multiport memory device and wherein the section enable lines are enabled based on the accessing port.
- 12. The memory bank of claim 7 wherein different rows of different sections can be simultaneously accessed to satisfy different memory access requests.
- 13. The memory bank of claim 7 including configuration information storage for selectively enabling sections.
- 14. The memory bank of claim 13 wherein the memory bank is part of a multiport memory device and the selective enabling of sections is on a port-by-port basis.
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of U.S. Provisional Application No. 60/252,724 entitled “METHOD AND APPARATUS FOR STORAGE I/O WITH FULL-DUPLEX ONE-TIME BLOCK I/O TRANSFER AND ADAPTIVE PAYLOAD SIZING,” filed Nov. 22, 2000, and is related to U.S. patent application Ser. No. ______, entitled “METHOD AND SYSTEM FOR PLESIOSYNCHRONOUS COMMUNICATIONS WITH NULL INSERTION AND REMOVAL” (Attorney Docket No. 371798002US); U.S. patent application Ser. No. ______, entitled “METHOD AND SYSTEM FOR TRANSITION-CONTROLLED SELECTIVE BLOCK INVERSION COMMUNICATIONS” (Attorney Docket No. 371798007US); U.S. patent application Ser. No. ______ entitled “COMMUNICATIONS ARCHITECTURE FOR STORAGE-BASED DEVICES” (Attorney Docket No. 371798008US1); U.S. patent application Ser. No. ______ entitled “METHOD AND SYSTEM FOR PACKET ORDERING BASED ON PACKET TYPE” (Attorney Docket No. 371798013US); U.S. patent application Ser. No. ______ entitled “METHOD AND SYSTEM FOR HOST HANDLING OF COMMUNICATIONS ERRORS” (Attorney Docket No. 371798014US); U.S. patent application Ser. No. ______ entitled “METHOD AND SYSTEM FOR DYNAMIC SEGMENTATION OF COMMUNICATIONS PACKETS” (Attorney Docket No. 371798015US); U.S. patent application Ser. No. ______ entitled “METHOD AND SYSTEM FOR ASYMMETRIC PACKET ORDERING BETWEEN COMMUNICATIONS DEVICES” (Attorney Docket No. 371798016US); U.S. patent application Ser. No. ______ entitled “METHOD AND SYSTEM FOR COMMUNICATING CONTROL INFORMATION VIA OUT-OF-BAND SYMBOLS” (Attorney Docket No. 371798017US); U.S. patent application Ser. No. ______ entitled “METHOD AND SYSTEM FOR INTEGRATING PACKET TYPE INFORMATION WITH SYNCHRONIZATION SYMBOLS” (Attorney Docket No. 371798018US); U.S. Patent application Ser. No. ______ entitled “METHOD AND SYSTEM FOR NESTING OF COMMUNICATIONS PACKETS” (Attorney Docket No. 371798019US); U.S. patent application Ser. No. ______ entitled “COMMUNICATIONS ARCHITECTURE FOR MEMORY-BASED DEVICES” (Attorney Docket No. 371798012US); U.S. patent application Ser. No. ______ entitled “METHOD AND SYSTEM FOR DC-BALANCING AT THE PHYSICAL LAYER” (Attorney Docket No. 371798020US); and U.S. Patent application Ser. No. ______ entitled “MULTISECTION MEMORY BANK SYSTEM” (Attorney Docket No. 371798021US, which are all hereby incorporated by reference in their entirety.
Provisional Applications (1)
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Number |
Date |
Country |
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60252724 |
Nov 2000 |
US |