Claims
- 1. A system, comprising:
a processor having a programmable fuse block programmed with one or more configuration signals each having a first configuration state and at least one secondary configuration state; logic coupled to the processor to determine the first configuration state and to generate a first output specified by the first configuration state, and to determine any secondary configuration states and to generate any secondary outputs specified by the secondary configuration states.
- 2. The system of claim 1, wherein the first configuration state specifies a first voltage and any secondary configuration states specify a secondary voltage.
- 3. The system of claim 1, wherein the first configuration state specifies a first frequency and any second configuration states specify a secondary frequency.
- 4. The system of claim 1, wherein the first and any secondary outputs are primary and secondary voltages, respectively.
- 5. The system of claim 1, wherein the first and any secondary outputs are first and secondary frequencies, respectively.
- 6. A system, comprising:
logic to generate first and secondary outputs; a processor coupled to the logic having a programmable fuse block programmed with one or more configuration signals each having a first configuration state and at least one secondary configuration state, wherein the first set of configuration states specifies a first set of outputs and any secondary sets of configuration states specify secondary outputs; a control signal value coupled between the logic and the processor to control whether the logic generates the first outputs or the secondary outputs.
- 7. The system of claim 6, wherein the first set of configuration states specifies a first voltage and a first frequency and any secondary configuration states specify a secondary voltage and a secondary frequency.
- 8. The system of claim 6, wherein the first set of configuration states specifies a first frequency and a first voltage and any secondary configuration states specify a secondary frequency and a secondary voltage.
- 9. The system of claim 6, wherein the first and secondary outputs are first and secondary voltages.
- 10. The system of claim 6, wherein the first and secondary outputs are first and secondary frequencies.
- 11. A processor, comprising:
a programmable fuse block; and logic coupled to the programmable fuse block to drive a first set of configuration states from a programmable fuse block, to generate a first control signal value to indicate that the processor desires to drive one or more secondary set of configuration states from the programmable fuse block, to receive a second control signal value to indicate that the processor may drive the secondary set of configuration states from the programmable fuse block, and to drive the secondary set of configuration states from the programmable fuse block.
- 12. The processor of claim 11, wherein the first set of configuration states specifies a first voltage and any secondary sets of configuration states specify a secondary voltage.
- 13. The processor of claim 11, wherein the first set of configuration states specifies a first frequency and any secondary sets of configuration states specify a secondary frequency.
- 14. An apparatus, comprising:
a machine-readable medium having stored thereon instructions for causing a processor to:
drive a first set of configuration states from a programmable fuse block, the first set of configuration states specifying a first set of inputs to the processor; generate a first control signal value to indicate that the processor desires to drive one or more secondary set of configuration states from the programmable fuse block, the secondary set of configuration states specifying a secondary set of inputs to the processor; receive a second control signal value to indicate that the processor may drive a secondary set of configuration states from the programmable fuse block; and drive the secondary set of configuration states from the programmable fuse block.
- 15. The apparatus of claim 14, wherein the first set of configuration states specifies a first voltage and any secondary configuration states specifies a secondary voltage.
- 16. The apparatus of claim 14, wherein the first set of configuration states specifies a first frequency and any secondary configuration states specify a secondary frequency.
- 17. The apparatus of claim 14, wherein the instructions are further to cause the processor to permit a voltage regulator to read the first and secondary sets of configuration states when a fuse block voltage has reached a threshold value.
- 18. The apparatus of claim 14, wherein the instructions are further to cause the processor to receive a third control signal value to permit a clock generator or a voltage regulator to read the programmable fuse block when the programmable fuse block fuse block voltage has reached a threshold value.
- 19. The apparatus of claim 16, wherein the instructions are further to cause the processor to permit a clock generator or a voltage regulator to read the programmable fuse block after a predetermined time period has elapsed.
- 20. The apparatus of claim 19, wherein the instructions are further to cause the processor to receive a frequency or a voltage from the clock generator or voltage regulator, respectively, after the clock generator or voltage regulator reads the programmable fuse block.
- 21. An apparatus, comprising:
a machine-readable medium having stored thereon instructions for causing a processor to:
operate at a first processor configuration based on a first configuration state read from a programmable fuse block; assert a configuration change control signal value to indicate a change to a secondary processor configuration; latch at least one secondary configuration state from the programmable fuse block, de-assert the configuration change control signal value; and operate at the secondary processor configuration based on any secondary configuration state read from a programmable fuse block.
- 22. The apparatus of claim 21, wherein the first configuration state specifies a first voltage and any secondary configuration states specify a secondary voltage.
- 23. The apparatus of claim 21, wherein the first configuration state specifies a first frequency and any secondary configuration states specify a secondary frequency.
- 24. The apparatus of claim 21, wherein the instructions are further to cause the processor to permit a voltage regulator to read the first and secondary configuration states when the programmable fuse block voltage has reached a threshold value.
RELATED APPLICATIONS
[0001] The present application is related to U.S. Ser. No. 09/746,168.