The present disclosures generally relate to integrated circuits, and more particularly, to multistage dynamic domino circuits with an internally generated delay reset clock.
In a high speed design, dynamic circuits are often used. Often, multiple dynamic stages are used within a single clock phase. The second stage in this chain is often “footless,” where there is no clocked n-channel device. The second stage requires a clock which delays only the falling edge of the first stage clock. Accordingly, this avoids the precharge device being on at the same time while the evaluate device is still on.
However, it is critical that the rising edge of the second stage clock is not delayed more than the first stage evaluate time. If it is, then there is a delay penalty in the second stage. There will also be excess current in the precharge and evaluate devices. This time, the current is due to the precharge device being late to turn off. In one prior art device, to avoid these problems, a second stage clock (clk_delay) is generated outside of the dynamic block.
Footed dynamic domino stage 12 further includes a keeper device 26, for example, a p-channel device. Keeper device 26 includes a control input coupled to an output 28 of stage 12. In addition, an inverter 30 couples between the evaluation logic 20 and output 28. Furthermore, keeper device 26 also includes terminals coupled between system voltage supply potential (VDD) 32 and evaluation logic 20.
Footless dynamic domino stage 14 includes precharge device 34 and a clock delay 36, wherein clock delay 36 has an output (clk_delay) 38. Clock delay 36 includes a falling edge delay 40, a NOR gate 42, and an inverter 44. Falling edge delay 40 includes, for example, serially coupled first and second inverters. NOR gate 42 receives a first input corresponding to clock signal (clk) on signal line 18 and a second input corresponding to an output of the falling edge delay 40. An output of NOR gate 42 is input to inverter 44, which in turn provides an output signal on output (clk_delay) 38.
Footless dynamic domino stage 14 also includes evaluation logic 46 and a keeper device 48, for example, a p-channel device. Keeper device 48 includes a control input coupled to an output 50 of stage 14. In addition, an inverter 52 couples between the evaluation logic 46 and output 50. Furthermore, keeper device 48 also includes terminals coupled between system voltage supply potential (VDD) 32 and evaluation logic 46. Evaluation logic is coupled to system ground via system ground 33, making the stage a footless stage.
Footed dynamic domino stage 12 further includes a keeper device 26, for example, a p-channel device. Keeper device 26 includes a control input coupled to an output 28 of stage 12. In addition, an inverter 30 couples between the evaluation logic 20 and output 28. Furthermore, keeper device 26 also includes terminals coupled between system voltage supply potential (VDD) 32 and evaluation logic 20.
Circuit 60 includes external devices 64 and 68. Device 64 includes a buffer delay for delaying a clock input signal on line 62 and providing a output delayed clock (clk1) on signal line 66. Clock delay 68 includes a delay 40, a NOR gate 42, and an inverter 44. Delay 40 includes, for example, a falling edge delay of serially coupled first and second inverters. NOR gate 42 receives a first input corresponding to clock signal (clk) on signal line 62 and a second input corresponding to an output of the delay 40. An output of NOR gate 42 is input to inverter 44, which in turn provides an output signal on output (clk_delay) 70. Footless dynamic domino stage 14 includes precharge device 34 having a control input of precharge device 34 coupled to the output (clk_delay) of clock delay 68 on signal line 70.
Footless dynamic domino stage 14 also includes evaluation logic 46 and a keeper device 48, for example, a p-channel device. Keeper device 48 includes a control input coupled to an output 50 of stage 14. In addition, an inverter 52 couples between the evaluation logic 46 and output 50. Furthermore, keeper device 48 also includes terminals coupled between system voltage supply potential (VDD) 32 and evaluation logic 46. Evaluation logic is coupled to system ground via system ground 33, making the stage a footless stage.
However, an inherent weakness of circuit 60 is that the external placement of clock buffer 64 and clock delay 68 causes timing issues when the circuit is integrated into a chip. For example, signal line 66 (clk1) and signal line 70 (clk_delay) have different loads and wire lengths when routed at the chip level. As a result, the corresponding delays must be matched subsequent to being routed to their destinations within the chip, adding complexity to the chip design and manufacture thereof.
Accordingly, there is needed a circuit structure and method for overcoming the problems in the art as discussed above.
According to one embodiment of the present disclosure, a multistage dynamic domino circuit includes a footed dynamic domino stage, a footless dynamic domino stage, and a internal delay circuit. The footed dynamic domino stage includes a first precharge circuit, evaluation logic, and a data output coupled to the evaluation logic. The footless dynamic domino stage includes evaluation logic including a data input coupled to the data output of the footed dynamic domino stage and a second precharge circuit. The second precharge circuit includes a first precharge device including a first current terminal and a control terminal coupled to a clock line. The second precharge circuit further includes a second precharge device including a first current terminal coupled to the first current terminal of first precharge device and a control terminal. The delay circuit includes an input coupled to the clock line and an output coupled to the control terminal of the second precharge device to provide a delayed version of a clock signal provided at the input of the delay circuit.
The embodiments of the present disclosure are illustrated by way of example and not limited by the accompanying figures, in which like references indicate similar elements, and in which:
Skilled artisans appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve an understanding of the embodiments of the present disclosure.
As will be discussed further herein , the embodiments of the present disclosure remove a prior restriction that the second stage clock (clk_delay) be generated outside of the dynamic block. Accordingly, the embodiments of the present disclosure allow for the second stage clock (clk_delay) to be internally generated. In one embodiment, the second stage includes two p-channel precharge devices. A first precharge device turns off on the rising edge of the clock. The second precharge device is controlled by a delayed version of the same clock. Furthermore, according to another embodiment of the present disclosure, a number of footless stages are daisy chained or cascaded together in a serial arrangement, including daisy chaining the internal delay repeatedly from one stage to a next stage to form a multistage dynamic domino circuit with an internally generated delay reset clock.
Referring again to the figures,
Footed dynamic domino stage 82 further includes a keeper device 102, for example, a p-channel device. Keeper device 102 includes a control input coupled to an output 104 of stage 82. In addition, an inverter 106 couples between the evaluation logic 90 and output 104. Furthermore, keeper device 102 also includes terminals coupled between system voltage supply potential (VDD) 108 and evaluation logic 90.
Footless dynamic domino stage 84 includes precharge circuit 112 and a delay circuit 118. Precharge circuit 112 includes serially coupled p-channel devices 114 and 116. Clock Delay circuit 118 includes, for example, serially coupled first and second inverters 120,122 for delaying the clock signal (clk) on signal line 88 to provide an output signal (clk_delay) on output signal line 119. Precharge circuit 112 receives first and second input signals corresponding to clock signal (clk) from signal line 88 and a delayed clock (clk_delay) from signal line 119, respectively.
Footless dynamic domino stage 84 also includes evaluation logic 124 having data inputs e and f, corresponding to reference numerals 126 and 128, respectively. Evaluation logic 124 also includes an input coupled to an output of the footed dynamic domino stage 82 at signal line 104. Evaluation logic 124 couples to ground at 110. As shown, evaluation logic 90 and evaluation logic 124 are for illustration purposes only, and can otherwise include any suitable evaluation logic for a particular multistage domino circuit application. Footless dynamic domino stage 84 further includes a keeper device 130, for example, a p-channel device. Keeper device 130 includes a control input coupled to an output 132 of stage 84. In addition, an inverter 134 couples between the evaluation logic 124 and output 132. Furthermore, keeper device 130 also includes terminals coupled between system voltage supply potential (VDD) 108 and evaluation logic 124. Evaluation logic 124 is coupled to system ground via system ground 110, making the stage a footless stage.
The second timing signal is that of (clk_delay) on signal line 119. Reference numeral 148 identifies a rising edge of clk_delay on signal line 119. Reference numeral 150 identifies a falling edge of clk_delay on signal line 119. The third timing signal is that of the output of footed stage 82 on signal line 104, also corresponding to an input of the evaluation circuit 124. Reference numeral 152 identifies a rising edge of signal on line 104 and reference numeral 154 identifies a falling edge of the signal on line 104. The fourth timing signal is that of the input signal line 128 of the evaluation circuit 124. Reference numeral 156 identifies a rising edge of signal on line 128 and reference numeral 158 identifies a falling edge of the signal on line 128.
An advantage of circuit 80 of
In addition, an advantage of circuit 80 of
Footless dynamic domino stage 164 includes precharge circuit 170 and a delay circuit 176. Precharge circuit 170 includes serially coupled p-channel devices 172 and 174. Clock delay circuit 176 can include, for example, serially coupled first and second inverters for delaying the clock signal (clk) on signal line 158 and provide an output signal (clk_delay) on an output signal line 178 of the clock delay circuit. Precharge circuit 170 receives first and second input signals corresponding to clock signal (clk) from signal line 158 and a delayed clock (clk_delay) from the output 178 of clock delay circuit 176, respectively. Footless dynamic domino stage 164 also includes evaluation logic that includes an input coupled to an output of the footed dynamic domino stage 162. As shown in
Footless dynamic domino stage 164 further includes a keeper device, for example, a p-channel device. The keeper device includes a control input coupled to an output of stage 164. In addition, an inverter couples between the evaluation logic and output. Furthermore, the keeper device also includes terminals coupled between system voltage supply potential (VDD) and the evaluation logic. The evaluation logic couples to system ground via a system ground, making the stage a footless stage.
Footless dynamic domino stage 166 includes precharge circuit 180 and a delay circuit 186. Precharge circuit 180 includes serially coupled p-channel devices 182 and 184. Clock delay circuit 186 can include, for example, serially coupled first and second inverters for delaying the clock signal (clk) on signal line 158 and provide an output signal (clk_delay) on an output signal line 188 of the clock delay circuit. Precharge circuit 180 receives first and second input signals corresponding to clock signal (clk) from signal line 158 and a delayed clock (clk_delay) from the output 188 of clock delay circuit 186, respectively. Footless dynamic domino stage 166 also includes evaluation logic that includes an input coupled to an output of the footless dynamic domino stage 164. The evaluation logic of stage 166 can include any suitable evaluation logic for a particular multistage domino circuit application.
Footless dynamic domino stage 166 further includes a keeper device, for example, a p-channel device. The keeper device includes a control input coupled to an output 190 of stage 166. In addition, an inverter couples between the evaluation logic and output 190. Furthermore, the keeper device also includes terminals coupled between system voltage supply potential (VDD) and the evaluation logic. The evaluation logic couples to system ground via a system ground, making the stage a footless stage.
In the embodiment of
Furthermore, with respect to the multistage dynamic domino circuit 160, delay block 186 can also be configured differently. That is, in another alternate embodiment, delay block 186 is not required to be coupled as shown but can be optimized with the clock (clk) on signal line 158 as an input, as opposed to receiving its input from the output 178 of delay block 176. This method would require that delay block 186 take into account a precharge delay greater than an accumulation of all preceeding precharge stages before the output of delay block 186 falls, making p-channel device 184 conductive to supply potential VDD. As shown in
According to one embodiment, the multistage domino circuit includes two series p-channel devices and a delay chain within at least the second stage to allow for internal generation and control of the delay reset falling edge only. Accordingly, the requirement for an external pulse generator as implemented in the prior art is no longer needed. Rather, according to the present embodiments, internal circuits as described herein resolve the difficult timing and integration issues of the external pulse generator implementations.
In the foregoing specification, the disclosure has been described with reference to various embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present embodiments as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present embodiments.
Benefits, other advantages, and solutions to problems have been described above with regard to specific embodiments. However, the benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential feature or element of any or all the claims. As used herein, the term “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements by may include other elements not expressly listed or inherent to such process, method, article, or apparatus.