Patent Application
20250183877
The present description relates to a multistage feed network, a superconducting system comprising the multistage feed network, and a method for fabricating the superconducting system. In particular, the present description relates to a multistage feed network for distributing a signal for feeding a plurality of tiles of a superconducting circuit.
A superconducting circuit typically comprises superconducting wires and Josephson junctions that together form superconducting loops in which information in the form of a magnetic single flux quantum (SFQ) is encoded and stored.
The superconducting circuits can be configured to implement traditional logic gates such as AND gates, OR gates, Flip Flops, etc. These gates, in turn, can be configured to implement more complex logic such as shift registers, counters, processors, etc.
A superconducting system comprising superconducting circuits is capable of performing computing operations at a clock rate in excess of 100 GHz and is over 100 times more energy efficient than conventional electronic circuits. However, distributing signals, such as power signals and clock signals, to a large-scale superconducting circuit can be challenging.
Manufacturing superconducting systems is also difficult due to fabrication limitations related to power distribution, logic efficiency, and memory density.
Hence, there is a need for an improved superconducting circuit and an improved method for fabricating a superconducting circuit.
An objective of the present description is to provide an improved multistage feed network for distributing signals for feeding a superconducting circuit. The multistage feed network can suppress parasitic modes, and maintain a uniform signal amplitude and/or a uniform signal phase for feeding the superconducting circuit.
Another objective of the present description is to provide a method for fabricating a superconducting system comprising a superconducting circuit including Josephson junction(s) and a multistage feed network, by forming Josephson junction(s) in some layers of a fabrication stack, while forming other parts of the superconducting circuit and the multistage feed network, in other layers of the fabrication stack. That is, the multistage feed network may be formed by using the existing resources (e.g., layers of the fabrication stack) for forming other parts of the superconducting circuit. This is advantageous not only for parameter targeting of the superconducting system but also for a simplified manufacturing of superconducting systems.
According to an aspect, there is provided a multistage feed network for distributing a signal for feeding a superconducting circuit. The multistage feed network comprises:
For example, the two-port network may comprise a first port and a second port; wherein a voltage across the first port is V1, a current flowing through a terminal of the first port is I1, a voltage across the second port is V2, a current flowing through a terminal of the second port is I2; wherein parameters A, B, C and D of the two-port network may be defined as:
The above example is an ideal two-port network. Practical implementations, e.g., by using superconducting materials, may be used to achieve a result close to the ideal two-port network.
The first incoming signal received from the AC voltage source may be used as a combined power/clock signal, which can be used to provide power and/or clock to a superconducting circuit.
The multistage feed network may be used for distributing a power signal and/or clock signal to the superconducting circuit.
Said one of the plurality of two-port networks may comprise at least one transmission line element having a length of one-half wavelength (λ/2).
The at least one transmission line element may comprise a single transmission line having a length of one-half wavelength (λ/2), or two transmission lines (i.e. a cascade of two transmission lines) connected in series each having a length of one quarter wavelength (λ/4).
The wavelength (λ) in the present description may refer to a wavelength of a signal transmitted through the transmission line(s).
A transmission line is a conductor designed to conduct an electromagnetic signal, when the conductor is long enough relatively to the wavelength of the signal such that the wave nature of the transmission must be taken into account. Transmission lines are widely used in the fields where the wavelengths of the transmitted signals are short, e.g., radio frequency (RF) engineering.
For the purposes of analysis, a transmission line can be modelled as a two-port network.
The at least one transmission line element may be implemented as a lumped element network comprising at least one inductor and at least one capacitor.
The Nth stage may comprise a bottom mesh network made of interconnected superconducting wires configured to feed the pluralities of Nth outgoing signals to the superconducting circuit.
The bottom mesh network may comprise multiple mesh network partitions split by one or more capacitors.
At least one of the one or more capacitors may be connected in series between every two adjacent mesh network partitions for splitting the bottom mesh network.
A capacitance of the at least one of the one or more capacitors may be selected to cause a resonance with inductors of said two adjacent mesh network partitions.
The first stage may comprise a top mesh network made of interconnected superconducting wires configured to electrically connect to multiple nodes for feeding the plurality of first outgoing signals to the second stage.
The first stage may comprise a transmission line element having a length of an integer multiple of one wavelength (λ) between any two electrically connected adjacent nodes of the multiple nodes.
Any stage of the number N stages, except for the first and the Nth stage, may comprise a mesh network made of interconnected superconducting wires configured to feed the pluralities of the outgoing signals of said stage to its immediate subsequent stage.
Said mesh network may comprise multiple mesh network partitions split by one or more capacitors.
At least one of the one or more capacitors may be connected in series between every two adjacent mesh network partitions for splitting said mesh network.
A capacitance of the at least one of the one or more capacitors may be selected to cause a resonance with inductors of said two adjacent mesh network partitions.
Any stage of the number N stages, except for the first and the Nth stage, may comprise a mesh network made of interconnected superconducting wires configured to electrically connect to multiple nodes for feeding the pluralities of the outgoing signals of said stage to its immediate subsequent stage.
Said stage may comprise a transmission line element having a length of an integer multiple of one wavelength (λ) between any two electrically connected adjacent nodes of the multiple nodes.
Said one of the plurality of two-port network may comprise a first matching network element and a second matching network element electrically connected in series between said stage and its immediate subsequent stage.
The first matching network element may comprise:
The second matching network element may comprise:
According to a second aspect, there is provided a superconducting system, comprising a superconducting circuit comprising a plurality of tiles. Each of the plurality of tiles comprises:
The superconducting system comprises the multistage feed network according to the first aspect configured to feed an outgoing signal of the pluralities of Nth outgoing signals to the terminal shared by the inductor and the at least one capacitor.
An inductance of the inductor and a capacitance of the at least one capacitor may be selected to cause the at least one resonant circuit to resonate at a frequency that substantially matches a particular frequency of said outgoing signal to facilitate switching a state of the at least one Josephson junction via a single flux quantum, SFQ, pulse.
The term “substantially” should be understood as a tolerance may exist between the frequency at which the at least one resonant circuit resonates and the particular frequency of said outgoing signal.
In other words, although the frequency at which the at least one resonant circuit resonates may not perfectly match the particular frequency, the tolerance may be tiny enough such that a matching can be considered to be achieved.
The tolerance may be 10%, preferably 5%, more preferably 2%, most preferably 1%, of the particular frequency.
According to a third aspect, there is provided a superconducting system, comprising a phase generator of a ring structure for generating multiple phase signals for feeding a superconducting circuit. The phase generator is configured to electrically connect to an AC voltage source such that a current flows through the ring structure in one direction;
At least one of the number M transmission line elements may be implemented as a lumped element network comprising at least one inductor and at least one capacitor.
The superconducting system may comprise the superconducting circuit. The superconducting circuit may comprise a plurality of tiles, each comprising:
According to a fourth aspect, there is provided a method for fabricating a superconducting system comprising:
The method comprises:
The step of 1) forming, in first layers of a fabrication stack, the multistage feed network and the plurality of tiles except for the at least one Josephson junction may comprise:
The step of 1) forming, in first layers of a fabrication stack, the multistage feed network and the plurality of tiles except for the at least one Josephson junction may comprise:
According to a fifth aspect, there is provided a method for fabricating a superconducting system comprising
The method comprises:
The second, third, fourth and fifth aspects may generally present the same or corresponding advantages as the first aspect.
It is noted that the invention relates to all possible combinations of features recited in the claims.
The above, as well as additional objects, features, and advantages of the present description, will be better understood through the following illustrative and non-limiting detailed description, with reference to the appended drawings. In the drawings like reference numerals will be used for like elements unless stated otherwise.
A superconducting circuit comprises superconducting wires formed from materials that can carry a direct current (DC) in the absence of an electric field. Such materials have almost zero resistance at or below their critical temperature. One example superconductor, niobium, has a critical temperature (Tc) of 9.3 Kelvin. At temperatures below the critical temperature, niobium is superconductive. However, at temperatures above the critical temperature, niobium behaves like a normal metal with electrical resistance.
A superconducting tile is an elemental circuit with materials that can conduct electricity with almost zero resistance when cooled below the critical temperature. Examples of superconducting materials include superconducting ceramics and superconducting metals.
The superconducting circuit comprises a plurality of tiles each comprising at least one Josephson junction. The Josephson junction typically comprises two superconductors coupled via a region that restricts the current. Examples of this region include or correspond to a physical narrowing of the superconductor itself, a metal region, or a thin insulating barrier. Some examples of Josephson junctions comprise niobium superconductors and an Al2O3 barrier therebetween. When a potential difference between the two superconductors is integrated with respect to time over one cycle of phase change, the magnetic flux through the loop changes by an integer multiple of a single quantum of magnetic flux. The voltage pulse associated with the single quantum of magnetic flux corresponds to a SFQ pulse. As an example, overdamped Josephson junctions can create individual SFQ pulses. In AC-SFQ circuits, each Josephson junction may be part of one or more superconducting loops. The phase difference across the Josephson junction may be modulated by the magnetic flux applied to the loop.
In connection with
For example, each tile 1A-1I may comprise at least one resonant circuit. The resonant circuit may be driven by a signal having a particular frequency and is configured to resonate at substantially the same frequency at which it is being driven.
The resonant frequencies of the resonant circuits of the plurality of tiles 1 may be substantially the same (e.g., 100 GHZ), but the phase may be different. The number of phases required relates to many factors, including but not limited to: the size of the pipeline of AC-SFQ circuits being driven by the resonant circuits, the frequency at which the AC-SFQ circuits are clocked, the size of the superconducting circuit, etc.
If eight phases are required, the phases of the resonant circuits of different tiles 1 may be spaced apart by 45°. For example, the phase of the resonant circuits of the first tile 1A is 0°, the phase of the resonant circuits of the second tile 1B is 45°, the phase of the resonant circuits of the third tile 1C is 90°, . . . .
If four phases are required, the phases of the resonant circuits of different tiles 1 may be spaced apart by 90°. For example, the phase of the resonant circuits of the first tile 1A is 0°, the phase of the resonant circuits of the second tile 1B is 90°, the phase of the resonant circuits of the third tile 1C is 180°, . . . .
Taking
The superconducting circuit 100 may comprise multiple groups of tiles as illustrated in
A feed network is needed for feeding signals to the large number of tiles 1. The feed network can be implemented as a resonant LC feed network. However, the performance of such resonant LC feed network is limited due to different reasons.
One reason is the parasitic higher order resonant modes. The frequency separation between wanted (ZOR) mode and higher order modes will decrease with an increasing size of the feed network. For a larger feed network size, wanted (ZOR) mode and unwanted modes overlap which will lead to amplitude and phase variations over the feed network.
Other reasons include the process parameter variations. A linear variation of the resonance frequency on a large feed network will lead to very large amplitude and phase variations over the feed network.
Other reasons also include parasitic capacitance. The resonant LC feed network has low voltage levels, but the feed network has significant voltages and is sensitive to parasitic capacitance that causes parasitic coupling to ground and between different phases of the feed network. The parasitic capacitance of the feed network further limits the
impedance of the matching network which severely limits the maximum obtainable feed impedance of the feed network.
Further, due to the phase variations mentioned in the above, generating and delivering multiple phase signals on-chip with an acceptable error in both phase and amplitude is challenging. Thus, an improved multistage feed network for distributing a signal for feeding a superconducting circuit is described in the present description.
In connection with
Hereinafter, the example multistage feed network used in the present description has three stages as shown in
The multistage feed network 2 comprises at least two stages. Preferably, the multistage feed network 2 comprises at least three stages.
The multistage feed network 2 comprises a plurality of two-port networks 21, each configured to electrically connect to two adjacent stages in between. Each two-port network 21 is configured to perform impedance matching between the two stages that it is electrically connected to.
This is advantageous as the multistage feed network 2 may transform the very low impedance of the tiles 1 to the 50-ohm impedance at the signal source (not shown).
The first stage Z2 is configured to electrically connect to a signal source (not shown) for receiving a first incoming signal, and to distribute the first incoming signal to a plurality of first outgoing signals.
A two-port network 21A is configured to be provided in between and to electrically connect to the first stage Z2 and the second stage Z1.
The second stage Z1 is configured to receive a plurality of second incoming signals, and to distribute each of the plurality of second incoming signals to a plurality of second outgoing signals.
A two-port network 21B is configured to be provided in between and to electrically connect to the second stage Z1 and the third stage Z0.
The third stage Z0 is configured to receive a plurality of third incoming signals, and to distribute each of the plurality of third incoming signals to a plurality of third outgoing signals.
The pluralities of the third outgoing signals are configured to be fed to the superconducting circuit (the tiles 1).
A feed line 20 for feeding the signal from the signal source to the first stage Z2 is represented as a transmission line in
The signal source is an Alternating Current (AC) voltage source. The first incoming signal received from the signal source is a combined power/clock signal. The combined signal may be used to provide both power and clock to the superconducting circuit.
At least one of the multiple stages Z2, Z1, Z0 comprises a mesh network made of interconnected superconducting wires such that the incoming signal(s) of said stage is configured to be distributed to the outgoing signals of said stage by said mesh network with a minimal deviation of signal amplitude and of signal phase.
For each stage except for the last stage (e.g., the first stage Z2 and the second stage Z1 in
Each of the plurality of first outgoing signals of the first stage Z2 is configured to be electrically coupled to one of the plurality of the second incoming signals of the second stage Z1 by the two-port network 21A. That is, the plurality of first outgoing signals become the plurality of the second incoming signals after passing through the two-port network 21A. The plurality of first outgoing signals and the plurality of second incoming signals may have a one-to-one correspondence.
Each of the pluralities of second outgoing signals of the second stage Z1 is configured to be electrically coupled to one of the plurality of the third incoming signals of the third stage Z0 by the two-port network 21B. That is, the pluralities of second outgoing signals become the plurality of the third incoming signals after passing through the two-port network 21B. The pluralities of second outgoing signals and the plurality of third incoming signals may have a one-to-one correspondence.
In
The multistage feed network 2 can be considered as a “hierarchical” feed network which receives a source signal from the AC voltage source at a top stage (i.e. the first stage Z2), and further distributes the signal(s) in each stage for uniformly feeding the plurality of tiles 1. The deviations of signal amplitude and of signal phase between the outgoing signals can be minimized, or at least reduced.
The term “hierarchical” here refers merely to the flow of the signals from upstream (the signal source) to downstream (the tiles 1). The term “hierarchical” does not imply the relative positions or layers of a fabrication stack where the stages of the multistage feed network are formed. That is, the first, second, . . . and Nth stages do not need to be formed in a particular order in the fabrication stack.
The multistage feed network 2 may have a progressively increased impedance from the Nth stage to the first stage.
The multistage feed network 2 may be progressively sparser from the Nth stage to the first stage.
This is advantageous as the ZOR mode can be stabilized even when parameter gradients are present.
The two-port network 21 may comprise at least one transmission line element having a length of one-half wavelength (λ/2).
As an example, in
Each transmission line element may comprise a single transmission line having a length of one-half wavelength (λ/2), or two transmission lines connected in series (i.e. a cascade of two transmission lines) each having a length of one quarter wavelength (λ/4).
In the present description, the wavelength (λ) is the wavelength of a signal transmitted through the transmission line(s).
Any of the transmission lines may be implemented as a classical transmission line, as a miniaturized transmission line (e.g., using periodic inductive and/or capacitive loading), or as a lumped LC network.
In the present description, any transmission line element may be implemented as a lumped element network comprising at least one inductor and at least one capacitor.
A lumped element network may comprise only inductor(s) and capacitor(s) coupled together. In the present description, any transmission line element may be implemented as a lumped element network comprising only inductor(s) and capacitor(s) coupled together.
This is advantageous as all these implementations may be formed by using the available components (e.g., superconducting wires, inductors, and capacitors) already existing in the fabrication stack.
In connection with
The two-port network 21 of
Each port comprises two terminals +, −. A voltage across the two terminals of the first port is V1, and a current flowing through any one of the two terminals of the first port is I1. A voltage across the two terminals of the second port is V2, and a current flowing through any one of the two terminals of the second port is I2. The same current may flow into each port as may leave that port.
The two-port network 21 can be mathematically defined by using parameters A, B, C and D as:
The two-port network 21 can also be mathematically defined by using other parameters, such as z parameter, y parameter, etc.
The last stage (i.e. the third stage Z0 in
The bottom mesh 22C may be a mesh, e.g., a two-dimensional (2D) mesh as shown in
The first stage Z2 may comprise a top mesh network 22A made of interconnected superconducting wires configured to electrically connect to multiple nodes (not shown) for feeding the plurality of first outgoing signals to the second stage. Each node of the multiple nodes may be configured to electrically couple to at least two other nodes of the multiple nodes.
The first stage Z2 may comprise a transmission line element having a length of an integer multiple of one wavelength (λ) between any two electrically connected adjacent nodes of the multiple nodes.
This is advantageous as parasitic capacitance incorporated into the top mesh network 22A can be absorbed by the full-wavelength transmission line between the adjacent nodes. Thus, the two-port network 21A can be fed with signals of a same phase. It can guarantee a minimum amplitude variation even when there are significant parasitic capacitance and linear parameter variations. Thus, it can improve performance of the signal (power/clock signal) distribution over a large distance across a large-scale superconducting circuit.
Alternatively, or in combination, the top mesh network 22A may further comprise a transmission line having an integer multiple of one-half wavelength (λ/2) between at least some of the two electrically coupled nodes of the first mesh.
Nodes connecting to the transmission line having a length of an integer multiple of one-half wavelength (λ/2) may be interleaved with nodes connecting to the transmission line having a length of an integer multiple of one wavelength (λ), for feeding signals of an opposite phase to its immediate subsequent stage.
This may reduce by half the number of two-port networks needed between two stages. This may result in a lower total parasitic capacitance and less resource consumption for the routing layers. The transmission lines may be realized by any known ways, such as a classical transmission line, a miniaturized transmission lines (e.g., using periodic inductive and/or capacitive loading), or as lumped LC structures.
The “middle” stages, i.e. any stage of the number N stages except for the first and the Nth stage (e.g., the second stage Z1 in
Said “middle” stage may comprise a transmission line element having a length of an integer multiple of one wavelength (λ) between any two electrically connected adjacent nodes of the multiple nodes.
A superconducting system comprises a superconducting circuit comprising the plurality of tiles 1, and the multistage feed network 2. Each of the plurality of tiles 1 comprises at least one resonant circuit comprising an inductor comprising a first terminal and a second terminal, and at least one capacitor comprising a first terminal electrically connected to the second terminal of the inductor; and at least one Josephson junction comprising a first terminal electrically connected to a second terminal of the at least one capacitor and a second terminal electrically connected to a ground or virtual ground node. The multistage feed network 2 is configured to feed an outgoing signal of the pluralities of Nth outgoing signals to the terminal shared by the inductor and the at least one capacitor.
In connection with
The resonant circuit can bias the Josephson junction 13.
A terminal shared by the inductor 11 and the capacitor 12 (i.e. the terminal connected to the first terminal 12A of the capacitor 12 and the second terminal 11B of the inductor 11) may be configured to receive a Nth outgoing signal from the Nth stage (e.g., the third stage Z0 in
The terminal may be configured to be fed with the Nth outgoing signal via the Nth mesh network (e.g., the third mesh 22C in
The AC voltage source (not shown) may be configured to output the first incoming signal having a particular magnitude, frequency, and phase. The first incoming signal may be distributed stage by stage into the Nth outgoing signals. Upon being driven by the Nth outgoing signal, the resonant circuit is configured to generate an AC signal that applies a bias voltage to the Josephson junction 13.
An inductance of the inductor 11 and a capacitance of the at least one capacitor 12 may be selected to cause the at least one resonant circuit to resonate at a frequency that substantially matches a particular frequency of the Nth outgoing signal to facilitate switching a state (e.g., advancing the superconductor phase) of the at least one Josephson junction 13, e.g., via a single flux quantum, SFQ, pulse.
For example, the inductance of the inductor 11 and the capacitance of the capacitor 12 of the resonant circuit may be selected to satisfy the expression:
where f is the resonant frequency, L is the inductance of the inductor 11, and C is the capacitance of the capacitor 12.
The values of the output impedance and magnitude of the AC voltage source, the inductance of the inductor 11, etc., may be selected based and/or may depend on various parameters.
The resonant circuit of
The inductance of the inductor 11 scales inversely with the number of the plurality of capacitors 12. In particular, the inductance of the inductor 11 and the capacitances of the plurality of capacitors 12 are selected to satisfy the expression:
where f is the resonant frequency, L is the inductance of the inductor 11, C is the capacitance of each of the plurality of capacitors 12, and A corresponds to the number of the plurality of capacitors 12, which in some examples corresponds to the number of the multiple Josephson junctions 13.
After discussing the superconducting system, the method for fabricating the superconducting system will be discuss in detail in connection with
The method for fabricating the superconducting system comprises: forming, in the first layers of a fabrication stack, the multistage feed network 2 and the plurality of tiles 1 except for the at least one Josephson junction 13 (S71); and forming, in second layers of the fabrication stack, the at least one Josephson junction 13 (S72).
This is advantageous as the multistage feed network 2 may be formed in the same layers of the fabrication stack for forming the tiles 1 except for the Josephson junctions 13.
The other features relating to the multistage feed network 2 described in the present description, e.g., the two-port network 21 for performing impedance matching, may be generally applicable to the method for fabricating the superconducting system.
The step (S71) of forming, in first layers of a fabrication stack, the multistage feed network 2 and the plurality of tiles 1 except for the at least one Josephson junction 13 may comprise:
The at least one Josephson junction 13 may comprise a first terminal 13A electrically connected to a second terminal 12B of the at least one capacitor 12 and a second terminal 13B electrically connected to a ground or virtual ground node.
The step (S71) forming, in first layers of a fabrication stack, the multistage feed network 2 and the plurality of tiles 1 except for the at least one Josephson junction 13 may comprise:
The fabrication stack comprising layers for forming the superconducting system will be discussed in detail.
The fabrication stack comprises first layers where the multistage feed network 2 and the tiles 1 except for the Josephson junctions 13 are formed.
That is, the resonant circuit(s), including the inductor(s) 11 and the capacitor(s) 12 may be formed in the first layers.
The first layers may comprise one or more inductor layers and one or more capacitor layers in which inductors 11 and capacitors 12 are respectively formed.
The first layers may comprise a ground layer (e.g., a ground plane) below each of the one or more capacitor layers to provide isolation.
The first layers may comprise a conductive interconnect layer where the one or more mesh networks are formed.
The superconducting circuit fabrication stack comprises second layers where the Josephson junctions 13 are formed.
The area of a particular tile on one of the first layers may be determined either by the area of its capacitor(s) 12 or the area of its inductor(s) 11. The area of a particular tile 1 may be made to match the area of its Josephson junctions 13.
For example, one hundred Josephson junctions having an average critical current, Ic, of 50 μA at a critical current density of
may occupy a 5×5 μm2 area, which can accommodate one hundred capacitors, but may only accommodate one inductor.
For instance, for the same frequency, bias current, quality factor Q, and capacitance requirements used in the tile 1 of
The capacitors 12 may be implemented as Metal-Insulator-Metal (MIM) structures comprising a high-K dielectric and high kinetic inductance electrodes (e.g., NbTiN electrodes). The MIM capacitors may be sized to provide a bias current, Ib, to the Josephson junction given by b Ib/Ic≈0.75. The target capacitance for the 35 μA Josephson junction is 2.6 fF and scales linearly with the Josephson junction size.
In some examples of the MIM capacitors, the dielectric comprises HfOx(Si), which has a high dielectric constant, k, and which facilitates tuning of the capacitance via an applied DC voltage. In an example, the area of the smallest capacitor is 0.1 μm2 which corresponds to a capacitor having a dielectric constant k of 32 and a 10 nm thickness. In some examples, the MIM capacitors have NbTiN electrodes.
In connection with
The bottom mesh network 22N may comprise multiple mesh network partitions split by one or more capacitors Cs. At least one of the one or more capacitors Cs may be connected in series between every two adjacent mesh network partitions for splitting the bottom mesh network 22N.
In
By providing the capacitor(s) Cs, the amplitude variations of the pluralities of Nth outgoing signals for feeding the tiles 1 can be reduced across the superconducting circuit as each partition of the bottom mesh network 22N can be individually biased and tuned to different resonant frequencies.
For example, the capacitance of the capacitors Cs can be selected to compensate the amplitude variations even when no tuning is applied on the capacitors Cr of the resonant circuits of the tiles 1.
A capacitance of the at least one of the one or more capacitors Cs may be selected to cause a resonance with inductors Lr of said two adjacent mesh network partitions.
The “middle” stages, i.e. any stage of the number N stages except for the first and the Nth stage (e.g., the second stage Z1) may comprise a mesh network made of interconnected superconducting wires configured to feed the pluralities of the outgoing signals of said stage to its immediate subsequent stage.
Similar to the bottom mesh network 22N as shown in
A capacitance of the at least one of the one or more capacitors may be selected to cause a resonance with inductors of said two adjacent mesh network partitions.
It is advantageous as said capacitor(s) may reduce the amplitude variations of the pluralities of outgoing signals of said stage for feeding to its immediate subsequent stage, as each partition can be individually biased and tuned to different resonant frequencies.
Each section 511, 512 comprises an inductor and a capacitor. In the bottom section 512, a capacitor Cb and an inductor Lb form a resonant low-pass network at a resonance frequency or, wherein ωr2LbCb=1.
In the top section 511, a capacitor Ct and an inductor Lt form a similar resonant low-pass network.
In
In
The impedance transformation of the two-port network 51 can be calculated as a voltage ratio
This ratio is equal to
Thus, the parasitic capacitance Cp of the stage Z1 limits the voltage ratio.
In connection with
Similar to the two-port network 51 of
Similarly to
In
Similar to the example of
Similar to the example of
The first matching network element 211 may comprise a series capacitor Ct comprising a first terminal electrically connected to the stage Z1, and a second terminal electrically connected to the second matching network element 212, and a shunt inductor Lt comprising a first terminal connected to the first terminal of the series capacitor Ct, and a second terminal electrically connected to a ground or virtual ground node.
The series capacitor Ct and the shunt inductor Lt of the first matching network element 211 may be considered as a high-pass network.
The second matching network element 212 may comprise a series inductor Lb comprising a first terminal electrically connected to the second terminal of the series capacitor Ct, and a second terminal electrically connected to the stage Z0, and a shunt capacitor Cp comprising a first terminal connected to the second terminal of the series inductor Lb, and a second terminal electrically connected to the ground or virtual ground node.
The series inductor L; and the shunt capacitor Cb of the second matching network element 212 may be considered as a resonant low-pass network at a resonance frequency ωr, wherein ωr2LbCb=1.
The impedance transformation of the two-port network 21 can be calculated as the voltage ratio
This ratio is equal to
Thus, the parasitic Capacitance Cp of the Z1 stage will no longer limit the voltage ratio.
Inclusion of the first matching network element 211 allows for a better compensation for parasitic capacitance Cp of the stage Z1 that it connects to. Consequently, with the two-port network 21, the multistage feed network 2 can achieve a higher voltage transformation. Further, it is possible to extend the number of tiles 1 as Cp is proportional to the number of tiles 1.
In connection with
The phase generator 3 comprises a ring structure for generating multiple phase signals for feeding a superconducting circuit (not shown).
The phase generator 3 is configured to electrically connect to an AC voltage source Vs such that a current flows through the ring structure in one direction.
The AC voltage source Vs may be electrically coupled to the ring structure via a coupling resistor Rs.
The AC voltage source Vs may be the same as the one the first stage electrically connected to for receiving the first incoming signal.
Alternatively, the AC voltage source Vs may be different from the one the first stage electrically connected to for receiving the first incoming signal.
For example, in
There are many other options to feed the phase generator 3, such as to feed the phase generator 3 by two quadrature signals (same amplitude, 90 degrees out-of-phase).
The ring structure comprises a number M transmission line elements configured to electrically connect in series, each having a length of an integer multiple of one Mth wavelength (λ/M). A number M different phase signals are configured to output between two adjacent transmission line elements of the number M transmission lines, respectively. M is an integer, and M≥2.
If M equals to 8, as shown in
The length of each transmission lines Zc1 may be an integer multiple of one eighth wavelength, such as one quarter or one-half wavelength. That is, a length of the ring structure (a total length of all the M transmission lines) may be an integer multiple of one wavelength (λ).
The superconducting system comprises a number M multistage feed networks 2 (not shown), each for feeding one of the number M different phase signals to the superconducting circuit (the tiles 1).
The parallel LC networks provided between two adjacent transmission lines Zc1 in
The geometry of the ring structure guarantees a generation of perfect multiphase signals at the resonance frequency of the ring structure. This topology has a very low phase error between the different phase signals due to the geometric structure of the ring structure when it is on resonance, corresponding to an integer multiple of a full wavelength over a length of ring structure.
The transmission lines Zc1 of the ring structure may be implemented by lumped LC pi-networks, e.g., by using integrated tile inductors and tunable bias capacitors available in the superconducting circuit fabrication stack. With the tunable capacitors, the resonance frequency of the ring structure and the feed line Zc2 (λ/4) can be adjusted to the frequency of the networks (e.g., power/clock networks) that it feeds. Multiple of such phase generators 3 may be provided in the superconducting circuit 100 for stabilizing the networks that they feed.
This is advantageous as the different phase signals may be generated internally on-chip instead of using external phase signals, such that an improved control of the phase signals can be achieved. Further, the properties of the phase signals, e.g., amplitude uniformity, can be improved.
The superconducting system may comprise the superconducting circuit comprising a plurality of tiles 1, each comprising at least one resonant circuit comprising: an inductor 11 comprising a first terminal and a second terminal, and at least one capacitor 12 comprising a first terminal electrically connected to the second terminal of the inductor; and at least one Josephson junction 13 comprising a first terminal electrically connected to a second terminal of the at least one capacitor and a second terminal electrically connected to a ground or virtual ground node.
The number M multistage feed networks 2 may be configured to feed the number M different phase signals to the terminal shared by the inductor 11 and the at least one capacitor 12, respectively.
Similar to the method of
This is advantageous as the multistage feed networks 2 and the phase generator 3 may be formed in the same layers of the fabrication stack for forming the tiles 1 except for Josephson junctions 13.
The step of forming, in first layers of a fabrication stack, the number M multistage feed networks 2, the phase generator 3, and the plurality of tiles 1 except for the at least one Josephson junction 13 may comprise:
The at least one Josephson junction 13 may comprise a first terminal 13A electrically connected to a second terminal 12B of the at least one capacitor 12 and a second terminal 13B electrically connected to a ground or virtual ground node.
The step forming, in first layers of a fabrication stack, the number M multistage feed networks 2, the phase generator 3, and the plurality of tiles 1 except for the at least one Josephson junction 13 may comprise: forming at least two stages of the multistage feed network 2 by interleaving two metal layers of the first layers.
The features of the fabrication stack comprising layers for forming the superconducting system discussed in connection to
In the above the inventive concept has mainly been described with reference to a limited number of examples. However, as is readily appreciated by a person skilled in the art, other examples than the ones disclosed above are equally possible within the scope of the inventive concept, as defined by the appended claims.
