The present invention relates generally to electronic communications, and more particularly to a system and method for amplifying a very low level radio frequency signal before it is further processed in a communications system or device.
A very steep growth in location-related services is foreseen in the next few years by industry analysts. Cellular phones with embedded Global Positioning Systems (GPS) engines will enable network-based positioning methods. Assisted GPS solutions allow a direct migration path into 3G handsets besides being more accurate than cell-tower-based ones. Co-existence of a GPS receiver together with cell-phones on the same Printed Circuit Board (PCB) poses new challenges, though. Power savings and a high integration level, in order to simplify the application board, are key targets. In this way, battery life is extended and bill of materials reduced. On the other hand, the limited isolation between transceivers makes leaking signals dangerous interferers.
Well-known GPS implementations include a passive filter to reduce the in-band noise of the signal. In these implementations the passive filter has very stringent requirements, adding substantial cost and real estate to the GPS functionality.
In light of the above, there exists a need for a new low-noise amplifier (LNA) architecture that reduces the need for passive filters in a GPS implementation.
The receiver front-end amplifier disclosed hereinafter addresses a need for eliminating an external passive filter in a low-power LNA for GPS applications. The LNA has a notch filter, followed by a first stage gain that is a highly linear voltage-voltage feedback LC-loaded low noise amplifier and a second stage gain.
The invention provides a receiver as set out in the claims appended hereto.
The invention will now be described by way of example with reference to the drawings in which:
In accordance with the present invention, a low noise amplifier for a GPS receiver within a cellular phone is composed of a notch filter, followed by a first gain stage that is an highly linear voltage-voltage feedback LC-loaded low noise amplifier and a second gain stage.
Referring to
Q1 and its associated components act as a low noise amplifier (LNA). Coupled between its collector terminal and the supply rail VS is an output resonant circuit Lload, Cload tuned to the wanted signal frequency. Voltage-voltage feedback is provided by a capacitive voltage divider C1, C2, C1 being coupled between the collector terminal and the base terminal of transistor Q1, and C2 being connected between the base terminal and ground. Transistor Q1 is provided with a bias current by a current source Ibias coupled to its base terminal.
The LNA with voltage-voltage feedback and an inductor-capacitor load is chosen due to its superior linearity performance, at given power consumption, over the inductively degenerated topology.
The notch filter is provided at a blocking frequency and is resonated out the wanted signal frequency by means of the capacitor Cbypass. The input impedance is thus the load impedance reflected by the feedback loop. Capacitor Cbypass forms a series-resonant circuit with an inductor Lnotch, resonant at the wanted signal frequency to allow a low impedance path from the input VIN to Q1 at that frequency.
In this way, attenuation of the wanted (GPS) signal by the notch is largely avoided despite the wanted signal frequency being adjacent the interference frequency.
Coupled to the output of the first gain stage formed by Q1 and its associated components via coupling capacitor C3 is a second gain stage having a common source input transconductor Q2 and an output device Q3. Field-effect transistor Q2 has its gate terminal connected to coupling capacitor C3 to receive the amplified and filtered version of the received signal. Transistor Q2 is biased from a first bias voltage source Vbias via a resistor Rbias coupled to the gate terminal. The source of transistor Q2 is connected to ground, whilst its drain terminal is coupled to the emitter of an output bipolar transistor Q3, the collector of which is coupled to the supply rail VS via a choke Lchoke. Bias for the output transistor Q3 is provided from a second bias source Vbias2 connected directly to the base terminal of transistor Q3. Transistor Q3 acts as a buffer and the amplified output signal obtained from the collector of the transistor Q3 is delivered to an output terminal IOUT via an output coupling capacitor C4.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/GB2006/003589 | 9/26/2006 | WO | 00 | 7/20/2007 |
Number | Date | Country | |
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60720254 | Sep 2005 | US |