Patent Application
20080268628
The present disclosure relates generally to the fabrication of semiconductor devices, and more particularly to the process of doping areas of semiconductor devices to impart electronic activity.
The present disclosure relates generally to the field of semiconductor fabrication. In conventional practice, semiconductor fabrication begins with the provision of a substrate wafer, comprising silicon formed in a regular, crystalline structure. A circuit pattern is devised in which regions of the substrate are intended to support NMOS and PMOS semiconductor devices. These regions are isolated from each other with the formation of electronically inert isolation trenches. Each region is then doped with a type of dopant opposite the electronic nature of the devices to be created thereupon. The formation of the semiconductor devices then occurs upon this substrate, and typically involves doping the electronically active areas of the device with the desired type of dopant. For instance, NMOS devices are often formed by implanting a p-type dopant in a region of the semiconductor, and then forming the devices by implanting an n-type dopant in order to create the electronically active regions of the NMOS device. In the case of a typical transistor, two electronically active areas are created in this manner to represent the source and drain regions of the transistor, and are bridged by forming a gate that can be operated to regulate electronic flow between the electronically active areas. The devices may then be connected through a metallization step, in which metal paths are formed to connect the electronically active areas of the devices into a fully interconnected circuit.
The disclosure more specifically relates to the process of doping a semiconductor substrate with an n-type dopant in order to form electronically active areas for these semiconductor devices. Conventional practice involves doping with an n-type dopant, which is often selected from the group IV elements, such as arsenic, phosphorus, and germanium. One method of performing this doping is by ion implantation, in which ionized particles of the compound are fired at high energy into designated areas of the semiconductor substrate. The group IV atoms enhance the n-type electronic conductivity in relation to the surrounding substrate. However, the implantation of these atoms also disrupts the lattice structure of the crystalline silicon wafer, thereby imparting an uncontrollable structural irregularity that may cause undesirable electronic or physical characteristics. This irregularity may be reduced by performing a subsequent annealing step, in which the semiconductor is exposed to high temperatures in order to re-establish the regular molecular bonds that impart a crystalline structure in the doped regions of the semiconductor.
The process described above may be used to place a dopant in a specific region that will serve as an electronically active area (referred to herein as the “target area,” both before and after doping.) It will be appreciated that in light of the trends of miniaturization and enhanced computation performance of electronic components, tight control of dopant placement is highly valued. The doping area must be controlled to form well-defined electronically active areas, and is typically delineated by the selective deposition of a photolithography layer that covers areas where doping is not desired. The doping therefore occurs only in the exposed regions, resulting in well-defined lateral borders of the electronically active areas. Also, tight controls on the depth of placement by ion implantation may improve control over the placement of dopant in the target area. The depth of ion implantation may be controlled by altering the velocity of the dopant ions fired at the semiconductor wafer, since relatively slow-moving ions will be placed at a shallower depth and within a tighter range.
However, in many doping methods, two physical characteristics may interfere with controlled placement of the dopant. First, the semiconductor substrate may form a crystalline lattice in a configuration that includes longitudinal channels. If an ion placed via ion implantation is fired at the substrate with an angle and position corresponding to a channel, it may deeply penetrate the substrate before coming to rest in a region of the lattice, resulting in undesirably deep penetration. Second, in both ion implantation and other types of dopant placement, when the substrate is heated for annealing, the target area becomes a region of high dopant concentration, and some of the dopant may diffuse out of the target area, both laterally and longitudinally, thereby disrupting the well-defined borders of the active area. Worse, the diffused dopant may connect with a neighbouring component or breach the isolation trench, causing unpredicted and undesirable electronic properties. Both of these characteristics of some doping processes disrupt the tight control of active area doping, and hence the performance and reliability of semiconductors fabricated in this manner.
It is always desirable to find improvements in doping techniques, and the present disclosure relates to such improvements.
The following presents a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the disclosure. This summary is not an extensive overview of the disclosure. It is intended neither to identify key or critical elements of the disclosure nor to delineate the scope of the disclosure. Rather, its primary purpose is merely to present one or more concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.
The present disclosure relates to the placement of arsenic as an n-type dopant in a target area in order to form active regions in an NMOS semiconductor component. As discussed herein, the placement of arsenic as a dopant may encounter two problems: the channeling of arsenic to an undesired depth for dopant introduced via ion implantation, and the diffusion of arsenic past the boundaries of the active area during heat-induced annealing. It has been discovered that placing carbon in the target area (before, during, or after placing arsenic) may reduce the diffusion of arsenic out of the target area during annealing. Accordingly, the diffusion of arsenic may be suppressed by placing a carbon-containing arsenic diffusion suppressant in the target area prior to annealing. Data supporting this result is presented and discussed herein. The present disclosure suggests this technique for the formation of an n-type active area on a semiconductor substrate, and particularly for the formation of an NMOS transistor. Enhancements of this technique, as discussed herein, may further improve the process control over the depth of doping, the undesirable diffusion of arsenic, and maintenance of the regularity of the silicon lattice.
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the disclosure. These are indicative of but a few of the various ways in which one or more aspects of the present disclosure may be employed. Other aspects, advantages and novel features of the disclosure will become apparent from the following detailed description of the disclosure when considered in conjunction with the annexed drawings.
One or more aspects of the present disclosure are described with reference to the drawings, wherein like reference numerals are generally utilized to refer to like elements throughout, and wherein the various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the present disclosure. It may be evident, however, to one skilled in the art that one or more aspects of the present disclosure may be practiced with a lesser degree of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more aspects of the present disclosure.
As discussed hereinabove, the present disclosure relates to the placement of arsenic in a target area of a semiconductor substrate for the purpose of forming an n-type active area. The control of the arsenic doping is facilitated by the introduction of a carbon-containing arsenic diffusion suppressant in the target area prior to annealing. Placing such an agent in the target area prior to annealing may reduce the diffusion of arsenic out of the target area, and may therefore enhance the border definition of the active area.
This advantage may be illustrated by reference to the figures of this disclosure.
By contrast,
In another set of embodiments, the arsenic and carbon-containing arsenic diffusion suppressant are used in addition to another n-type dopant. As noted above, among the group IV elements, phosphorus is sometimes preferred over arsenic as an n-type dopant. This preference is motivated for the alleviation of some disadvantageous properties of arsenic as an n-type dopant. For instance, arsenic is a larger atom than phosphorus, so it causes more disruption to the crystalline lattice upon ion implantation. A heavy dose of arsenic implantation may disrupt the heavily doped area to such an extent that annealing cannot bring the lattice within process control tolerances. On the other hand, a pure phosphorus dopant may also be difficult to control, as the small size of phosphorus leads to greater rates of diffusion and channeling. Therefore, a blend of arsenic and phosphorus may be used (either together or in any appropriate order of placement.) In this set of embodiments, arsenic may be used in conjunction with an n-type dopant other than arsenic. In accordance with the present invention, the arsenic component of this mixed dopant is controlled with respect to diffusion by the introduction of a carbon-containing arsenic diffusion suppressant, and optionally with respect to channeling by the use of an amorphizer (e.g., germanium.)
A demonstration of the properties described herein is provided in
The chart of
The method disclosed hereinabove describes the n-type doping of a target area in a semiconductor substrate. This method is illustrated in
Although the disclosure has been shown and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art based upon a reading and understanding of this specification and the annexed drawings. The disclosure includes all such modifications and alterations and is limited only by the scope of the following claims. In particular regard to the various functions performed by the above described components (assemblies, elements, devices, circuits, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the disclosure. In addition, while a particular feature of the disclosure may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.” Also, “exemplary” as utilized herein merely means an example, rather than the best.
