1. Field of the Invention
The present invention relates to user-programmable circuits. More particularly, the present invention relates to field programmable gate array (FPGA) integrated circuits and to arrangements for flip-flop and logic circuits in FPGA architectures.
2. The Prior Art
Modern FPGA functionality is provided by logic modules and flip-flops. Logic modules can be n-input look-up-tables (n-LUTs) or any other kind of function generators with n inputs, where (n>1). The flip-flops can be simple D type flip-flops, or they can have additional functionality such as CLEAR, RESET, LOAD, and ENABLE. These additional functions (with the exception of ENABLE) can be synchronous with the clock (CLK) or asynchronous (or both.)
Logic modules and flip-flops are often grouped into clusters that may typically vary in size from four to more than twenty. The clustering provides no additional functionality; it is done for routing convenience. In addition to the functionality provided by the logic modules and flip-flops, the FPGAs may include other types of functional blocks such as multipliers, RAMs, FIFOs, etc.
The most common arrangement of logic modules and flip-flops is shown in
The arrangement shown in
The packing limitations of the arrangement shown in
The arrangement shown in
Even though the arrangement shown in
According to one aspect of the present invention, a logic module and flip-flop arrangement includes a first input multiplexer having a plurality of data inputs coupled to routing resources, and an output. Second through nth input multiplexers, each have a plurality of data inputs coupled to routing resources, and an output. A clock multiplexer has a plurality of inputs coupled to clock resources, and an output. An input-select multiplexer has a plurality of inputs and an output, a first input of the data select multiplexer is coupled to the output of the first input multiplexer. A flip-flop has a clock input coupled to the output of the clock multiplexer, a data output coupled to a second input of the input-select multiplexer, and a data input. A logic module has a plurality of data inputs and an output, one data input of the logic module coupled to the output of the input select multiplexer, the other data inputs of the logic module are each coupled to the output of a different one of the second through nth input multiplexers. A flip-flop multiplexer having an output coupled to the data input of the flip-flop, a first input coupled to the output of the first input multiplexer, a second input coupled to the data output of the logic module, and a third input coupled to routing resources.
According to another aspect of the present invention, the flip-flop multiplexer includes fourth and fifth inputs coupled to routing resources.
According to another aspect of the present invention, the logic module further includes a sum output, a carry-in input and a carry-out output, and the flip-flop multiplexer further includes a sixth input coupled to the sum output of the logic module.
Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the invention will readily suggest themselves to such skilled persons.
The present invention addresses the limitations of prior-art architectures by enlarging the routing multiplexer in between the logic module and the flip-flop, and accepting one or more inputs from routing resources.
Referring now to
It has been verified that a single routing input to the flip-flop can increase the packing density by about 2.5%. The density can be increased even more by providing additional inputs to multiplexer 28 as shown in the illustrative embodiment of
The present invention may be used in connection with both clustered and non-clustered routing architectures. When used in clustered architectures, for cluster sizes ranging from eight to sixteen, having three inputs from the routing resources directly to flip-flop 12 that bypass logic module 10 as shown in
It has been found that providing more than three inputs, however, results in diminishing returns in terms of packing density increase, except for large cluster sizes (with 18 or more logic modules and flip-flops) and special types of FPGA designs that are unusually register rich. Besides, the larger the multiplexer between the logic module and the flip-flop becomes, the slower the multiplexer gets (even if it stays as a single level multiplexer), and it is not desirable to grow it by allowing for more than three inputs for general purpose FPGAs. For FPGAs specifically targeted for high register applications, however, this can be done.
Referring now to
The present invention performs well with only a few additional inputs to the multiplexer 28 between the logic module 10 and the flip-flop 12. Flip-flop/routing multiplexer 28 is in general much smaller than any of the multiplexers 14, 16, 18, and 20 that furnish the inputs to the logic module 10. This is explained by the way in which flip-flops are commonly used in logic designs programmed into FPGAs. It has been discovered that the most common mode of flip-flop usage is to drive the flip-flop from a logic module without fanout, or to drive a logic module by the flip-flop without fanout. These two cases combined account for nearly 70% of all flip-flop usage in FPGA designs. In fact these two cases can be handled very efficiently by the prior-art arrangement of
The present invention as illustratively shown in
While embodiments and applications of this invention have been shown and described, it would be apparent to those skilled in the art that many more modifications than mentioned above are possible without departing from the inventive concepts herein. The invention, therefore, is not to be restricted except in the spirit of the appended claims.
This application is a Continuation of co-pending U.S. patent application Ser. No. 12/360,971, filed Jan. 28, 2009, which claims priority to U.S. Provisional Patent Application Ser. No. 61/054,661, filed Jan. 30, 2008, the entirety of both of which are hereby incorporated by reference herein.
Number | Date | Country | |
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61024661 | Jan 2008 | US |
Number | Date | Country | |
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Parent | 12360971 | Jan 2009 | US |
Child | 12717315 | US |