Near natural breakdown device

Abstract

A semiconductor device includes a semiconductor region wherein the semiconductor region is a forced or non-forced Near Natural breakdown region, which is completely depleted when a predetermined voltage having a magnitude less than or equal to the breakdown voltage of a non-Natural breakdown (for example, Zener breakdown and Avalanche breakdown) is applied across the device.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic representation of conventional pn junction diode 100.

FIG. 2 shows the current (I) versus voltage (V) characteristics of a conventional pn junction diode.

FIG. 3 is a schematic representation of a forced near natural breakdown device (NNBD) 300, having a P-type region that is in a near natural breakdown condition before a natural breakdown voltage V_fbr is applied, according to one embodiment of the present invention.

FIG. 4 shows the current-voltage (IV) characteristics of NNBD 300.

FIG. 5( a) is a schematic representation of NNBD 500, an NPN transistor having a collector semiconductor region in near natural breakdown condition before a natural breakdown voltage V_{fbr NPN} is applied, according to one embodiment of the present invention.

FIG. 5( b) shows an expanded view of NNBD 500 when collector semiconductor region 501 is fully depleted under the natural breakdown condition.

FIG. 5( c) is a schematic representation of NNBD 510, a PNP transistor having a collector semiconductor region in near natural breakdown condition before a natural breakdown voltage V_{fbr PNP} V_{fbr NPN} according to one embodiment of the present invention.

FIG. 5( d) shows an expanded view of NNBD 510 when collector semiconductor region 511 is fully depleted under the natural breakdown condition.

FIG. 5( e) shows the collector current I_C versus V_CE IV curve for a bipolar transistor.

FIG. 5( f) is a schematic representation of NNBD 520, an NPN transistor having an emitter semiconductor region in near natural breakdown condition before a natural breakdown voltage V_fbr is applied, according to one embodiment of the present invention.

FIG. 5( g) shows an expanded view of NNBD 520 when the emitter semiconductor region is fully depleted under the natural breakdown condition.

FIG. 5( h) is a schematic representation of NNBD 530, an NPN transistor having both collector and emitter semiconductor regions in near natural breakdown condition before natural breakdown voltages are applied, according to one embodiment of the present invention.

FIG. 5( i) shows an expanded view of NNBD 530 when both collector and emitter semiconductor regions are fully depleted under the natural breakdown condition.

FIG. 5( j) is a schematic representation of NNBD 540, a PNP transistor having an emitter semiconductor region in near natural breakdown condition before a natural breakdown voltage V_fbr is applied, according to one embodiment of the present invention.

FIG. 5( k) shows an expanded view of NNBD 540 when the emitter semiconductor region is fully depleted under the natural breakdown condition.

FIG. 5( l) is a schematic representation of NNBD 550, a PNP transistor having both collector and emitter semiconductor regions in near natural breakdown condition before natural breakdown voltages are applied and an expanded view when both collector and emitter semiconductor regions are fully depleted under the natural breakdown condition, according to one embodiment of the present invention.

FIG. 6( a) is a schematic representation of NNBD 600, having an N-type region that is fully depleted at a reverse natural breakdown voltage V_fbr, according to one embodiment of the present invention.

FIG. 6( b) shows the current-voltage (IV) characteristics of NNBD 600.

FIG. 6( c) is a schematic-representation of NNBD 600, having an N-type region that is fully depleted at a reverse Natural breakdown voltage V_fbr, according to one embodiment of the present invention.

FIG. 7( a) is a schematic representation of NNBD 700 at zero applied bias voltage and at a reverse bias voltage of V_fbr, according to one embodiment of the present invention; NNBD 700 represents a forced near natural breakdown N-Schottky diode under a forced near natural breakdown condition.

FIG. 7( b) is a schematic representation of NNBD 710 at zero applied bias voltage and at reverse bias voltage of V_fbr, according to one embodiment of the present invention; NNBD 710 represents a forced near natural breakdown P-Schottky diode under a forced near natural breakdown condition.

FIGS. 8( a) and 8(c) show NNBD 800 and NNBD 820 each including one forced near natural breakdown region adjacent to a contact at zero bias voltage bias and at a natural breakdown voltage V_fbr.

FIGS. 8( b) and 8(d) show NNBD 810 and NNBD 830 each including two forced near natural breakdown regions each adjacent to a contact at zero bias voltage bias and at a natural breakdown voltage V_fbr.

FIG. 9 shows a table of NNBD structures and characteristics under bias voltage, according to the present invention.

FIG. 10( a) shows IV curve of NNBD 300 in forward current and forward bias voltage, when the V_fbr is at its smallest bias voltage (near-zero) to create a natural breakdown condition on p-region 301.

FIG. 10( b) shows IV curve of NNBD 300 in reverse current and reverse bias voltage, when the V_fbr is at its smallest bias voltage (near-zero) to create a natural breakdown condition on p-region 301.

Claims

1. A semiconductor device, comprising: a first region formed of a semiconductor material of a first conductivity type; anda second region adjacent the first region, wherein the first region becomes completely depleted when a predetermined voltage is applied across the first and second regions.

2. A semiconductor device as in claim 1, wherein the first conductivity type is n-type.

3. A semiconductor device as in claim 1, wherein the first conductivity type is p-type.

4. A semiconductor device as in claim 1, wherein the second region comprises a semiconductor material of a second conductivity type opposite in polarity to the first conductivity type.

5. A semiconductor device as in claim 4, wherin the second region becomes completely depleted when the predetermined voltage is applied across the first and second regions.

6. A semiconductor device as in claim 1, wherein the second region comprises a conductive material forming a schottky barrier to the first region.

7. A semiconductor device as in claim 1, further comprising a third region adjacent the second region, wherein the second region comprises a semiconductor material of a second conductivity type opposite in polarity to the first conductivity type, and wherein the third region comprises a semiconductor material of the first conductivity type.

8. A semiconductor device as in claim 7, wherein the first region, the second region and the third region form a bipolar transistor.

9. A semiconductor device as in claim 8, wherein the first region functions as an emitter for the bipolar transistor.

10. A semiconductor device as in claim 8, wherein the first region functions as a collector for the bipolar transistor.

11. A semiconductor device as in claim 7, wherein the third region provides an ohmic contact to the second region.

12. A semiconductor device as in claim 1, further comprising a third region adjacent the first region forming an ohmic contact with the first region.

13. A semiconductor device as in claim 12, further comprising a fourth region adjacent the second region forming an ohmic contact with the second regions.

14. A method for providing a semiconductor device, comprising: forming a first region from a semiconductor material of a first conductivity type; andforming a second region adjacent the first region, such that the first region becomes completely depleted when a predetermined voltage is applied across the first and second regions.

15. A method as in claim 14, wherein the first conductivity type is n-type.

16. A method as in claim 14, wherein the first conductivity type is p-type.

17. A method as in claim 14, wherein the second region is formed from a semiconductor material of a second conductivity type opposite in polarity to the first conductivity type.

18. A method as in claim 14, wherein the second region is formed from a metal, the second region thereby forming a schottky barrier to the first region.

19. A method as in claim 14, further comprising forming a third region adjacent the second region, wherein the second region comprises a semiconductor material of a second conductivity type opposite in polarity to the first conductivity type, and wherein the third region comprises a semiconductor of the first conductivity type.

20. A method as in claim 19, wherein the first region, the second region and the third region form a bipolar transistor.

21. A method as in claim 20, wherein the first region functions as an emitter for the bipolar transistor.

22. A method as in claim 20, wherein the first region functions as a collector for the bipolar transistor.

23. A method as in claim 19, wherein the third region provides an ohmic contact to the second region.

24. A method as in claim 14, further comprising forming a third region adjacent the first region, the third region forming an ohmic contact with the first region.

25. A method as in claim 24, further comprising forming a fourth region adjacent the second region, the fourth region forming an ohmic contact with the second regions.

26. A method for providing a natural breakdown condition within an existing semiconductor device, comprising: providing a first semiconductor region having a first doping concentration within the existing semiconductor device;providing a second region adjacent the first region within the existing semiconductor device;provding a predetermined voltage to create the natural breakdown condition;forming a width for the first semiconductor region such that the first semiconductor region becomes fully depleted when the predetermined voltage is applied across the first semiconductor region and the second regions.

27. A method to conduct current at a predetermined voltage using a depletion band, comprising: providing a first semiconductor region having a first doping concentration;providing a second region adjacent to the first semiconductor region such that the depletion band completely covers the first semiconductor region when the predetermined voltage is applied across the first semiconductor region and the second region.