NETWORK DEVICE CAPABLE OF ACTING AS PTP MASTER AND METHOD PERFORMED THEREBY

TECHNICAL FIELD

Embodiments of the disclosure generally relate to communication, and, more particularly, to network device capable of acting as precision time protocol (PTP) master and method performed thereby.

BACKGROUND

This section introduces aspects that may facilitate better understanding of the present disclosure. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is in the prior art or what is not in the prior art.

Global navigation satellite system (GNSS) covers global positioning system (GPS), Beidou, GLONASS, etc. When a GNSS receiver unit is powered, it searches for satellites on received radio frequency (RF) signals. Once the GNSS receiver unit locks to satellites, it will start to send one pulse per second (1PPS) and time of day (TOD) sentences towards its client via a TOD interface. After the client or node receives the 1PPS and TOD sentences, the node can take a grandmaster (GM) role and distribute sync to downstream.

International telecommunication union telecommunication standardization sector (ITU-T) V.11-based time/phase distribution interface including RJ-45 connector, 1PPS rise and fall time specification, performance specification, etc., are defined in section 19 of ITU-T G.703.

According to ITU-T G.8275.1, there are several types of clock shown in Table 1 below.

TABLE 1

Mapping between [ITU-T G.8275] and PTP clock types

Clock type from

Clock type from

[ITU-T G.8275]
Description
[IEEE 1588]

T-GM
Master-only ordinary clock
OC

(master with a single PTP port, always a GM, cannot be

slaved to another PTP clock)

Master-only boundary clock
BC

(master with multiple PTP ports, always a GM,

cannot be slaved to another PTP clock)

T-BC
Boundary clock
BC

(may become a GM, or may be slaved to another PTP

clock)

T-TSC
Slave-only ordinary clock
OC

(always a slave, cannot become a GM)

T-TC
Transparent clock
End-to-end TC

According to ITU-T G.8275.2, there are several types of clock shown in Table 2 below.

TABLE 2

Mapping between ITU-T G.8275.2 and PTP clock types

Clock type from

Clock type from

[ITU-T G.8275.2]
Description
[IEEE 1588]

T-GM
Master-only ordinary clock (master with a single PTP
OC

port, cannot be slaved to another PTP clock)

Master-only boundary clock (master with multiple
BC

PTP ports, cannot be slaved to another PTP clock)
(Note 1)

T-BC-P
Boundary clock (may become a GM, or may be slaved
BC

(partial)
to another PTP clock)

T-BC-A
Boundary clock assisted by a local time reference that
BC

(assisted partial)
is used as a primary source of time (may become a
(Note 2)

GM, or may be slaved to another PTP clock)

T-TSC-P
Slave-only, single port, ordinary clock
OC

(partial)
(always a slave)

PTP clock at the end of the PTP synchronization
BC

chain, multiple port clock
(Note 1)

T-TSC-A
Slave-only, single port, ordinary clock (always a
OC

(assisted partial)
slave) assisted by a local time reference that is used as
(Note 2)

a primary source of time

PTP clock at the end of the PTP synchronization
BC

chain, multiple port clock assisted by a local time
(Note 1)

reference that is used as a primary source of time
(Note 2)

NOTE 1 -

According to [IEEE 1588], a clock that has multiple PTP ports is by definition a boundary clock.

NOTE 2 -

Examples of a local time reference: PRTC or GNSS-based time source.

For a telecom grandmaster (T-GM), there is always a GNSS receiver inside of the T-GM. For a telecom boundary clock (T-BC) or assisted partial-support telecom boundary clock (T-BC-A) as a GM, there is usually a GNSS receiver integrated with it. The T-BC or T-BC-A can connect with the GNSS receiver via a TOD interface defined in G.703.

SUMMARY

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

One of the objects of the disclosure is to provide an improved network device capable of acting as a precision time protocol (PTP) master. In particular, one of the problems to be solved by the disclosure is that for the existing network device acting as a PTP master, its PTP performance may be degraded due to the unstable output performance of a global navigation satellite system (GNSS) receiver included in or connected with the network device.

According to a first aspect of the disclosure, there is provided a network device capable of acting as a PTP master. The network device may comprise or be connectable with a GNSS receiver for receiving a pulse timing signal. The network device may comprise a signal controller and a synchronization unit. The signal controller may be configured to detect whether the received pulse timing signal is in abnormal status, to generate and provide a normal pulse timing signal to the synchronization unit within a predetermined time period in response to detecting the received pulse timing signal to be in abnormal status, and to provide the received pulse timing signal to the synchronization unit in response to detecting the received pulse timing signal to be not in abnormal status. The synchronization unit may be configured to synchronize with the generated normal pulse timing signal or the received pulse timing signal.

In this way, the unstable problem of the GNSS receiver can be solved to improve the stability of the PTP master.

In an embodiment of the disclosure, the abnormal status may be a status where the received pulse timing signal is in outage. The signal controller may comprise a timer whose expiration time is the predetermined time period. The signal controller may be further configured to detect whether the received pulse timing signal is recovered to be normal when the predetermined time period has elapsed, and to trigger a first predetermined remedial operation when detecting the received pulse timing signal to be not recovered.

In an embodiment of the disclosure, the first predetermined remedial operation may comprise a PTP holdover or a switching to a backup clock source.

In an embodiment of the disclosure, the abnormal status may be a status where the received pulse timing signal is degraded. The predetermined time period may be a time period during which a predetermined number of consecutive pulse timing signals are detected in terms of occurrence or absence of degradation. The signal controller may be further configured to detect whether the received pulse timing signal is recovered to be normal when the predetermined number of consecutive pulse timing signals have been detected, and to trigger a second predetermined remedial operation when detecting the received pulse timing signal to be not recovered.

In an embodiment of the disclosure, the second predetermined remedial operation may comprise a PTP holdover, or a switching to a backup clock source, or a restart of the GNSS receiver.

In an embodiment of the disclosure, the signal controller may be further configured to provide the received pulse timing signal to the synchronization unit when detecting the received pulse timing signal to be recovered.

In an embodiment of the disclosure, the signal controller may comprise a high-stability oscillator, a high-frequency signal generator, a counter, a detector and a normal signal generator. The high-frequency signal generator may be configured to generate a high-frequency signal based on a clock signal from the high-stability oscillator. The counter may be configured to count a number of pulses of the high-frequency signal that occur between two predetermined edges of the received pulse timing signal. The detector may be configured to detect whether the received pulse timing signal is in abnormal status, based on the counted number of pulses of the high-frequency signal. The normal signal generator may be configured to generate a normal pulse timing signal based on the high-frequency signal.

In an embodiment of the disclosure, the high-stability oscillator may be a temperature compensation crystal oscillator (TCXO) or an oven controlled crystal oscillator (OCXO).

In an embodiment of the disclosure, the detector may be configured to detect the received pulse timing signal to be in abnormal status when a difference between the counted number of pulses of the high-frequency signal and a reference number of pulses of the high-frequency signal is not within a predetermined range. The normal signal generator may be configured to generate the normal pulse timing signal based on the high-frequency signal and the reference number of pulses of the high-frequency signal.

In an embodiment of the disclosure, the reference number of pulses of the high-frequency signal may be counted between two predetermined edges of the received pulse timing signal in normal status during a calibration process.

In an embodiment of the disclosure, the calibration process may be performed periodically.

In an embodiment of the disclosure, the high-frequency signal generator may be a phase locked loop (PLL) or a digital PLL (DPLL).

In an embodiment of the disclosure, the synchronization unit may be a PLL or a DPLL.

In an embodiment of the disclosure, the pulse timing signal may be a one pulse per second (1PPS) signal.

In an embodiment of the disclosure, the network device may further comprise a timestamp unit configured to generate timestamps for PTP messages based on clock signals from the synchronization unit.

In an embodiment of the disclosure, the network device may further comprise a local clock configured to maintain a local time based on clock signals from the synchronization unit, and a timestamp unit configured to generate timestamps for PTP messages based on the local time of the local clock.

In an embodiment of the disclosure, the network device may act as one of: a telecom grandmaster (T-GM), a telecom boundary clock (T-BC), and an assisted partial-support telecom boundary clock (T-BC-A).

According to a second aspect of the disclosure, there is provided a method performed by a network device capable of acting as a PTP master. The network device may comprise or be connectable with a GNSS receiver for receiving a pulse timing signal. The method may comprise detecting whether the received pulse timing signal is in abnormal status. The method may further comprise generating and providing a normal pulse timing signal to a synchronization unit of the network device within a predetermined time period in response to detecting the received pulse timing signal to be in abnormal status. The method may further comprise providing the received pulse timing signal to the synchronization unit in response to detecting the received pulse timing signal to be not in abnormal status.

In this way, the unstable problem of the GNSS receiver can be solved to improve the stability of the PTP master.

In an embodiment of the disclosure, the abnormal status may be a status where the received pulse timing signal is in outage. The method may further comprise detecting whether the received pulse timing signal is recovered to be normal when the predetermined time period has elapsed. The method may further comprise triggering a first predetermined remedial operation when detecting the received pulse timing signal to be not recovered.

In an embodiment of the disclosure, the first predetermined remedial operation may comprise a PTP holdover, or a switching to a backup clock source.

In an embodiment of the disclosure, the abnormal status may be a status where the received pulse timing signal is degraded. The predetermined time period may be a time period during which a predetermined number of consecutive pulse timing signals are detected in terms of occurrence or absence of degradation. The method may further comprise detecting whether the received pulse timing signal is recovered to be normal when the predetermined number of consecutive pulse timing signals have been detected. The method may further comprise triggering a second predetermined remedial operation when detecting the received pulse timing signal to be not recovered.

In an embodiment of the disclosure, the second predetermined remedial operation may comprise a PTP holdover, or a switching to a backup clock source, or a restart of the GNSS receiver.

In an embodiment of the disclosure, the method may further comprise providing the received pulse timing signal to the synchronization unit when detecting the received pulse timing signal to be recovered.

In an embodiment of the disclosure, detecting whether the received pulse timing signal is in abnormal status may comprise generating a high-frequency signal based on a clock signal from a high-stability oscillator of the network device. Detecting whether the received pulse timing signal is in abnormal status may further comprise counting a number of pulses of the high-frequency signal that occur between two predetermined edges of the received pulse timing signal. Detecting whether the received pulse timing signal is in abnormal status may further comprise detecting whether the received pulse timing signal is in abnormal status based on the counted number of pulses of the high-frequency signal. The normal pulse timing signal may be generated based on the high-frequency signal.

In an embodiment of the disclosure, the high-stability oscillator may be a TCXO or an OCXO.

In an embodiment of the disclosure, the received pulse timing signal may be detected to be in abnormal status when a difference between the counted number of pulses of the high-frequency signal and a reference number of pulses of the high-frequency signal is not within a predetermined range. The normal pulse timing signal may be generated based on the high-frequency signal and the reference number of pulses of the high-frequency signal.

In an embodiment of the disclosure, the calibration process may be performed periodically.

In an embodiment of the disclosure, the synchronization unit may be a PLL or a DPLL.

In an embodiment of the disclosure, the pulse timing signal may be a 1PPS signal.

In an embodiment of the disclosure, the network device may act as one of: a T-GM, a T-BC, and a T-BC-A.

According to a third aspect of the disclosure, there is provided a network device capable of acting as a PTP master. The network device may comprise or be connectable with a GNSS receiver for receiving a pulse timing signal. The network device may comprise at least one processor and at least one memory. The at least one memory may contain instructions executable by the at least one processor, whereby the network device may be operative to detect whether the received pulse timing signal is in abnormal status. The network device may be further operative to generate and provide a normal pulse timing signal to a synchronization unit of the network device within a predetermined time period in response to detecting the received pulse timing signal to be in abnormal status. The network device may be further operative to provide the received pulse timing signal to the synchronization unit in response to detecting the received pulse timing signal to be not in abnormal status.

In an embodiment of the disclosure, the network device may be operative to perform the method according to the above second aspect.

According to a fourth aspect of the disclosure, there is provided a computer program product. The computer program product may contain instructions which when executed by at least one processor, cause the at least one processor to perform the method according to the above second aspect.

According to a fifth aspect of the disclosure, there is provided a computer readable storage medium. The computer readable storage medium may store thereon instructions which when executed by at least one processor, cause the at least one processor to perform the method according to the above second aspect.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features and advantages of the disclosure will become apparent from the following detailed description of illustrative embodiments thereof, which are to be read in connection with the accompanying drawings.

FIG. 1 is a diagram illustrating the existing network device acting as a PTP master;

FIG. 2 is a diagram illustrating a scenario where the GNSS receiver related to a node has short outage;

FIG. 3 is a diagram illustrating a network device according to an embodiment of the disclosure;

FIG. 4 is a diagram for explaining the signal controller of FIG. 3;

FIG. 5 is a diagram illustrating a network device according to an embodiment of the disclosure;

FIG. 6 is a flowchart illustrating a method performed by a network device according to an embodiment of the disclosure;

FIG. 7 is a flowchart for explaining the method of FIG. 6;

FIG. 8 is a flowchart illustrating a method performed by a network device according to an embodiment of the disclosure;

FIG. 9 is a flowchart illustrating a method performed by a network device according to an embodiment of the disclosure;

FIG. 10 is a block diagram showing an apparatus suitable for use in practicing some embodiments of the disclosure;

FIG. 11 is a block diagram showing a network device according to an embodiment of the disclosure;

FIG. 12 is a block diagram for explaining the phase detector of FIG. 11;

FIG. 13 is a flowchart illustrating an exemplary process performed by the network device of FIG. 11; and

FIG. 14 is a flowchart illustrating an exemplary process performed by the network device of FIG. 11.

DETAILED DESCRIPTION

For the purpose of explanation, details are set forth in the following description in order to provide a thorough understanding of the embodiments disclosed. It is apparent, however, to those skilled in the art that the embodiments may be implemented without these specific details or with an equivalent arrangement.

FIG. 1 illustrates the existing network device acting as a PTP master. As shown, the network device 100 comprises or is connectable with a GNSS receiver 102. The network device 100 comprises a digital phase locked loop (DPLL) 104, a time of day (TOD) reception module 106, a local clock 108 and a timestamp unit 110. With this solution, the 1PPS signal from the ToD port of the GNSS receiver 102 is directly connected to the DPLL 104. The DPLL 104 can electrically lock to the input 1PPS signal. When the DPLL 104 is locked to the input 1PPS signal, it can distribute the locked signals to the local clock 108 for maintaining the local clock or to the timestamp unit 110 for timestamping. The ToD message from the GNSS receiver 102 can be received in the ToD reception module 106, and the ToD information may be set to the local clock 108 or the timestamp unit 110 to align the time. Thus, the clock and phase information on the timestamp unit 110 could be from the local clock 108 or the DPLL 104.

The signal from satellites is received by an antenna via radio. Due to some reasons, for example, sky view, weather, interference, etc., it may have frequency short outage during a period or bad signal. This will cause the GNSS receiver output to be unstable. When a T-GM, a T-BC or a T-BC-A (as a GM) is integrated with the GNSS receiver via the TOD port, the status of the GM may change due to the short outage, and the output performance may be degraded due to the bad signal.

There may be typically two failure cases needed to be considered. The first case is that the GNSS receiver has 1PPS short outage. Due to sky view, interference, or weather, etc., the GNSS receiver may stop the 1PPS signal for several seconds and be recovered for several times in a short period. This has an impact on the existing solution shown in FIG. 1. Specifically, with the existing solution, the DPLL will report lost lock of 1PPS and consequently PTP will lose GNSS reference, thereby either going into holdover or switching to a backup reference.

This change on PTP may cause network re-arrangement, in further to trigger sync chain changes on the network, especially for the case when Appendix V of G.8275.1 is applied. According to Appendix V of G.8275.1, the Acquiring clock mode, if included in an implementation, allows a T-GM or a T-BC to delay the distribution of GM information transmitted by the clock. The purpose of this Acquiring clock mode is to allow a T-GM or a T-BC some time to establish a timescale with acceptable accuracy before using it for the clock's node time.

For example, as shown in FIG. 2, if the GNSS receiver 2011 has short outage, then Node A may go into to holdover since there is no available source. Node B would switch to the backup GM 208, thereby changing to acquire state from the new clock source. Consequently, Nodes A, C, D, E, F and G would also change the source and clock state. This is a big impact for the PTP chain.

The second case is that the GNSS receiver has 1PPS signal degraded. That is, the 1PPS and ToD message are still there, but the quality of the 1PPS is degraded. For example, the 1PPS has an offset of several microseconds compared with the GPS phase in several second's period. This may also have a big impact on the Sync network. This is because with the existing solution of FIG. 1, the DPLL will follow this degraded 1PPS signal to set the local clock. The wrong phase information will take effect on the timestamp unit and be distributed to the downstream. This causes the whole PTP phase shifting on the chain, further causing service impact on radio base stations (RBSs).

The present disclosure proposes an improved network device capable of acting as a PTP master and a method performed thereby. Examples of the network device include, but not limited to, a switch, a router, a baseband device, a radio equipment, and the like. The network device may also be a “multiple services network device” that provides support for multiple networking functions (e.g., switching, routing, bridging, Layer 2 aggregation, session border control, quality of service, and/or subscriber management), and/or provides support for multiple application services (e.g., data, voice, and video). When carrying out PTP clock synchronization, the network device may act as any one of a telecom grandmaster (T-GM), a telecom boundary clock (T-BC), an assisted partial-support telecom boundary clock (T-BC-A), and the like. Hereinafter, the solution of the present disclosure will be described in detail with reference to FIGS. 3-14.

FIG. 3 is a diagram illustrating a network device according to an embodiment of the disclosure. As shown, the network device 300 may comprise or be connectable with a GNSS receiver 302 for receiving a pulse timing signal (e.g. a 1PPS signal). Thus, the network device is capable of acting as a PTP master. The network device 300 comprises a signal controller 304 and a synchronization unit 306. The signal controller 304 is configured to detect whether the received pulse timing signal is in abnormal status, to generate and provide a normal pulse timing signal to the synchronization unit 306 within a predetermined time period in response to detecting the received pulse timing signal to be in abnormal status, and to provide the received pulse timing signal to the synchronization unit 306 in response to detecting the received pulse timing signal to be not in abnormal status. The synchronization unit 306 is configured to synchronize with the generated normal pulse timing signal or the received pulse timing signal. For example, the synchronization unit 306 may be a PLL/DPLL, or any other circuit with similar functionality. With the network device of FIG. 3, the unstable problem of the GNSS receiver can be solved to improve the stability of the PTP master.

As a first case, the abnormal status is a status where the received pulse timing signal is in outage. For this first case, the signal controller 304 may comprise a timer 3046 whose expiration time is the predetermined time period, as shown in FIG. 4. The signal controller 304 may be further configured to detect whether the received pulse timing signal is recovered to be normal when the predetermined time period has elapsed, and to trigger a first predetermined remedial operation when detecting the received pulse timing signal to be not recovered. For example, the first predetermined remedial operation may comprise, but not limited to, a PTP holdover, or a switching to a backup clock source. The holdover may refer to an operating condition of a clock which has lost its controlling input and is using stored data, acquired while in locked operation, to control its output. On the other hand, the signal controller 304 may be further configured to provide the received pulse timing signal to the synchronization unit 306 when detecting the received pulse timing signal to be recovered.

As a second case, the abnormal status is a status where the received pulse timing signal is degraded (e.g. by a predetermined signal quality). For this second case, the predetermined time period may be a time period during which a predetermined number of consecutive pulse timing signals are detected in terms of occurrence or absence of degradation. The signal controller 304 may be further configured to detect whether the received pulse timing signal is recovered to be normal when the predetermined number of consecutive pulse timing signals have been detected, and to trigger a second predetermined remedial operation when detecting the received pulse timing signal to be not recovered. For example, the second predetermined remedial operation may comprise, but not limited to, a PTP holdover, or a switching to a backup clock source, or a restart of the GNSS receiver. On the other hand, the signal controller 304 may be further configured to provide the received pulse timing signal to the synchronization unit 306 when detecting the received pulse timing signal to be recovered.

For either of the above two cases, the signal controller 304 may comprise a high-stability oscillator 3041, a high-frequency signal generator 3042, a counter 3043, a detector 3044 and a normal signal generator 3045. For example, the high-stability oscillator 3041 may be a temperature compensation crystal oscillator (TCXO), or an oven controlled crystal oscillator (OCXO), or any other oscillator with similar performance. The high-frequency signal generator 3042 may be configured to generate a high-frequency signal based on a clock signal from the high-stability oscillator. For example, The high-frequency signal generator 3042 may be implemented as a PLL/DPLL, or any other circuit with similar functionality.

The counter 3043 may be configured to count a number of pulses of the high-frequency signal that occur between two predetermined edges of the received pulse timing signal. As an example, the two predetermined edges may be the rising edges of two consecutive pulse timing signals. As another example, the two predetermined edges may be the rising edge and the falling edge of one pulse timing signal. The counter 3043 may be implemented by using various hardware circuits such as field programmable gate array (FPGA), application specific integrated circuit (ASIC), or the like.

The detector 3044 may be configured to detect whether the received pulse timing signal is in abnormal status, based on the counted number of pulses of the high-frequency signal. For example, the detector 3044 may be configured to detect the received pulse timing signal to be in abnormal status when a difference between the counted number of pulses of the high-frequency signal and a reference number of pulses of the high-frequency signal is not within a predetermined range. Note that if the received pulse timing signal is in outage, the counted number of pulses of the high-frequency signal may increase constantly since there are no corresponding edges of the received pulse timing signal, so that the difference between the counted number and the reference number falls outside the predetermined range. The reference number of pulses of the high-frequency signal may be counted between two predetermined edges of the received pulse timing signal in normal status during a calibration process. Since the pulse timing signal received from the GNSS receiver is generally in normal status most of the time, the received pulse timing signal may be considered to be in normal status if the corresponding counted number of pulses remains unchanged or the difference between the counted number and the reference number falls within the predetermined range for a long enough time. Optionally, the calibration process may be performed periodically in order to cope with the possible aging of the high-stability oscillator. The detector 3044 may be implemented by using various hardware circuits such as field programmable gate array (FPGA), application specific integrated circuit (ASIC), or the like.

The normal signal generator 3045 may be configured to generate a normal pulse timing signal based on the high-frequency signal. For example, the normal signal generator 3045 may be configured to generate the normal pulse timing signal based on the high-frequency signal and the reference number of pulses of the high-frequency signal. The normal signal generator 3045 may be implemented by using various hardware circuits such as field programmable gate array (FPGA), application specific integrated circuit (ASIC), or the like.

FIG. 5 is a diagram illustrating a network device according to an embodiment of the disclosure. The network device is capable of acting as a PTP master. As shown, the network device 300′ may comprise or be connectable with a GNSS receiver 302 for receiving a pulse timing signal (e.g. a 1PPS signal). The network device 300′ comprises a signal controller 304, a synchronization unit 306, a local clock 308 and a timestamp unit 310. Thus, the difference between the network device 300′ and the network device 300 lies in that the component (e.g. the local clock 308 or the timestamp unit 310) related to timestamping is further shown in the network device 300′ of FIG. 5. As an example, the timestamp unit 310 may be configured to generate timestamps for PTP messages based on clock signals from the synchronization unit 306. As another example, the local clock 308 may be configured to maintain a local time based on clock signals from the synchronization unit. The timestamp unit 310 may be configured to generate timestamps for PTP messages based on the local time of the local clock.

FIG. 6 is a flowchart illustrating a method performed by a network device according to an embodiment of the disclosure. The network device may comprise or be connectable with a GNSS receiver for receiving a pulse timing signal (e.g. a 1PPS signal). Thus, the network device is capable of acting as a PTP master. At block 602, the network device detects whether the received pulse timing signal is in abnormal status. As a first case, the abnormal status may be a status where the received pulse timing signal is in outage. As a second case, the abnormal status may be a status where the received pulse timing signal is degraded. For either of the two cases, block 602 may be implemented as blocks 708-712 of FIG. 7.

At block 708, the network device generates a high-frequency signal based on a clock signal from a high-stability oscillator of the network device. For example, the high-stability oscillator may be a TCXO, or an OCXO, or any other oscillator with similar performance. The high-frequency signal may be generated by using a PLL/DPLL, or any other circuit with similar functionality. At block 710, the network device counts a number of pulses of the high-frequency signal that occur between two predetermined edges of the received pulse timing signal. For example, the number of pulses of the high-frequency signal may be counted by the counter 3043 described above.

At block 712, the network device detects whether the received pulse timing signal is in abnormal status based on the counted number of pulses of the high-frequency signal. For example, the received pulse timing signal may be detected to be in abnormal status when a difference between the counted number of pulses of the high-frequency signal and a reference number of pulses of the high-frequency signal is not within a predetermined range. The reference number of pulses of the high-frequency signal may be counted between two predetermined edges of the received pulse timing signal in normal status during a calibration process. Optionally, the calibration process may be performed periodically in order to cope with the possible aging of the high-stability oscillator.

At block 604, the network device generates and provides a normal pulse timing signal to a synchronization unit of the network device within a predetermined time period in response to detecting the received pulse timing signal to be in abnormal status. For instance, the normal pulse timing signal may be generated based on the high-frequency signal. As an exemplary example, the normal pulse timing signal may be generated based on the high-frequency signal and the reference number of pulses of the high-frequency signal. The synchronization unit may be a PLL/DPLL, or any other circuit with similar functionality. For the above first case where the received pulse timing signal is in outage, a timer whose expiration time is the predetermined time period may be started in response to detecting the received pulse timing signal to be in abnormal status. For the above second case where the received pulse timing signal is degraded, the predetermined time period may be a time period during which a predetermined number of consecutive pulse timing signals are detected in terms of occurrence or absence of degradation.

At block 606, the network device provides the received pulse timing signal to the synchronization unit in response to detecting the received pulse timing signal to be not in abnormal status. With the method of FIG. 6, the unstable problem of the GNSS receiver can be solved to improve the stability of the PTP master.

FIG. 8 is a flowchart illustrating a method performed by a network device according to an embodiment of the disclosure. The method may be applicable to the above first case where the received pulse timing signal is in outage. At block 814, the network device detects whether the received pulse timing signal is recovered to be normal when the predetermined time period has elapsed. For example, block 814 may be implemented in a way similar to block 602. At block 816, the network device triggers a first predetermined remedial operation when detecting the received pulse timing signal to be not recovered. For example, the first predetermined remedial operation may comprise, but not limited to, a PTP holdover, or a switching to a backup clock source. At block 818, the network device provides the received pulse timing signal to the synchronization unit when detecting the received pulse timing signal to be recovered.

FIG. 9 is a flowchart illustrating a method performed by a network device according to an embodiment of the disclosure. The method may be applicable to the above second case where the received pulse timing signal is degraded. At block 914, the network device detects whether the received pulse timing signal is recovered to be normal when the predetermined number of consecutive pulse timing signals have been detected. For example, block 914 may be implemented in a way similar to block 602. At block 916, the network device triggers a second predetermined remedial operation when detecting the received pulse timing signal to be not recovered. For example, the second predetermined remedial operation may comprise, but not limited to, a PTP holdover, or a switching to a backup clock source, or a restart of the GNSS receiver. At block 918, the network device provides the received pulse timing signal to the synchronization unit when detecting the received pulse timing signal to be recovered.

FIG. 10 is a block diagram showing an apparatus suitable for use in practicing some embodiments of the disclosure. For example, at least part of the network device described above may be implemented through the apparatus 1000. As shown, the apparatus 1000 may include a processor 1010, a memory 1020 that stores a program, and optionally a communication interface 1030 for communicating data with other external devices through wired and/or wireless communication.

The program includes program instructions that, when executed by the processor 1010, enable the apparatus 1000 to operate in accordance with the embodiments of the present disclosure, as discussed above. That is, the embodiments of the present disclosure may be implemented at least in part by computer software executable by the processor 1010, or by hardware, or by a combination of software and hardware.

The memory 1020 may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as semiconductor based memory devices, flash memories, magnetic memory devices and systems, optical memory devices and systems, fixed memories and removable memories. The processor 1010 may be of any type suitable to the local technical environment, and may include one or more of general purpose computers, special purpose computers, microprocessors, digital signal processors (DSPs) and processors based on multi-core processor architectures, as non-limiting examples.

FIG. 11 is a block diagram showing a network device according to an embodiment of the disclosure. As shown, the network device 1100 may comprise or be connectable with a GNSS receiver 1102 for receiving a 1PPS signal. Thus, the network device 1100 is capable of acting as a PTP master. The network device 1100 comprises a phase detector 1112, a high-stability oscillator 1114, a DPLL 1104, a ToD reception module 1106, a local clock 1108 and a timestamp unit 1110. Compared with the existing network device 100 of FIG. 1, it can be seen that a hardware (HW) phase detector 1112 is added between the GNSS receiver 1102 and the DPLL 1104 in this embodiment. Thus, the signal controller 304 of FIG. 3 is implemented as including the phase detector 1112, the high-stability oscillator 1114, and some part of the software (SW) described later in this embodiment. The newly added phase detector 1112 may be a FPGA or an ASIC chip. The clock source of the phase detector 1112 may be a high-stability oscillator such as a TCXO, an OCXO, or any other oscillator with stable frequency accuracy. The phase detector 1112 may be configured to detect a GNSS receiver failure event (e.g. short outage, or signal degradation) and simulate a correct (or normal) 1PPS signal to the DPLL 1104. With the network device 1100, the impact when the GNSS receiver is unstable (which may be caused by sky view, weather, interference, etc.) can be mitigated. This, in turn, is very helpful for the stability of the sync network.

From the oscillator point of view, the frequency stability of a crystal oscillator is greatly affected by temperature, and the frequency stability of any crystal oscillator decreases with aging time. Thus, e.g. a TCXO or an OCXO available in market may be used for achieving high frequency stability. For example, some OCXO frequency stability can reach+−3 ppb daily over −40° C.˜85° C.

From the software (SW) point of view, there may be three sub-modules inside the phase detector 1112. The first sub-module is a hold-off timer so that if 1PPS short outage happens, the network device or the node waits for specific hold-off time before going to holdover or switching to a backup source. The second sub-module is a degradation counter so that when a predetermined number of consecutive 1PPS signals are detected by the phase detector 1112 and thus the degradation counter reaches the predetermined number (which may be configurable), the phase detector 1112 can stop to simulate a correct 1PPS signal to the DPLL 1104. The third sub-module is a GNSS receiver restart module. In case that the GNSS receiver can support remote restart, this function may be supported by the third sub-module to restart the GNSS receiver. Optionally, from the SW point of view, there may be a command or instruction for controlling the enabling or disabling of the phase detector (or the GNSS receiver performance detector).

FIG. 12 illustrates an exemplary example for the phase detector of FIG. 11. As shown, the phase detector 1112 may comprise a PLL 1201, a counter 1202, a detecting component 1203 and a 1PPS generator 1204. The PLL 1201 (e.g. an internal PLL) may be used to generate a high frequency clock signal (H_CLK) which is locked with the high-stability oscillator 1114. The counter 1202 may comprise a counting component 1205 and a latch 1206. The counting component 1205 may be driven by the H_CLK signal to count the pulses of the H_CLK signal that occur in the interval between two GNSS receiver 1PPS rising edges, so as to get the counter value per second. The counter value may be latched by the latch 1206 and provided to the detecting component 1203. Note that in the calibration process, the counter value obtained when the GNSS receiver 1102 is working normally may be used as the reference counter value for detecting abnormality in the 1PPS signal. In order to improve the accuracy, the frequency of the H_CLK signal may be as higher as possible and multiple cycles of 1PPS can be counted. The above actions may be executed periodically to eliminate the deviation produced by the counter due to the frequency granularity of H_CLK and to reduce the impact of the oscillator aging.

The phase detecting component 1203 may detect whether the phase error between the current counter value and the reference counter value is not within a predetermined range. When detecting that the GNSS receiver 1102 is unstable (e.g. when the phase error is not within the predetermined range), the 1PPS generator 1204 may be triggered to generate and provide an accurate 1PPS to the DPLL 1104. On the other hand, when detecting that the GNSS receiver 1102 is stable, the received 1PPS signal may be provided to the DPLL 1104.

FIG. 13 is a flowchart illustrating an exemplary process performed by the network device of FIG. 11. This process corresponds to the above first case where the GNSS receiver has short outage. As shown, the 1PPS signal is provided to the phase detector 1112 from the GNSS receiver 1102. The phase detector 1112 checks each 1PPS signal at block 1301. If the 1PPS signal is correct or in good performance, without loss of signal (LOS) and signal degradation, the 1PPS signal is transmitted to the DPLL 1104 as the input source of the DPLL 1104 at block 1302. On the other hand, if the phase detector 1112 detects that there is 1PPS LOS, both the phase detector and the SW start a holdoff timer at block 1303. The holdoff timer could be configurable and start with a default value.

Whether the holdoff timer has expired may be determined at block 1304. If the result of the determination is negative (i.e. during the holdoff timer period), the phase detector 1112 simulates and provides a 1PPS signal to the DPLL 1104 based on the high-stability oscillator at block 1305. On the other hand, if the holdoff timer has expired, the phase detector 1112 detects the quality of the 1PPS signal at block 1306.

If the 1PPS signal is recovered and correct, the phase detector 1112 transmits the 1PPS signal to the DPLL 1104 as the input source of the DPLL 1104 at block 1307. On the other hand, if the 1PPS signal is still LOS, the phase detector 1112 informs the SW of this event. The SW forces to holdover or switch to a backup clock source (if there is a backup) at block 1308.

FIG. 14 is a flowchart illustrating an exemplary process performed by the network device of FIG. 11. This process corresponds to the above second case where the 1PPS signal from the GNSS receiver is degraded. As shown, the 1PPS signal is provided to the phase detector 1112 from the GNSS receiver 1102. The phase detector 1112 checks each 1PPS signal at block 1401. If the 1PPS signal is correct or in good performance, without LOS and signal degradation, the signal is transmitted to the DPLL 1104 as the input source of the DPLL 1104 at block 1402. On the other hand, if the phase detector 1112 detects that the 1PPS signal has been degraded, N consecutive 1PPS signals are detected at block 1404, where N is a predetermined number. If the number of the degraded 1PPS signals is less than N, the phase detector 1112 simulates and provides a 1PPS signal to the DPLL 1104 based on the high-stability oscillator at block 1405.

If the number of the degraded signals is equal to N, whether the 1PPS signal still has degradation is checked at block 1406. If no degraded signal is detected any more, the phase detector 1112 transmits the 1PPS signal to the DPLL 1104 as the input source of the DPLL 1104 at block 1407. On the other hand, if the degraded signal still exists, the phase detector 1112 informs the SW of this event. The SW may force to holdover or switch to the backup clock source (if there is a backup) at block 1408. Alternatively or additionally, the SW may reset the GNSS receiver (if it supports remote control) or report an alarm for operation to manually reset the GNSS receiver or replace it with a new GNSS receiver at block 1409.

In general, the various exemplary embodiments may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the disclosure is not limited thereto. While various aspects of the exemplary embodiments of this disclosure may be illustrated and described as block diagrams, flow charts, or using some other pictorial representation, it is well understood that these blocks, apparatus, systems, techniques or methods described herein may be implemented in, as non-limiting examples, hardware, software, firmware, special purpose circuits or logic, general purpose hardware or controller or other computing devices, or some combination thereof.

As such, it should be appreciated that at least some aspects of the exemplary embodiments of the disclosure may be practiced in various components such as integrated circuit chips and modules. It should thus be appreciated that the exemplary embodiments of this disclosure may be realized in an apparatus that is embodied as an integrated circuit, where the integrated circuit may comprise circuitry (as well as possibly firmware) for embodying at least one or more of a data processor, a digital signal processor, baseband circuitry and radio frequency circuitry that are configurable so as to operate in accordance with the exemplary embodiments of this disclosure.

It should be appreciated that at least some aspects of the exemplary embodiments of the disclosure may be embodied in computer-executable instructions, such as in one or more program modules, executed by one or more computers or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types when executed by a processor in a computer or other device. The computer executable instructions may be stored on a computer readable medium such as a hard disk, optical disk, removable storage media, solid state memory, RAM, etc. As will be appreciated by one skilled in the art, the function of the program modules may be combined or distributed as desired in various embodiments. In addition, the function may be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits, field programmable gate arrays (FPGA), and the like.

References in the present disclosure to “one embodiment”, “an embodiment” and so on, indicate that the embodiment described may include a particular feature, structure, or characteristic, but it is not necessary that every embodiment includes the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to implement such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

It should be understood that, although the terms “first”, “second” and so on may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and similarly, a second element could be termed a first element, without departing from the scope of the disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed terms.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “has”, “having”, “includes” and/or “including”, when used herein, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components and/or combinations thereof. The terms “connect”, “connects”, “connecting” and/or “connected” used herein cover the direct and/or indirect connection between two elements. It should be noted that two blocks shown in succession in the above figures may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved.

The present disclosure includes any novel feature or combination of features disclosed herein either explicitly or any generalization thereof. Various modifications and adaptations to the foregoing exemplary embodiments of this disclosure may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings. However, any and all modifications will still fall within the scope of the non-Limiting and exemplary embodiments of this disclosure.

NETWORK DEVICE CAPABLE OF ACTING AS PTP MASTER AND METHOD PERFORMED THEREBY

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