Patent Application
20080040519
The following specification describes a TCP/IP offload network interface device called Sahara, which is capable of full duplex data transfer rates of at least ten-gigabits/second. This Introduction highlights a few of the features of Sahara, which are more fully described throughout the remainder of the document.
As shown in the upper-left-corner of
In the particular 10 G/s physical layer embodiment of XAUI, data is striped over 4 channels, encoded with an embedded clock signal then sent in a serial fashion over differential signals. Although a 10 Gb/S data rate is targeted, higher and lower data rates are possible.
In this embodiment, the data is received from XAUI by Receive XGMII Extender Sublayer (RcvXgx) hardware, aligned, decoded, re-assembled and then presented to the Receive media access control (MAC) hardware (RcvMac). In this embodiment, the Receive MAC (RcvMac) is separated from the Transmit MAC (XmtMac), although in other embodiments the Receive and Transmit MACs may be combined.
The Receive MAC (RcvMac) performs known MAC layer functions on the data it has received, such as MAC address filtering and checking the format of the data, and stores the appropriate data and status in a Receive MAC Queue (RcvMacQ). The Receive MAC Queue (RcvMacQ) is a buffer that is located in the received data path between the Receive MAC (RcvMac) and the Receive Sequencer (RSq).
The Receive Sequencer (RSq) includes a Parser (Prs) and a Socket Detector (Det). The Parser reads the header information of each packet stored in the Receive MAC Queue (RcvMacQ). A FIFO stores IP addresses and TCP ports of the packet, which may be called a socket, as assembled by the parser. The Socket Detector (Det) uses the IP addresses and TCP ports, stored in the FIFO, to determine whether that packet corresponds to a TCP Control Block (TCB) that is being maintained by Sahara. The Socket Detector compares the packet socket information from the FIFO against TCB socket information stored in the Socket Descriptor Ram (SktDscRam) to determine TCB association of the packet. The Socket Detector (Det) may utilize a hash bucket similar to that described in U.S. Published Patent Application No. 20050182841, entitled “Generating a hash for a TCP/IP offload device,” to detect the packet's TCB association. Compared to prior art TNICs, that used a processor to determine that a packet corresponds to a TCB, this hardware Socket Detector (Det) frees the chip's processor for other tasks and increases the speed with which packet-TCB association can be determined.
The Receive Sequencer's (RSq) Socket Detector (Det) creates a Receive Event Descriptor for the received packet and stores the Receive Event Descriptor in a Receive Event Queue implemented in the Dma Director (Dmd) block. The Receive Event Descriptor comprises a TCB identifier (TCBID) that identifies the TCB to which the packet corresponds, and a Receive Buffer ID that identifies where, in Dram, the packet is stored. The Receive Event Descriptor also contains information derived by the Receive Sequencer (RSq), such as the Event Code (EvtCd), Dma Code (DmaCd) and Socket Receive Indicator (SkRcv). The Receive Event Queue (RcvEvtQ) is implemented by a Dma Director (Dmd) that manages a variety of queues, and the Dma Director (Dmd) notifies the Processor (CPU) of the entry of the Receive Event Descriptor in the Receive Event Queue (RcvEvtQ).
Once the CPU has accessed the Receive Event Descriptor stored in the Receive Event Queue (RcvEvtQ), the CPU can check to see whether the TCB denoted by that descriptor is cached in Global Ram (GRm) or needs to be retrieved from outside the chip, such as off-chip memory or host memory. The CPU also schedules a DMA to bring the header from the packet located in Dram into Global Ram (GRm), which in this embodiment is dual port SRAM. The CPU then accesses the IP and TCP headers to process the frame and perform state processing that updates the corresponding TCB. The CPU contains specialized instructions and registers designed to facilitate access and processing of the headers in the header buffers by the CPU. For example, the CPU automatically computes the address for the header buffer and adds to it the value from an index register to access header fields within the header buffer.
Queues are implemented in a Queue RAM (QRm) and managed jointly by the CPU and the DMA Director (Dmd). DMA events, whether instituted by the CPU or the host, are maintained in Queue RAM (Qrm) based queues.
The CPU is pipelined in this embodiment, with 8 CPUs sharing hardware and each of those CPUs occupying a different pipeline phase at a given time. The 8 CPUs also share 32 CPU Contexts. The CPU is augmented by a plurality of functional units, including Event Manager (EMg), Slow Bus Interface (Slw), Debugger (Dbg), Writable Control Store (WCS), Math Co-Processor (MCp), Lock Manager (LMg), TCB Manager (TMg) and Register File (RFl). The Event Manager (EMg) processes external events, such as DMA Completion Event (RspEvt), Interrupt Request Event (IntEvt), Receive Queue Event (RcvEvt) and others. The Slow Bus Interface (Slw) provides a means to access non-critical status and configuration registers. The Writable Control Store (WCS) includes microcode that may be rewritten. The Math Co-Processor (MCp) divides and multiplies, which may be used for example for TCP congestion control.
The Lock Manager (LMg) grants locks to the various CPUs, and maintains an ordered queue which stores lock requests allowing allocation of locks as they become available. Each of the locks is defined, in hardware or firmware, to lock access of a specific function. For example, the Math Co-Processor (MCp) may require several cycles to complete an operation, during which time other CPUs are locked out from using the Math Co-Processor (MCp). Maintaining locks which are dedicated to single functions allows better performance as opposed to a general lock which serves multiple functions.
The Event Manager (EMg) provides, to the CPU, a vector for event service, significantly reducing idle loop instruction count and service latency as opposed to single event polling performed by microcode in previous designs. That is, the Event Manager (EMg) monitors events, prioritizes the events and presents, to the cpu, a vector which is unique to the event type. The CPU uses the vector to branch to an event service routine which is dedicated to servicing the unique event type. Although the Event Manager (EMg) is configured in hardware, some flexibility is built in to enable or disable some of the events of the Event Manager (EMg). Examples of events that the Event Manager (EMg) checks for include: a system request has occurred over an I/O bus such as PCI; a DMA channel has changed state; a network interface has changed state; a process has requested status be sent to the system; and a transmitter or receiver has stored statistics.
As a further example, one embodiment provides a DMA event queue for each of 32 CPU contexts, and an idle bit for each CPU context indicating whether that context is idle. For the situation in which the idle bit for a context is set and the DMA event queue for that context has an event (the queue is not empty), the Event Manager (EMg) recognizes that the event needs to be serviced, and provides a vector for that service. Should the idle bit for that context not be set, instead of the Event Manager (EMg) initiating the event service, firmware that is running that context can poll the queue and service the event.
The Event Manager (EMg) also serves CPU contexts to available CPUs, which in one embodiment can be implemented in a manner similar to the Free Buffer Server (FBS) that is described below. A CPU Context is an abstract which represents a group of resources available to the CPUs only when operating within the context. Specifically, a context specifies a specific set of resources comprising CPU registers, a CPU stack, DMA descriptor buffers, a DMA event queue and a TCB lock request. When a CPU is finished with a context, it writes to a register, the CPU Context ID, which sets a flip-flop indicating that the context is free. Contexts may be busy, asleep, idle (available) or disabled.
The TCB Manager (TMg) provides hardware that manages TCB accesses by the plurality of CPUs and CPU Contexts. The TCB Manager (TMg) facilitates TCB locking and TCB caching. In one embodiment, 8 CPUs with 32 CPU Contexts can together be processing 4096 TCBs, with the TCB Manager (TMg) coordinating TCB access. The TCB Manager (TMg) manages the TCB cache, grants locks to processor contexts to work on a particular TCB, and maintains order for lock requests by processor contexts to work on a TCB that is locked.
The order that is maintained for lock requests can be affected by the priority of the request, so that high priority requests are serviced before earlier received requests of low priority. This is a special feature built into the TCB Manager (TMg) to service receive events, which are high priority events. For example, two frames corresponding to a TCB can be received from a network. While the TCB is locked by the first processor context that is processing the first receive packet, a second processor context may request a lock for the same TCB in order to process a transmit command. A third processor context may then request a lock for the same TCB in order to process the second receive frame. The third lock request is a high priority request and will be given a place in the TCB lock request chain which will cause it to be granted prior to the second, low priority, lock request. The lock requests for the TCB are chained, and when the first CPU context, holding the initial lock gets to a place where it is convenient to release the lock of the TCB, it can query the TCB Manager (TMg) whether there are any high priority lock requests pending. The TCB Manager (TMg) then can release the lock and grant a new lock to the CPU context that is waiting to process the second receive frame.
Sequence Servers issue sequential numbers to CPUs during read operations. Used as a tag to maintain the order of receive frames. Also used to provide a value to insert into the IP header Identification field of transmit frames.
Composite Registers are virtual registers comprising a concatenation of values read from or to be written to multiple single content registers. When reading a Composite Register, short fields read from multiple single content registers are aligned and merged to form a 32 bit value which can be used to quickly issue DMA and TCB Manager (TMg) commands. When writing to Composite Registers, individual single content registers are loaded with short fields which are aligned after being extracted from the 32-bit ALU output. This provides a fast method to process Receive Events and DMA Events. The single content registers can also be read and written directly without use of the Composite Register.
A Transmit Sequencer (XSq) shown in the upper right portion of
In a current embodiment, the CPU can initiate DMA of an unmodified prototype header from a host memory resident TCB to a transmit buffer and initiate DMA of transmit data from host memory to the same transmit buffer. While the DMAs are taking place, the CPU can write a transmit command, comprising a command code and header modification data, to a proxy buffer. When the DMAs have completed the CPU can add DMA accumulated checksum to the proxy buffer then initiate DMA of the proxy buffer contents (transmit command) to the Transmit Command Queue (XmtCmdQ). The Transmit Sequencer (XSq) Dispatcher (Dsp) removes the transmit command from the Transmit Command Queue (XmtCmdQ) and presents it to the Dram Controller (DrmCtl) which copies the header modification portion to the XmtDmaQ then copies header and data from the transmit buffer to the XmtDmaQ. The Transmit Sequencer (XSq) Formatter (Fmt) removes header modification data, transmit header and transmit data from the Transmit DMA Queue (XmtDmaQ), merges the header modification data with the transmit header then forwards the modified transmit header to the Transmit Mac Queue (XmtMacQ) followed by transmit data. Transmit header and transmit data are read from the Transmit Mac Queue (XmtMacQ) by a Transmit MAC (XmtMac) for sending on XAUI.
For the situation in which device memory is sufficient to store all the TCBs handled by the device, e.g., 4096 TCBs in one embodiment, as opposed to only those TCBs that are currently cached. In one embodiment, instead of a queue of descriptors for free buffers that are available, a Free Buffer Server (FBS) is utilized that informs the CPU of buffers that are available. The Free Buffer Server (FBS) maintains a set of flip-flops that are each associated with a buffer address, with each flip-flop indicating whether its corresponding buffer is available to store data. The Free Buffer Server (FBS) can provide to the CPU the buffer address for any buffer whose flip-flop is set. The list of buffers that may be available for storing data can be divided into groups, with each of the groups having a flip-flop indicating whether any buffers are available in that group. The CPU can simply write a buffer number to the Free Buffer Server (FBS) to free a buffer, which sets a bit for that buffer and also sets a bit in the group flip-flop for that buffer. To find a free buffer, the Free Buffer Server (FBS) looks first to the group bits, and finding one that is set then proceeds to check the bits within that group, flipping the bit when a buffer is used and flipping the group bit when all the buffers in that group have been used. The Free Buffer Server (FBS) may provide one or more available free buffer addresses to the CPU in advance of the CPU's need for a free buffer or may provide free buffers in response to CPU requests.
Such a Free Buffer Server (FBS) can have N levels, with N=1 for the case in which the buffer flip-flops are not grouped. For example, 2 MB of buffer space may be divided into buffers having a minimum size that can store a packet, e.g., 1.5 KB, yielding about 1,333 buffers. In this example, the buffer identifications may be divided into 32 groups each having 32 buffers, with a flip-flop corresponding to each buffer ID and to each group. In another example, 4096 buffers can be tracked using 3 levels with 8 flips-flops each. Although the examples given are in a networking environment, such a free-buffer server may have applications in other areas and is not limited to networking.
The host interface in this embodiment is an eight channel implementation of PciExpress (PciE) which provides 16 Gb of send and 16 Gb of receive bandwidth. Similar in functional concept to previous Alacritech TNICs, Sahara differs substantially in it's architectural implementation. The receive and transmit data paths have been separated to facilitate greater performance. The receive path includes a new socket detection function mentioned above, and the transmit path adds a formatter function, both serving to significantly reduce firmware instruction count. Queue access is now accomplished in a single atomic cycle unless the queue-indirect feature is utilized. As mentioned above, TCB management function has been added which integrates the cam, chaining and TCB Lock functions as well as Cache Buffer allocation. A new event manager function reduces idle-loop instruction count to just a few instructions. New statistics registers, automatically accumulate receive and transmit vectors. The receive parsing function includes multicast filtering and, for support of receive-side-scaling, a toeplitz hash generator. The Director provides compact requests for initiating TCB, SGL and header DMAs. A new CPU increases the number of pipeline stages to eight, resulting in single instruction ram accesses while improving operating frequency. Adding even more to performance are the following enhancements of the CPU:
Parity has been implemented for all internal rams to ensure data integrity. This has become important as silicon geometries decrease and alpha particle induced errors increase.
Sahara employs several, industry standard, interfaces for connection to network, host and memory. Following is a list of interface/transceiver standards employed:
Sahara is implemented using flip-chip technology which provides a few important benefits. This technology allows strategic placement of I/O cells across the chip, ensuring that the die area is not pad-limited. The greater freedom of I/O cell and ram cell placement also reduces connecting wire length thereby improving operating frequency.
External devices are employed to form a complete TNIC solution.
A functional block diagram of Sahara is shown in
In short, Sahara performs all the functions of a traditional NIC as well as performing offload of TCP/IP datapath functions. The CPU manages all functions except for host access of flash memory, phy management registers and pci configuration registers.
Frames which do not include IP datagrams are processed as would occur with a non-offload NIC. Receive frames are filtered based on link address and errors, then transferred to preallocated receive buffers within host memory. Outbound frames are retrieved from host memory, then transmitted.
Frames which include IP datagrams but do not include TCP segments are transmitted without any protocol offload but received frames are parsed and checked for protocol errors. Receive frames without datagram errors are passed to the host and error frames are dumped. Checksum accumulation is also supported for Ip datagram frames containing UDP segments.
Frames which include Tcp segments are parsed and checked for errors. Hardware checking is then performed for ownership of the socket state. Tcp/Ip frames which fail the ownership test are passed to the host system with a parsing summary. Tcp/Ip frames which pass the ownership test are processed by the finite state machine (FSM) which is implemented by the TNIC CPU. Tcp/Ip frames for non-owned sockets are supported with checksum accumulation/insertion.
The following is a description of the steps which occur while processing a receive frame.
Receive Mac
The following is a description of the steps which occur while processing a transmit frame.
CPU
Host memory provides storage for control data and packet payload. Host memory data structures have been defined which facilitate communication between Sahara and the host system. Sahara hardware includes automatic computation of address and size for access of these data structures resulting in a significant reduction of firmware overhead. These data structures are defined below.
TCP Control Block
TCBs comprise constants, cached-variables and delegated-variables which are stored in host memory based TCB Buffers (TcbBuf) that are fixed in size at 512 B. A diagram of TCB Buffer space is shown in
Constants and cached-variables are read-only, but delegated variables may be modified by the CPUs while the TCB is cached. All TCBs are eventually flushed from the cache at which time, if any delegated-variable has been modified, the changed variable must be copied back to the TcbBuf. This is accomplished with a special DMA operation which copies to the TcbBuf, from the CchBuf, all delegated variables and incidental cached variables up to the next 32B boundary. The DMA operation copies an amount of data determined by the configuration constant G2hTcbSz. This constant should be set to a multiple of 32 B to preclude read-modify-write operations by the host memory controller. To this same end, delegated variables are located at the beginning of the TcbBuf to ensure that DMAs start at a 64-byte boundary. Refer to sections Global Ram, DMA Director and Slow Bus Controller for additional information.
Prototype Headers
Every connection has a Prototype Header (PHdr) which is not cached in GlbRam but is instead copied from host memory to DRAM transmit buffers as needed. Headers for all connections reside in individual, 1 KB Composite Buffers (CmpBuf,
Special DMA operations have been defined, for copying prototype headers to transmit buffers. A host address is computed using the configuration constant—Composite Buffer Base Address (CmpBBs), with a fixed buffer size of 1 KB. Another configuration constant, prototype-header transmit DMA-size (H2dHdrSz), indicates the size of the copy. Refer to sections DMA Director and Slow Bus Controller for additional information.
TCB Receive Queue
Every connection has a unique TCB Receive Queue (TRQ) in which to store information about buffered receive packets or frames. The TRQ is allocated storage space in the TRQ reserved area of the composite buffers previously defined. The TRQ size is programmable and can be up to 768-bytes deep allowing storage of up to 192 32-bit descriptors. This is slightly more than needed to support a 256 KB window size assuming 1448-byte payloads with the timestamp option enabled.
When a TCB is ejected from or imported to a GlbRam TCB Cache Buffer (CchBuf), its corresponding receive queue may or may not contain entries. The receive queue can be substantially larger than the TCB and therefore contribute greatly to latency. It is for this reason that the receive queue is copied only when it contains entries. It is expected that this DMA seldom occurs and therefore there is no special DMA support provided.
Transmit Commands.
Transmit Command Descriptors (XmtCmd,
The command descriptor includes a Scatter-Gather List Read Pointer (SglPtr, Fig. xx-a), a 4-byte reserved field, a 2-byte Flags field (Flgs), a 2-byte List Length field (LCnt), a 12-byte memory descriptor and a 4-byte reserved field. The definition of the contents of Flgs is beyond the scope of this document. The SglPtr is used to fetch page descriptors from a scatter-gather list and points to the second page descriptor of the list. MernDsc[0] is a copy of the first entry in the SGL and is placed here to reduce latency by consolidating what would otherwise be two DMAs. LCnt indicates the number of entries in the SGL and includes MemnDsc[0]. A value of zero indicates that no data is to be transferred.
The host compiles the command descriptor or descriptors in the appropriate ring then notifies Sahara of the new command(s) by writing a value, indicating the number of new command descriptors, to the transmit tickle register of the targeted connection. Microcode adds this incremental value to a Transmit Ring Count (XRngCnt) variable in the cached TCB. Microcode determines command descriptor readiness by testing XRngCnt and decrements it each time a command is fetched from the ring.
Commands are fetched using an address computed with the Transmit Ring Pointer (XRngPtr), fetched from the cached TCB, and the configuration constants Transmit Ring Base address (XRngBs) and Transmit Rings Size (XRngSz). XRngPtr is then incremented by the DMA Director. Refer to sections Global Ram, DMA Director and Slow Bus Controller for additional information.
Receive Commands.
Receive Command Descriptors (RcvCmd,
The host compiles the command descriptor or descriptors in the appropriate ring then notifies Sahara of the new command(s) by writing a value, indicating the number of new command descriptors, to the receive tickle register of the targeted connection. Microcode adds this incremental value to a Receive Ring Count (RRngCnt) variable in the cached TCB. Microcode determines command readiness by testing RRngCnt and decrements it each time a command is fetched from the ring.
Commands are fetched using an address computed with the Receive Ring Pointer (RRngPtr), fetched from the cached TCB, and the configuration constants Receive Ring Base address (RRngBs) and Receive Ring Size (RRngSz). RRngPtr is then incremented by the DMA Director. Refer to sections Global Ram, DMA Director and Slow Bus Controller for additional information.
Scatter-Gather Lists.
A Page Descriptor is shown in
Memory descriptors in the host include an 8-byte Physical Address (PhyAd,
System Buffer Descriptor Lists.
A System Buffer Descriptor is shown in
Microcode schedules, as needed, a DMA of a SbfDsc list into the SbfDsc list staging area of the GlbRam. Microcode then removes individual descriptors from the list and places them onto context specific buffer descriptor queues until all queues are full. This method of serving descriptors reduces critical receive microcode overhead since the critical path code does not need to lock a global queue and copy a descriptor to a private area.
NIC Event Queues.
Event notification is sent to the host by writing NIC Event Descriptors (NEvtDsc,
The NEvtDsc is fixed at a size of 32 bytes which includes eight bytes of data, a two byte TCB Identifier (TcbId), a two byte Event Code (EvtCd) and a four byte Event Status (EvtSta). EvtSta is positioned at the end of the structure to be written last because it functions as an event valid indication for the host. The definitions of the various field contents are beyond the scope of this document.
Configuration constants are used to define the queues. These are NIC Event Queue Size (NEQSz) and NIC Event Queue Base Address (NEQBs) which are defined in section Slow Bus Controller. The CPU includes a pair of sequence registers, NIC Event Queue Write Sequence (NEQWrtSq) and NIC Event Queue Release Sequence (NEQRIsSq), for each NicEvtQ. These also function as read and write pointers. Sahara increments NEQWrtSq for each write to the event queue. The host sends a release count of 32 to Sahara each time 32 queue entries have been vacated. Sahara adds this value to NEQRlsSq to keep track of empty queue locations. Additional information can be found in sections CPU Operands and DMA Director.
Global Ram (GlbRam/GRm)
GlbRam, a 128 KB dual port static ram, provides working memory for the CPU. The CPU has exclusive access to a single port, ensuring zero wait access. The second port is used exclusively during DMA operations for the movement of data, commands and status. GlbRam may be written with data units as little as a byte and as large as 8 bytes. All data is protected with byte parity ensuring detection of all single bit errors.
Multiple data structures have been pre-defined, allowing structure specific DMA operations to be implemented. Also, the predefined structures allow the CPU to automatically compile GlbRam addresses using contents of both configuration registers and dynamic registers The resulting effect is reduced CPU overhead. The following list shows the structures and the memory used by them. Any additional structures may reduce the quantity or size of the TCB cache buffers.
Header Buffers
Configuration constants define the buffers. They are Header Buffer Base Address (HdrBBs) and Header Buffer Size (HdrBSz). The maximum buffer size allowed is 256 B.
Special CPU operands have been provided which automatically compile addresses for the header buffer area. Refer to section CPU Operand for additional information.
A special DMA is implemented which allows efficient initiation of a copy from DRAM to HdrBuf. Refer to section DMA Director for additional information.
TCB Valid Bit Map
A bit-map (
Proxy Buffers
Transmit packet processing uses assembly of transmit descriptors which are deposited into transmit command queues. Up to 32-bytes (8-entries) can be written to the transmit queue while maintaining exclusive access. In order to avoid spin-lock during queue access, a proxy DMA has been provided which copies contents of proxy buffers from GlbRam to the transmit command queues. Sixty four proxy buffers of 32-bytes each are defined by microcode and identified by their starting address. Refer to sections DMA Director and Transmit Operation for additional information.
System Buffer Descriptor Stage
Raw frames and slow path packets are delivered to the system stack via System Buffers (SysBuf/Sbf). These buffers are defined by System Buffer Descriptors (SbfDsc, See prior section System Buffer Descriptor Lists) comprising an 8-byte physical address and an 8-byte virtual address. The system assembles 128 SbfDscs into a 2 KB list then deposits a pointer to this list on to RcvRng 0. The system then notifies microcode by a writing to Sahara's tickle register. Microcode copies the lists as needed into a staging area of GlbRam from which individual descriptors will be distributed to each CPU context's system buffer descriptor queue. This stage is 2 KB to accommodate a single list.
DMA Descriptor Buffers
Event mode DMAs also access DmaBufs but do so for a different purpose. Event descriptors are written to the host memory resident NIC Event Queues. They are fetched from the DmaBuf by the DMA Director, but are passed on as data instead of being used as extended command descriptors. Event mode utilizes two consecutive DmaBufs since event descriptors are 32-bytes long. It is recommended that DmaCxs 6 and 7 be reserved exclusively for this purpose.
TCB Cache Buffers
A 12-bit identifier (TcbId) allows up to 4095 connections to be actively supported by Sahara. Connection 0 is reserved for raw packet transmit and system buffer passing. These connections are defined by a collection of variables and constants which are arranged in a structure known as a TCP Control Block (TCB). The size of this structure and the number of connections supported preclude immediate access to all of them simultaneously by the CPU due to practical limitations on local memory capacity. A TCB caching scheme provides a solution with reasonable tradeoffs between local memory size and the quantity of connections supported.
Most of GlbRam is allocated to TCB Cache Buffers (CchBuf/Cbf) leaving primary storage of TCBs in inexpensive host DRAM. In addition to storing the TCB structure, these CchBufs provide storage for the TCB Receive Queue (TRQ) and an optional Prototype Header (Phd). The Phd storage option is intended as a fallback in the event that problems are encountered with the transmit sequencer proxy method of header modification.
CchBufs are represented by cache buffer identifiers (CbfId). Each CpuCtx has a specialized register (CxCbfId) which is dedicated to containing the currently selected CbfId. This value is utilized by the DMA Director, TCB Manager and by the CPU for special memory accesses. CbfId represents a GlbRam resident buffer which has been defined by the configuration constants cache buffer base address (CchBBs) and cache buffer size (CchBSz). The CPU and the DMA Director access structures and variables in the CchBufs using a combination of hard constants, configuration constants and variable register contents. TRQ access by the CPU is facilitated by the contents of the specialized Connection Control register—CxCCtl which holds the read and write sequences for the TRQ. These are combined with TRQ Index (TRQIx), CbfId and CchBSz and CchBBs to arrive at a GlbRam address from which to read or to which to write. The values in CxCCtl are initially loaded from the cached TCB's CPU Variables field (CpuVars) whenever a context first gains ownership of a connection. The value in the CchBuf is updated immediately prior to relinquishing control of the connection. The constant TRQ Size (TRQSz) indicates when the values in CxCCtl should wrap around to zero.
Four command sub-structures are implemented in the CchBuf. Two of these provide storage for receive commands—RCmdA and RCmdB and the remaining two provide storage for transmit commands—XCmdA and XCmdB. The commands are used in a ping-pong fashion, allowing the DMA to store the next command or the next SGL entry in one command area while the CPU is actively using the other. Having a fixed size of 32-bytes, the command areas are defined by the configuration constant—Command Index (CmdIx). The DMA Director includes a ring mode which copies command descriptors from the XmtRngs and RcvRngs to the command sub-structures—XCmdA, XCmdB, RCmdA and RCmdB. The commands are retrieved from sequential entries of the host resident rings. A pointer to these entries is stored in the cached TCB in the sub-structure—RngCtrl and is automatically incremented by the DMA Director upon completion of a command fetch. Delivery to the CchBuf resident command sub-structure is ping-ponged, controlled by the CpuVars bits—XCmdOdd and RCmdOdd which are essentially images of XRngPtr[0] and RRngPtr[0] held in CxCCtl. These bits are used to form composite registers for use in DMA Director commands.
DRAM Controller (RcvDrm/Drm|XmtDrm/Drm)
XDC supports checksum and crc generation while writing to XmtDrm. XDC also provides a crc appending capability at completion of write data copying. RDC supports checksum and crc generation while reading from RcvDrm and also supports reading additional crc bytes, for testing purposes, which are not copied to the destination. Both controllers provide support for priming checksum and crc functions.
The RDC and XDC modules operate using clocks with frequencies which are independent of the remainder of the system. This allows for optimal speeds based on the characteristics of the chosen dram. Operating at the optimal rate of 500 Mb/sec/pin, the external data bus comprises 64 bits of data and 8 bits of error correcting code. The instantaneous data rate is 4 GB/s for each of the dram subsystems while the average data rate is around 3.5 GB/s due to the overhead associated with each read or write burst. A basic dram block size of 128 bytes is defined which yields a maximum burst size of 16 cycles of 16 B per cycle. Double data rate (DDR) dram is utilized of the type RLDRAM.
The dram controllers implement source and destination sequencers. The source sequencers accept commands to read dram data which is stored into DMA queues preceded by a destination header and followed by a status trailer. The destination sequencers accept address, data and status from DMA queues and save the data to the dram after which a DMA response is assembled and made available to the appropriate module. The dram read/write controller monitors these source and destination sequencers for read and write requests. Arbitration is performed for read requesters during a read service window and for write requesters during a write service window. Each requestor is serviced a single time during the service window excepting PrsDstSqr and XmtSrcSqr requests which are each allowed two DMA requests during the service window. This dual request allowance helps to insure that data late and data early events do not occur. Requests are limited to the maximum burst size of 128 B and must not exceed a size which would cause a burst transfer to span multiple dram blocks. E.g., a starting dram address of 5 would limit XfrCnt to 128-5 or 123.
The Dram Controller includes the following seven functional sub-modules:
PrsDstSqr—Parser to Drm Destination Sequencer monitors the RcvDmaQues and moves data to RcvDrm. No response is assembled.
D2hSrcSqr—Drm to Host Source Sequencer accepts commands from the DmdDspSqr, moves data from RcvDrm to D2hDmaQ preceded by a destination header and followed by a status trailer.
D2gSrcSqr—Drm to GlbRam Source Sequencer accepts commands from the DmdDspSqr, moves data from RcvDrm to D2gDmaQ preceded by a destination header and followed by a status trailer.
H2dDstSqr—Host to Drm Destination Sequencer monitors the H2dDmaQue and moves data to XmtDrm. It then assembles and presents a response to the DmdRspSqr.
G2dDstSqr—G1bRam to Drm Destination Sequencer monitors the G2dDmaQue and moves data to XmtDrm. It then assembles and presents a response to the DmdRspSqr.
D2dCpySqr—Drm to Drm Copy Sequencer accepts commands from the DmdDspSqr, moves data from Drm to Drm then assemble and presents a response to the DmdRspSqr.
XmtSrcSqr—Drm to Formatter Source Sequencer accepts commands from the XmtFmtSqr, moves data from XmtDrm to XmtDmaQ preceded by a destination header and followed by a status trailer.
DMA Director (DmaDir/Dmd)
The DMA Director services DMA request on behalf of the CPU and the Queue Manager. There are eleven distinct DMA channels, which the CPU can utilize and two channels which the Queue Manager can use. The CPU employs a combination of Global Ram resident descriptor blocks and Global Ram resident command queues to initiate DMAs. A command queue entry is always used by the CPU to initiate a DMA operation and, depending on the desired operation, a DMA descriptor block may also used. All DMA channels support the descriptor block mode of operation excepting the Pxy channel. The CPU may initiate TCB, SGL and Hdr DMAs using an abbreviated method which does not utilize descriptor blocks. The abbreviated methods are not available for all channels. Also, for select channels, the CPU may specify the accumulation of checksums and crcs during descriptor block mode DMAs. The following table lists channels and the modes of operation which are supported by each.
DMA commands utilize configuration information in order to proceed with execution. Global constants such as TCB length, SGL pointer offsets and so on are set up by the CPU at time zero. The configurable constants are:
Figure X depicts the blocks involved in a DMA. The processing steps of a descriptor, mode DMA are:
Proxy Command for Pxh and Pxl
Proxy commands provide firmware an abbreviated method to specify an operation to copy data from GRm resident Proxy Buffers (PxyBufs) on to transmit command queues. DMA variables are retreived and/or calculated using the proxy command fields in conjunction with configuration constants. The command is assembled and deposited into the proxy command queue (PxhCmdQ or PxlCmdQ) by the CPU. Format for the 32-bit, descriptor-mode, command-queue entry is:
The format of the 32-bit Proxy Buffer descriptor is:
TCB Mode DMA Command for G2h and H2g
TCB Mode (TcbMd) commands provide firmware an abbreviated method to specify an operation to copy TCBs between host based TCB Buffers and GRm resident Cache Buffers (Cbfs). DMA variables are retreived and/or calculated using the DMA command fields in conjunction with configuration constants. The dma size is determined by the configuration constants:
The format of the 32-bit, TCB-mode, command-queue entry is:
Variable TbfId and configuration constants CchBSz and CchBBs are used to calculate GlbRamras well as HstMem addresses for the copy operation. They are formulated as follows:
GRmAd=CchBBs+(CbfId*CchBSz);
HstAd=TcbBBs+(TbfId*2K);
Command Ring Mode DMA Command for H2g
Command Ring Mode (RngMd) commands provide firmware an abbreviated method to specify an operation to copy transmit and receive command descriptors between host based command rings (XmtRng and RcvRng) and GRm resident Cache Buffers (Cbfs). DMA variables are retreived and/or calculated using the DMA command fields in conjunction with configuration constants. Transmit ring command pointer (XRngPtr) and receive ring command pointer (RRngPtr) are retrieved from the CchBuf incremented and written back. Firmware must decrement transmit ring count (XRngCnt) and receive ring count (RRngCnt). The dma size is fixed at 32. The format of the 32-bit, Ring-mode, command-queue entry is:
Variables TbfId and CbfId and configuration constants XRngBs, RRngBs, XRngSz, RRngSz, XmtCmdIx, CchBSz and CchBBs are used to calculate GlbRam as well as HstMem addresses for the copy operation. They are formulated as follows for transmit command ring transfers:
GRmAd=CchBBs+(CbfId*CchBSz)+XmtCmdIx+32;
HstAd=XRngBs+((TbfId<<XRngSz)+XRngPtr)*32);
They are formulated as follows for receive command ring transfers:
GRmAd=CchBBs+(CbfId*CchBSz)+RcvCmdIx+32;
HstAd=XRngBs+((TbfId<<RRngSz)+RRngPtr)*32);
SGL Mode DMA Command for H2g
SGL Mode (SglMd) commands provide firmware an abbreviated method to specify an operation to copy SGL entries from the host resident SGL to the GRm resident TCB. DMA variables are retreived and/or calculated using the DMA command fields in conjunction with configuration constants and TCB resident variables. Either a transmit or receive SGL may be specified via the CmdMd[0]. This command is assembled and deposited into the H2g Dispatch Queue by the CPU. The format of the 32-bit, descriptor-mode, command-queue entry is:
CmdMd and CbfId are used along with configuration constants CchBSz, CchBBs, SglPIx and MemDscIx to calculate addresses. The 64-bit SGL pointer, which resides in a Cache Buffer, is fetched using an address formulated as:
GRmAd=CchBBs+(CbfId*CchBSz)+SglPIx+(IxSel*MemDscSz);
The retreived SGL pointer is then used to fetch a 12-byte memory descriptor from host memory which is in turn written to the Cache Buffer at an address formulated as:
GRmAd=CchBBs+(CbfId*CchBSz)+MemDscIx+(IxSel*16);
The SGL pointer is then incremented by the configuration constant SGLIncSz then written back to the CchBuf.
Event Mode DMA Command for G2h
Event Mode (EvtMd) commands provide firmware an abbreviated method to specify an operation to copy an event descriptor between GRm and HstMem. DMA variables are retreived and/or calculated using the DMA command fields in conjunction with configuration constants. The DMA size is fixed at 16 bytes. Data are copied from an event descriptor buffer determined by {DmaCx,CpuCx}.
The format of the 32-bit, Event-mode, command-queue entry is:
Command variables NEQId and NEQSq and configuration constants DmaBBs, NEQSZ and NEQBs are used to calculate the HstMem and GlbRam addresses for the copy operation. They are formulated as follows:
GRmAd=DmaBBs+{CpuCx,DmaCx,5′b00000};
HstAd=NEQBs+{(NEQId*NicQSz)+NEQSq,5′b00000};
Prototype Header Mode DMA Command for H2d Prototype Header Mode (PhdMd) commands provide firmware an abbreviated method to specify an operation to copy prototype headers to DRAM Buffers from host resident TCB Buffers (Tbf). DMA variables are retreived and/or calculated using the DMA command fields in conjunction with configuration constants. This command is assembled and deposited into a dispatch queue by the CPU. CmdMd[0] selects the dma size as follows:
The format of the 32-bit, protoheader-mode, command-queue entry is:
Configuration constants PHdrIx and CmpBBs are used to calculate the host address for the copy operation. The addresses are formulated as follows:
HstAd=(TbfId*1K)+CmpBBs;
DrmAd=XbfId*256;
This command does not include a DmaCx or DmaTg field. Any resulting response will have the DmaCx and DmaTg fields set to 5′b11011.
Prototype Header Mode DMA Command for G2d
Prototype. Header Mode (PhdMd) commands provide firmware an abbreviated method to specify an operation to copy prototype headers to DRAM Buffers from GRm resident TCB Buffers (Thf). DMA variables are retreived and/or calculated using the DMA command fields in conjunction with configuration constants. This command is assembled and deposited into a dispatch queue by the CPU. CmdMd[1] selects the dma size as follows:
The format of the 32-bit, protoheader-mode, command-queue entry is:
Configuration constants CchBSz and CchBBs are used to calculate GlbRam and dram addresses for the copy operation. They are formulated as follows:
GRmAd=(CbfId*CchBSz)+CchBBs+PHdrIx;
Drd=XbfId*256;
Header Buffer Mode DMA Command for D2g
Header Buffer Mode (HbfMd) commands provide firmware an abbreviated method to specify an operation to copy headers from DRAM Buffers to GRm resident Header Buffers (Hbf). DMA variables are retreived and/or calculated using the DMA command fields in conjunction with configuration constants. This command is assembled and deposited into a dispatch queue by the CPU.
The format of the 32-bit, header-mode, command-queue entry is:
Configuration constants HdrBSz and HdrBBs are used to calculate GlbRam and dram addresses for the copy operation. They are formulated as follows:
GRmAd=HdrBBs+({CpuCx,HbfId}*HdrBSz);
DrmAd=RbfId*32;
Descriptor Mode DMA Command for D2h, D2g, D2d, H2d, H2g, G2d an G2h
Descriptor Mode (DscMd) commands allow firmware greater flexibility in defining copy operations through the inclusion of additional variables assembled within a GlbRam-resident DMA Descriptor Block (DmaDsc). This command is assembled and deposited into a DMA dispatch queue by the CPU. The format of the 32-bit, descriptor-mode, command-queue entry is:
DMA Descriptor
The DMA Descriptor (DmaDsc) is an extension utilized, by DscMd DMA commands, to allow added specification of DMA variables. This method has the benefit of retaining single-word commands for all dispatch queues, thereby retaining the non-locked queue access method. The DmaDsc variables are assembled in, GlbRam resident, DmaDsc Buffers (DmaDsc). Each CpuCx has, preallocated, GlbRam memory which accommodates eight DmaDscs per CpuCx for a total of 256 DmaDscs. The DmaDscs are accessed using a GlbRam starting address formulated as:
GRmAd=DmaBBs+({CpuCx,DmaCx}*16)
DmaDscs are fetched by the DmdDspSqr and used, in conjunction with DmaCmds, to assemble a descriptor for presentation to the various DMA source sequencers. DmaDscs are also updated, upon DMA termination, with ending status comprising variables which reflect the values of address and length counters.
DMA Event for D2h, D2g, D2d, H2d, H2g, G2d and G2h
DMA Event (DmaEvt) is a 32-bit entry which is deposited into one of the 32 Context Dma Event Queues (C??EvtQ), upon termination of a DMA operation, if RspEn is set or if an error condition was encountered. The event is used to resume processing by a CPU Context and to relay DMA status. The format of the 32-bit event descriptor is as follows:
A response is forced regardless of the state of the RspEn bit anytime an error is detected. Next, the DmaErr bit of the xxx register will be set. Dma option is not updated for commands which encounter an error, but the dma descriptor is updated to reflect the residual transfer count at time of error.
Ethernet MAC and PHY
Receive Sequencer (RcvSqr/RSq)
The Receive Sequencer is depicted in
The receive process steps are:
CPU pushes RbfId onto RcvBufQ.
Transmit Sequencer (XmtSqr/XSq)
The Transmit Sequencer is depicted in
The transmit process steps are:
The CPU includes a Writeable Control Store (WCS) capable of storing up to 8K instructions. The instructions are loaded by the host through a mechanism described in the section Host Cpu Control Port. Every virtural CPU (thread) executes instructions fetched from the WCS. The WCS includes parity protection which will cause the CPU to halt to avoid data corruption.
A CPU Control Port allows the host to control the CPU. The host can halt the CPUs and force execution at location zero. Also, the host can write the WCS, check for parity errors and monitor the global cpu halt bit. A 2048 word Register File provides simultaneous 2-port-read and 1-port-write access. The File is partitioned into 41 areas comprising storage reserved for each of the 32 CPU contexts, each of the 8 CPUs and a global space. The Register File is parity protected and thus requires initialization prior to usage. Reset disables parity detection enabling the CPU to initialize the File before enabling detection. Parity errors cause the CPU to halt. Hardware support for CPU contexts facilitates usage of context specific resources with no microcode overhead. Register File and Global Ram addresses are automatically formed based on the current context. Changing CPU contexts requires no saving nor restoration of registers and pointers. Thirty-two contexts are implemented which allows CPU processing to continue while contexts sleep awaiting DMA completion.
CPU snooping is implemented to aid with microcode debug. CPU PC and data are exported via a multilane serial interface using an XGXS module. Refer to section XXXX and the SACI specification for additional information. See section Snoop Port for additional information.
Local memory called Global Ram (GlbRam or GRm) is provided for immediate access by the CPUs. The memory is dual ported however, one port is inaccessible to the CPU and is reserved for use by the DMA Director (DMD). Global Ram allows each CPU cycle to perform a read or a write but not both. Due to the delayed nature of writes, it is possible to have single instructions which perform both a read and a write, but instructions which attempt to read Global Ram immediately following an instruction which performs a write will result in a CPU trap. This memory is parity protected and requires initialization. Reset disables parity detection. Parity errors cause the CPU to halt.
Queues are integrated into the CPU utilizing a dedicated memory called Queue Ram (QueRAM or QRm). Similar to the Global Ram, the memory is dual-ported but the CPU accesses only a single port. DMD accesses the second port to write ingress and read egress queues containing data, commands and status. Care must be taken not to write any queue during an instruction immediately following an instruction reading any queue or a CPU trap will be performed. This memory is parity protected and must be initialized. See section Queues for additional information.
A Lock Manager provides several locks for which requests are queued and honored in the order in which they were received. Locks can be requested or cleared through the use of flags or test conditions. Some flags are dedicated to locking specific functions. In order to utilize the Math Coprocessor a CPU must be granted a lock. The lock is monitored by the Coprocessor and must be set before commands will be accepted. This allows single instructions to request the lock, write the coprocessor registers and perform a conditional jump. Another lock is dedicated to ownership of the Slow Bus Controller. The remaining locks are available for user definition. See section Lock Manager for additional information.
An Event Manager—has been included which monitors events requiring attention and generates vectors to expedite CPU servicing. The Event Manager is tightly integrated with the CPU and can monitor context state to mask context specific events. See section Event Manager for additional information.
Instruction Format
The CPU is vertically-microcoded. That is to say that the instruction is divided into ten fields with the control fields containing encoded values which select operations to be performed. Instructions are fetched from a writable-control-store and comprise the following fields.
Program Sequence Control (SqrCd).
The SqrCd field in combination with DbgCtl determines the program sequence as defined in the following table.
Condition Code Enable (CCEnb).
The CCEnb field allows the SvdCC register to be updated with the result of an ALU operation.
Alu Operations (AluOp).
The ALU performs 32-bit operations. All operations utilize two source operands except for the priority encode operation which uses only one and the add carry operation which uses the “C” bit of the SvdCC register.
Alu Operands (SrcA, SrcB, Dst).
All ALU operations require operands. Source operand codes provide the ALU with data on which to operate and destination operand codes direct the placement of the ALU product. Operand codes, names and descriptions are listed in the following tables.
10′b000000XXXX (0:15)—CPU Unique Registers.
Each CPU uses its own unique instance of the following registers.
10′b0000010XXX (16:23)—Context Unique Registers.
Each of the thirty two CPU contexts has a unique instance of the following registers. Each CPU has a CpCxId register which selects a set of these registers to be read or modified when using the operand codes defined below. Multiple CPUs may select the same context register set but only a single CPU should modify a register to avoid conflicts.
10′b00000110XX (24:28)—Aligned Registers.
These operands provide an alternate method of accessing a subset of those registers that have been defined previously which contain a field less than 32-bits in length. The operands allow reading and writing these previously defined registers using the alignment which they would have during use in composite registers.
10′b00000111XX (28:31)—Composite Registers.
These operands provide an alternate method of accessing a subset of those registers that have been defined previously which contain a field less than 32-bits in length. The operands allow reading and writing various composites of these previously defined registers. This has the effect of reading and merging or extracting and writing several registers with a single instruction.
10′b00001000XX, 10′b000010010X (32:37)—Instruction Literals.
These source operands facilitate various modes of access of the instruction literal fields.
10′b000010011X (38:39)—Slow Bus Registers.
These operands provide access to the Slow Bus Controller. See Slow Bus Subsystem for a more detailed description.
10′b0000101XXX (40:47)—Context and Event Control Registers.
These operands facilitate control of CPU events and contexts. See the section Event Manager for a more detailed description.
10′b000011XXXX (48:63)—TCB Manager Registers.
These operands facilitate control of TCB and Cache Buffer state. See the section TCB Manager for a more detailed description.
10′b0001000XXX (64:71) CPU Debug Registers.
These operands facilitate control of CPUs. See the section Debug Control for a more detailed description.
10′b00010010XX (72:75)—Math Coprocessor Registers.
These operands facilitate control of the Math Coprocessor. See the section Math Coprocessor for a more detailed description.
10′b00010011XX (76:79)—Memory Control Registers.
These operands allow the CPU to control memory parity detection. Each bit of the register represents a memory subsystem as follows: 0-WCS, 1-GlbRam, 2-QueRam, 3-RFile, 4-1TSram.
10′b000101XXXX (80:95)—Sequence Servers.
There are eight incrementers which will provide a sequence to the CPU when read. They allow multiple CPUs to take sequences without the need for locking, modifying and unlocking. The servers are paired such that one functions as a request sequence and the other functions as a service sequence. Refer to test conditions for more info. Alternatively, the sequence servers can be treated independently. A server can be read at its primary or secondary address. Reading the server with its secondary address causes the server to post increment. Writing a server causes the server to initialize to zero.
10′b00011XXXXX (96:127)—Reserved.
10′b0010XXXXXX, 10′b00110XXXXX (128:223)—Constants.
Constants provide an alternative to using the instruction literal field.
10′b001110XXXX, 10′b00111100XX, 10′b001111010X (224:244)—Reserved.
10′b001111011X (245:246)—NIC Event Queue Servers.
Bunch of verbiage here. NEQId=CpQId[2:0].
10′b0011111XXX, 10′b010XXXXXXX (248:383)—Queue Registers.
These operands facilitate control of the queues. See the section Queues for a more detailed description
10′b011XXXXXX (384:511)—Global Ram Operands.
These operands provide multiple methods to address Global Ram. The last three operands support automatic post-incrementing. The increment is controlled by the operand select bit Opd[3] and takes place after the address has been compiled. All operands utilize bits [2:0] to control byte swapping and size as shown below.
Hardware detects conditions where reading or writing of data crosses a word boundary and cause the program counter to load with the trap vector. The following shows how address and Opd[2:0] affect the Global Ram data presented to the ALU.
The following shows how address and Opd[2:0] affect the ALU data presented to the Global Ram.
10′ b1XXXXXXXXXX (512:1023)—Register File Operands.
These operands provide multiple methods to address the Register File. The Register File has three partitions comprising CPU space, Context space and Shared space.
Global Ram Address Literal (AdLit).
This field supplies a literal which is used in forming an address for accessing Global Ram.
Test Operations (TstCd).
Instruction bits [40:32] serve as the FlgCd and TstCd fields. They serve as the TstCd for Lpt, Rtt, Rtx and Jpt instructions. TstCd[8] forces an inversion of the selected test result. Test codes are defined in the following table.
Flag Operations (FlgCd).
Instruction bits[40:32] serve as the FlgCd and TstCd fields. They serve as the FlgCd for Cnt, Jmp, Jsr and Jsx instructions. Flag codes are defined in the following table.
Jump Address (JmpAd).
Instruction bits [31:16] serve as the JmpAd and LitHi fields. They serve as the JmpAd for Jmp, Jpt, Jsr and Jsx instructions.
Literal High (LitHi).
Instruction bits [31:16] serve as the JmpAd and LitHi fields. They serve as the LitHi for Lpt, Cnt, Rtt and Rtx instructions. LitHi can be used with LitLo to for a 32-bit literal.
Literal Low (LitLo).
Instruction bits [15:00] serve as the LitLo field.
CPU Control Port
The host requires a means to halt the CPU, download microcode and force execution at location zero. That means is provided by the CPU Control Port. The port also allows the host to monitor CPU status.
SACI Port.
Debug (Dbg)
Describe function of debug registers here.
Halt, run, stop, debug, trigger, debug operand and debug data.
Debug Operand allows the selection of the AluSrcB and AluDst operands for CPU debug cycles.
Debug Source Data is written to by the debug master. Can be specified in AluSrcB field of DbgOpd to force writing of data to destination specified in AluDst. This mechanism can be used to push on to the stack or PC or CPU specific registers which are otherwise not accessible to the debug master.
Debug Destination Data is written to by the debug slave. Is specified in AluDst field of DbgOpd to force saving of data specified in the AluSrcB field. This allows reading from the stack or PC or CPU specific register which are otherwise not accessible to the debug master.
lock manager (LckMgr/LMg)
A Register Transfer Language (RTL) description of a lock manager is shown below, and a block diagram of the lock manager is shown in
Slow Bus Controller
The slow bus controller comprises a Slow Data Register (SlwDat), a Slow Address Register (SlwAdr) and a Slow Decode Register (SlwDec). SlwDat sources data for a 32-bit data bus which connects to registers within each of Sahara's functional modules. The SlwDec decodes the SlwAdr[SglSel] bits asserts CfgLd signals which are subsequently synchronized by their target modules then used to enable loading of the target register selected by the SlwDec[RegSel] bits.
Multiple cycles are required for setup of SlwDat to the destination registers because the SlwDat bus is heavily loaded. Because of this, only a single CPU can access slow registers at a given time. This access is moderated by a queued lock. Queued lock xx must be acquired before a cpu can successfully write to slow registers. Failure to obtain the lock will cause the write to be ignored. The eight level pipeline architecture of the CPU ensures that a single CPU will allow eight clock cycles of setup and hold for slow data. A minimum of three destination clock cycles are needed to ensure that data is captured. This means that if the destination to CPU clock frequency ratio is less than 0.375 (SqrCtkFrq/CpuClkFrq) then a delay must be inserted between steps 2 and 3, and steps 4 and 5. The CPU ucode should perform the steps shown in
Insert module select and register select and register definition tables here.
Dispatch Queue Base (CmdQBs)
GlbRam address at which the first Dispatch Queue resides. Used by the CPU while writing to a dispatch queue and by DMA Dispatcher while reading for a dispatch queue.
Response Queue Base (EvtQBs)
GlbRam address at which the first Response Queue resides. Used by the CPU while reading from a response queue and by DMA Response Sequencer while writing to a response queue.
DMA Descriptor Base (DmaBBs)
GlbRam address at which the first DMA Descriptor resides. Used by the CPU, DMA Dispatcher and DMA Response Sequencer.
Header Buffer Base (HdrBBs)
GlbRam address at which the first Header Buffer resides. Used by the CPU and DMA Dispatcher.
Header Buffer Size (HdrBSz)
Size of the Header Buffers. Used by the CPU and DMA Dispatcher to determine the GlbRam location of successive Header Buffers. An entry of 0 indicates a size of 256.
TCB Map Base (TMapBs)
GlbRam address at which the TCB Bit Map resides. Used by the CPU.
Cache Buffer Base (CchBBs)
GlbRam address at which the first Cache Buffer resides. Used by the CPU and DMA Dispatcher.
Cache Buffer Size (CchBSz)
Size of the Cache Buffers. Used by the CPU and DMA Dispatcher to determine the GlbRam location of successive Cache Buffers and by the DMA Dispatcher to determine the amount of data to copy from dram TCB Buffers to Cache Buffers. An entry of 0 indicates a size of 2 KB.
Host Receive SGL Pointer Index (SglPlx)
Location of SGL Pointers relative to the start of a Cache Buffer. Used by the DMA Dispatcher to fetch the RcvSglPtr or XmtSglPtr during SGL mode operation.
Memory Descriptor Index (MemDscIx)
Location of the Next Receive Memory Descriptor relative to the start of a Cache Buffer. Used by the DMA Dispatcher to specify a data destination address during SGL mode operation.
Receive Queue Index (TRQIx)
Start of the Receive Queue relative to the start of a Cache Buffer. Used by the DMA Dispatcher for TCB mode operations to specify the amount of data to be copied. Used by the CPU to formulate Receive Queue read and write addresses.
Receive Queue Size (TRQSZ)
Size of the Receive Queue. Used by the DMA Dispatcher for TCB mode operations to specify the amount of data to be copied. Used by the CPU to determine roll-over boundaries for Receive Queue Write Sequence and Receive Queue Read Sequence. An entry of 0 indicates a size of 1 KB.
TCB Buffer Base (TcbBBs)
Host address at which the first TCB resides. Used by the DMA Dispatcher to formulate host addresses during TCB mode operations.
Dram Queue Base (DrmQBs)
Dram address at which the first dram queue resides. Used by the Queue Manager to formulate dram addresses during queue body read and write operations.
Math Coprocessor (MCP)
Sahara contains hardware to execute divide/multiply operations. There is only 1 set of hardware so only one processor may be using it at any one time.
The divider is used by requesting QLck[0] while writing to the dividend register. If the lock is not granted then the write will be inhibited, permitting a single instruction loop until the lock is granted. The operation is then initiated by writing to the divisor register which will cause test condition MthBsy to assert. When complete, MthBsy status will be reset and the result can be read from the quotient and dividend register.
Divide is executed sequentially 2 bits at a time. The number of clocks taken is actually deterministic, assuming the sizes of the operands are known. For divide, the number of cycles taken can be calculated as follows:
MS_Bit_divend=bit position of most significant 1 bit in dividend
MS_Bit_divisor=bit position of most significant 1 bit in divisor
Number of clocks to complete=MS_Bit_divend/2−MS_Bit_divisor/2+2
So if, for instance, we know that the dividend is less than 64K (fits in bits 15-0) and the divisor may be as small as 2 (represented by bit 1), then the maximum number of clocks to complete is 15/2−½+2=7−0+2=9 cycles The multiply is performed by requesting QLck[0] while writing to the multiplicand register. If the lock is not granted then the write will be inhibited, permitting a single instruction loop until the lock is granted. The operation is then initiated by writing to the multiplier register which will cause test condition MthBsy to assert. When complete, MthBsy status will be reset and the result can be read from the product register.
Multiply time is only dependent on the size of the multiplier. The number of cycles taken for multiply may be calculated by
MS_Bit_multiplier=bit position of most significant 1 bit in multiplier
Number of clocks to complete=MS_Bit_multiplier/2+1
So to multiply by a 16 bit number would take (15/2+1) or 8 clocks.
Queues
The Queues are utilized by the CPU for communication with modules or between processes. There is a dedicated Queue Ram which holds the queue data. The queues can be directly accessed by the CPU without need for issuing commands. That is to say that the CPU can read or write a queue with data. The instruction which performs the read or write must perform a test to determine if the read or write was successful.
There are three types of queues. Ingress queues hold information which is passing from a functional module to the CPU.
Event Manager (EvtMgr/EMg)
Events and CPU Contexts are inextricably bound. DMA response and run events invoke specific CPU Contexts while all other events demand the allocation of a free CPU Context for servicing to proceed.
Event control registers provide the CPU a method to enable or disable events and to service events by providing vector generation with automated context allocation. Events serviced, listed in order of priority, are:
EvtMgr prioritizes events and presents a context to the CPU along with a vector to be used for code branching. Event vectoring is accomplished when the CPU reads the Event Vector (EvtVec) register which contains an event vector in bits [3:0] and a CPU Context in bits [28:24]. The instruction adds the retrieved vector to a vector-table base-address constant, loading the resulting value into the program counter, thereby accomplishing a branch-relative function. The instruction actually utilizes the CpCxId destination operand along with a flag modifier which specifies the pc as a secondary destination. The actual instruction would appear something like:
EvtVec is an EvtMgr register, VTblAdr is the instruction address where the vector table begins, CpCxId is current CPU's context ID register and FlgLdPc specifies that the alu results also be written to the program counter. The final effect is for the CPU Context to be switched and the event to be decoded within a single cycle. A single exception exists for the RunEvt for which the EvtVec register does not provide the needed context for resumes. Reading the EvtVec register causes the event type associated with the current event vector to be disabled by clearing it's corresponding bit in the Event Enable register (EvtEnb) or in the case of a RspEvt, by setting the context to the busy state. The effect is to inhibit duplicate event service, until explicitly enabled at a later time. The event type may be re-enabled by writing it's bit position in the EvtEnb register or CtxSlp register. The vector table takes the following form.
EvtMgr provides an event mask for each of the CPUs. This allows ucode to configure each CPU with a unique mask for the purpose of distributing the load for servicing events. Also, a single CPU can be defined to service utility functions.
RSqEvt and CmdEvt priorities can be shared. Each time the EvtMgr issues RSqEvt or CmdEvt in response to an EvtVec-read the issued event is assigned the least of the two priorities while the other event is assigned the greater of the two priorites thus ensuring fairness. This is accomplished by setting PriTgl each time RSqEvt is issued.
TCB Manager (TcbMgr/TMg)
Due to Sahara's multi-CPU and multi-context architecture, TCB and Cache Buffer access is coordinated through the use of TCB Locks and Cache Buffer Locks. TcbMgr provides the services needed to facilitate these locks. TcbMgr is commanded via a register which has sixteen aliases whereby each alias represents a unique command. Command parameters are provided by the alu output during CPU instructions which specify one of the command aliases as the destination operand. Command responses are immediately saved to the CPU's accumulator.
TCB Locks
The objective of TCB locking is to allow logical CPUs, while executing a Context specific thread, to request ownership of a TCB for the purpose of reading the TCB, modifying the TCB or copying the TCB to or from the host. It is also the objective of TCB locking, to enqueue requests such that they are granted in the order received with respect to like priority requests and such that high priority requests are granted prior to normal priority requests.
Up to 4096 TCBs are supported and a maximum of 32 TCBs, one per CPU Context, can be locked at a given time. TCB ownership is granted to a CPU Context and each CPU Context can own no more than a single TCB. TCB ownership is requested when a CPU writes a CpxId and TcbId to the TlkNmlReq or TlkRcvReq operand. Lock ownership will be granted immediately provided it is not already owned by another CPU Context. If the requested TCB Lock is not available and the ChnInh option is not selected then the TCB Lock request will be chained. Chained TCB Lock requests will be granted at future times as TCB Lock release operations pass TCB ownership from CPU Context which initiated the next lock request.
Priority sub-chaining is affected by the TlkRcvReq and TlkRcvPop operands. This facilitates a low latency receive-event copy from the RcvSqr event queue to the TCB receive-list and the ensuing release of the CPU-context for re-use. This feature increases the availability of CPU Contexts for performing work by allowing them to be placed back into the free context pool. The de-queuing of high priority requests from the request chain does not affect the current lock ownership. It allows the current CPU to change to the CPU Context which generated the high priority request, then copy the receive-event descriptor from a context specific register to a CPU specific register, switch back to the previous CPU-context, release the dequeued CPU Context for re-use and finally push the retrieved receive-event descriptor on to the TCB receive-list.
Each CPU Context has a dedicated TCB-Lock register set of which the purpose is to describe a lock request. The TCB Lock register set is defined as follows.
TlkReqVld—Request Valid indicates that an active lock request exists and serves as a valid indication for all other registers. This register is set by the TlkNmlReq and TlkRcvReq commands and it is cleared by the TlIkLckRls and TlkRcvPop commands.
TlkTcbNum—TCB Number specifies one of 4096 TCBs to be locked. This register is modified by only the TlkNmlReq and TlkRcvReq commands. The contents of TlkTcbNum are continuously compared with the command parameter CmdTcb and the resultant status is used to determine if the specified TCB is locked or unlocked.
TlkGntFlg—Grant Flag indicates that the associated CPU Context has been granted Tcb ownership. Set by the commands TlkNmlReq and TlkRcvReq or when the CPU Context has a queued request which is scheduled to be serviced next and a different CPU Context relinquishes ownership. Grant Flag is cleared during the TlkLckFIs command.
TlkChnFlg—Chain Flag indicates that a different CPU Context has requested the same TCB-Lock and that it's request has been scheduled to be serviced next. TlkChnFlg is set during TlkNmIReq and TlkRcvReq commands and is cleared during TlkRcvPop and TlkLckFls commands.
TlkPriEnd—Priority End indicates that the request is the last request in the priority sub-chain. It is set or cleared during TlkRcvPop, TlIkLckRIs, TMgReqNml and TMgReqHgh commands.
TlkNxtCpx—Next CpX specifies the CPU Context of the next requester and is valid if TlkChnFlg is asserted.
The following four commands allow the CPU to control TCB Locking.
Request TCB Lock—Normal Priority (TlkNmlReq)
Requests, at a normal priority level, a lock for the specified TCB on behalf of the specified CPU Context. If the context already has a request for a TCB Lock other than the one specified, then TmgErr status is returned because a context may never own more than a single lock. If the context already has a request for the specified TCB Lock but does not yet own the TCB, then TmgErr status is returned because the specified context should be resuming with the lock granted. If the specified context already has ownership of the specified TCB, then TmgDup status is returned indicating successful resumption of a thread. If the specified TCB is owned by another context and ChnInh is reset, then the request will be linked to the end of the request chain and TmgSlp status will be returned indicating that the thread should retire until the lock is granted. If the specified TCB is owned by another context and ChnInh is set, then the request will not be linked and TmgSlp status will be returned. The request chaining inhibit is provided for unanticipated situations.
Release TCB Lock (TIkLckRIs)
Requests that the specified CPU Context relinquish the specified TCB Lock. If the CPU Context does not own the TCB, then TmgErr status is returned. If a chained request is found, it is immediately granted the TCB Lock and the ID of the new owner is returned in the response along with TmgRsm status. The current logical CPU may put the CPU Context ID of the new owner on to a resume list or it may immediately resume execution of the thread by assuming the CPU Context. If no chained request is found, then TmgGnt status is returned.
Request TCB Lock—Receive Priority (TlkRcvReq)
Requests, at a high priority level, a lock for the specified TCB on behalf of the specified CPU Context. If the context already has a request for a TCB Lock other than the one specified, then TmgErr status is returned because a context may never own more than a single lock. If the context already has a request for the specified TCB Lock but does not yet own the TCB, then TmgErr status is returned because the specified context should be resuming with the lock granted. If the specified context already has ownership of the specified TCB, then TmgDup status is returned indicating successful resumption of a thread. If the specified TCB is owned by another context and ChnInh is reset, then the request will be linked to the end of the priority request sub-chain and TmgSlp status will be returned. If a priority request sub-chain has not been previously established, then one will be established behind the head of the lock request chain by inserting the high priority request into the request chain between the current owner and the next normal priority requester. The priority sub-chaining affords a means to quickly pass RcvSqr events through to the receive queue residing within a TCB. If the specified TCB is owned by another context and ChnInh is set, then the request will not be linked and TmgSlp status will be returned. The request chaining inhibit is provided for unanticipated situations.
Pop Receive Request (TlkRcvPop)
Causes the removal of the next TCB Lock request in the receive sub-chain of the specified CPU Context. If the CPU Context does not own the specified TCB, then TmgErr status is returned. If there is no chained receive request detected then TmgEnd status is returned.
TCB Cache Control
Cache Buffers (Cbfs) are areas within Global Ram which have been reserved for the caching of TCBs. TcbMgr provides control and status registers for 128 Cache Buffers and can be configured to support fewer Cache Buffers. Each of the Cache Buffers has an associated Cache Buffer register set comprising control and status registers which are dedicated to describing the Cache Buffer state and any registered TCB. TcbMgr uses these registers to identify and to lock Cache Buffers for TCB access by the CPU. The Cache Buffer register set is defined as follows.
Cbfstate—Each of the Cache Buffers is assigned one of four states; DISABLED, VACANT, IDLE or BUSY as indicated by the two CbfState flip-flops. The DISABLED state indicates that the Cache Buffer is not available for caching of TCBs. The VACANT state indicates that the Cache Buffer is available for caching of TCBs but that no TCB is currently registered as resident. The IDLE state indicates that a TCB has been registered as resident and that the Cache Buffer is unlocked (not BUSY). The BUSY state indicates that a TCB has been registered as resident and that the Cache Buffer has been locked for exclusive use by a CPU Context.
CbfTcbNum—TCB Number identifies a resident TCB. The identifier is valid for IDLE and BUSY states only. This value is compared against the command parameter CmdTcb and then the result is used to confirm TCB residency for a specified Cache Buffer or to search for a Cache Buffer wherein a desired TCB resides.
CbfDtyFlg—A Dirty Flag is provided for each Cache Buffer to indicate that the resident TCB has been modified and needs to be written back to external memory. This bit is valid during the IDLE and BUSY states only. The Dirty Flag also serves to inhibit invalidation of a modified TCB. Attempts to register a new TCB or invalidate a current registration will be blocked if the Dirty Flag of the specified Cache Buffer is asserted. This protective feature can be circumvented by asserting the Dirty Inhibit (DtyInh) parameter when initiating the command.
CbfSlpFlg—Normally, TCB Locks ensure collision avoidance when requesting a Cache Buffer, but a situation may sometimes occur during which a collision takes place. Sleep Flag indicates that a thread has encountered this situation and has suspended execution while awaiting Cache Buffer collision resolution. The situation occurs whenever a requested TCB is not found to be resident and an IDLE Cache Buffer containing a modified TCB is the only Cache Buffer type available in which to cache the desired TCB. The modified TCB must be written back, to the external TCB Buffer, before the desired TCB can be registered. During this time, if another CPU requests the dirty TCB then CbfSlpFlg will be asserted, the context of the requesting CPU will be saved to CbfSlpCtx and then the thread will be suspended. When the Cache Buffer owner registers the new TCB a response is given which indicates that the suspended thread must be resumed.
CbfSlpCpx—Sleeping CPU Context indicates the thread which was suspended as a result of a Cache Buffer collision.
CbfCycTag—Each Cache Buffer has an associated Cycle Tag register which indicates the order in which it is to be removed from the VACANT Pool or the IDLE Pool for the purpose of caching a currently non-resident TCB. Two counters, VACANT Cache Buffer Count (VacCbfCnt) and IDLE Cache Buffer Count (IdlCbfCnt), indicate the number of Cache Buffers which are in the VACANT or IDLE states. When a Cache Buffer transitions to the VACANT state or to the IDLE state, the value in VacCbfCnt or IdlCbfCnt is copied to the CbfCycTag register and then the counter is incremented to indicate that a Cache Buffer has been added to the pool. When a Cache Buffer is removed from the VACANT Pool or the IDLE Pool, any Cache Buffer in the same pool will have it's CbfCycTag decremented providing that it's CbfCycTag contains a value greater than that of the exiting Cache Buffer. Also, the respective counter value, VacCbfCnt or IdlCbfCnt, is decremented to indicate that one less Cache Buffer is in the pool. CbfCycTag is valid for the VACANT and IDLE states and is not valid for the DISABLED and BUSY states. The CbfCycTag value of each Cache Buffer is continuously tested for a value of zero which indicates that it is the least recently used Cache Buffer in it's pool. In this way, TcbMgr can select a single Cache Buffer from the VACANT Pool or from the IDLE Pool in the event that a targeted TCB is found to be nonresident. The following five commands allow the CPU to initiate Cache Buffer search, lock and registration operations.
Get Cache Buffer. (CchBufGet)
This command requests assignment of a Cache Buffer for the specified TCB. TMg first performs a registry search and if an IDLE Cache Buffer is found wherein the specified TCB resides, then the Cache Buffer is made BUSY. TmgGnt status is returned along with the CbfId.
If a BUSY Cache Buffer is found, wherein the specified TCB resides, and SlpInh is set, then TmgSlp status is returned indicating that the Cache Buffer cannot be reserved for use by the requestor.
If a BUSY Cache Buffer is found, wherein the specified TCB resides, and SlpInh is not set, then the specified CPU Context ID is saved to the CbfSlpCpx and the CbfSlpFlg is set. TmgSlp status is returned indicating that the CPU Context should suspend operation until the Cache Buffer has been released.
If the specified TCB is not found to be residing in any of the Cache Buffers but an LRE Cache Buffer is detected, then the Cache Buffer state will be set to BUSY, the TCB will be registered to the Cache Buffer and TmgFch status plus CbfId will be returned.
If the specified TCB is not found to be residing in any of the Cache Buffers and no LRE Cache Buffer is detected but a LRU Cache Buffer is detected that does not have it's DtyFlg asserted, then the Cache Buffer state will be set to BUSY, the TCB will be registered to the Cache Buffer and TmgFch status will be returned along with the CbfId. The program thread should then schedule a DMA operation to copy the TCB from the external TCB Buffer to the Cache Buffer.
If the specified TCB is not found to be residing in any of the Cache Buffers, no LRE Cache Buffer is detected and a LRU Cache Buffer is detected that has it's DtyFlg asserted, then the Cache Buffer state will be set to BUSY and TmgFsh status will be returned along with the CbfId and it's resident TcbId. The program thread should then schedule a DMA operation to copy the TCB from the internal Cache Buffer to the external TCB Buffer, then upon completion of the DMA, register the desired TCB by issuing a CchTcbReg command, then schedule a DMA to copy the desired TCB for it's external TCB Buffer to the Cache Buffer.
Modify Dirty. (CchDtyMod)
Selects the specified Cache Buffer. If the state is BUSY and the specified TCB is registered, then the CbfDtyFlg is written with the value in DtyDat and a status of TmgGnt is returned. This command is intended primarily as a means to set the Dirty Flag. Clearing of the Dirty Flag is normally done as a result of invalidating the resident TCB.
Evict and Register. (CchTcbReg)
Requests that the TCB which is currently resident in the Cache Buffer be evicted and that the TCB which is locked by the specified CPU Context (TlkTcbNum[CmdCpx]) be registered. The Cache Buffer must be BUSY, CmdTcb must match the current registrant and Dirty must be reset or overridden with DtyInh in order for this command to succeed. SlpFlg without SlpInh causes SlpCpx to be returned along with TmgRsm status otherwise TmgGnt status is returned. This command is intended to register a TCB after completing a flush DMA operation.
Evict and Release. (CchTcbEvc)
Requests that the TCB which is currently resident in the Cache Buffer be evicted and that the Cache Buffer then be released to the Vacant Pool. The Cache Buffer must be BUSY, CmdTcb must match the current registrant and Dirty Flag must be reset or overridden with DtyInh in order for this command to succeed. SlpFlg without SlpInh causes SlpCpx to be returned along with TmgRsm status otherwise TmgGnt status is returned.
Release. (CchBufRIs)
Selects the specified Cache Buffer then verifies Cache Buffer BUSY and TCB registration before releasing the Cache Buffer. SlpFlg found causes SlpCpx to be returned along with TmgRsm status otherwise a TmgGnt status is returned. DtySet will cause the Dirty Flag to be asserted in the event of a successful Cbf release.
The following commands are intended for maintenance and debug usage only.
TCB Manager Reset. (TmgReset)
Resets all Cache Buffer registers and all TCB Lock registers.
TCB Query. (TmgTcbQry)
Performs registry search for the specified TCB and reports Cache Buffer ID. Also performs TCB Lock search for the specified TCB and reports Cpu Context ID. Additional TCB information can then be obtained by using the returned IDs along with the CchBufQry and TlkCpxQry commands. This command is intended for debug usage.
Cache Buffer Query. (CchBufQry)
Returns information for the specified Cache Buffer. This command is intended for debug usage.
Least Recently Emptied Query. (CchLreQry)
Report on least recently vacated Cache Buffer. Also returns vacant buffer count. Intended for degug usage.
Least Recently Used Query. (CchLruQry)
Report on least recently used Cache Buffer. Also returns idle buffer count. Intended for degug usage.
Cache Buffer Enable. (CchBufEnb)
Enables the specified Cache Buffer. Buffer must be in the DISABLE state for this command to succeed. Any other state will result in a TmgErr status. Intended for initial setup.
TCB Lock Query—Cpu Context (TlkCpxQry)
Returns the lock registers for the specified CPU Context. TcbDet indicates that CmdTcbId is valid and identical to TlkTcbNum. This command is intended for diagnostic and debug use.
Host Bus Interface Adaptor (HstBIA/BIA)
Host Event Queue (HstEvtQ)
Write Descriptor Entry:
CONVENTIONAL PARTS
PCI EXPRESS, EIGHT LANE
RLDRAM, 76 BIT, 500 Mb/S/Pin
XGXS/XAUI
SERDES
RGMII
MAC
SRAM
PLLs
1) Write request is presented to controller.
2) Read request is presented to controller.
3) Write 0 data, write 0 address and write enable are presented to RAM while OddCyc is false.
4) Read 0 address is presented to RAM while OddCyc is true.
5) Write 1 data, write 1 address and write enable are presented to RAM and read 0 data is available at RAM outputs.
6) Read 1 address is presented to RAM while read 0 data is available at read registers.
7) Write 2 data, write 2 address and write enable are presented to RAM, read 1 data is available at RAM outputs and read 0 data is available at Brm write data registers from where it will be written to Brm.
This application claims the benefit under 35 U.S.C. 119 of Provisional Patent Application Ser. No. 60/797,125, filed May 2, 2006, by inventors Daryl D. Starr, Clive M. Philbrick and Colin R. Sharp, entitled Network Interface Device with 10 Gb/sFull-Duplex Transfer Rate, which is incorporated by reference herein.
| Number | Date | Country | |
|---|---|---|---|
| 60797125 | May 2006 | US |
