Patent Application
20080159454
The invention relates to network on chips (NoC), and, more particularly, to transmitting/receiving data asynchronously.
System-on-Chip (SoC) design is a growing trend. In SoC design, on-chip-communication (OCC) is important because it limits throughput rate of the entire chip. Conventional OCC architectures utilize shared bus architecture, referred to as on-chip-bus (OCB), such as the IBM CoreConnect Bus Architecture and the ARM AMBA bus system.
Multi-clocking is a recent SoC design trend. Multi-clocking is challenged in transmitting data reliably between multiple clock domains. Synchronous multi-clock transmission methods typically suffer from data loss.
Accordingly, globally asynchronous locally synchronous (GALS) techniques are provided. GALS can achieve data transfer between different clock phases and different clock rates.
An on-chip data transmission device is provided. The on-chip data transmission device comprises a transmitter and a receiver. The transmitter transmits a control signal and a plurality of packets when logic levels of the control signal change. The logic level of the control signal changes every clock cycle. An input signal clock A determines the clock cycle. The receiver receives the transmitted control signal and a clock B signal A generates a first mixed clock having a phase substantially the same as the clock B, is subsequently generated and receives one transmitted packet per clock B cycle.
In another aspect of the invention, a network on chip device is provided. The network on chip device comprises a first silicon intellectual property (SIP) module, a transmitter (TX), a second SIP module, and a receiver RX. The first SIP sets a TX enable signal, generates a clock A signal and the plurality of packets. The transmitter transmits a control signal and the plurality of packets when logic levels of the control signal change, wherein the logic level of the control signal changes every clock cycle, and the clock cycle is determined by the clock A. The second SIP module sets an RX enable signal, and generates a clock B signal. The receiver receives the transmitted control signal and the clock B, and receives one of a plurality of transmitted packets per clock B cycle when the RX enable signal is set.
In another aspect of the invention, a network on chip device comprising a plurality of SIP modules is provided. Each SIP comprises a core module, a transmitter and a receiver. The core module sets a TX enable signal, and generates a clock A signal and a plurality of first packets. The transmitter generates a first control signal when the TX enable signal is set, and transmits the plurality of first packets when a logic level of the first control signal changes. The core module further sets an RX enable signal. The receiver receives a second control signal and receives one of the second packets per clock A cycle.
The invention will become more fully understood from the detailed description, given herein below, and the accompanying drawings. The drawings and description are provided for purposes of illustration only, and, thus, are not intended to be limiting of the invention.
In one embodiment of the invention, the receiver 204 comprises a first D flip-flop (DFF) 206, an exclusive-or (XOR) gate 208, a mutual exclusion unit (ME) 210, and a second DFF 212. The first DFF 206 has a control input, a data input bus, a clock input, a control output bus and a data output bus. The first DFF 206 accepts the transmitted control signal as the control input, the first mixed clock as clock input, the transmitted packets as the data input bus, and generates a first DFF control output and a first DFF data output bus. The exclusive-or (XOR) gate 208 generates an XOR output according to the transmitted control signal and the first DFF control output. The mutual exclusion unit (ME) 210 accepts the XOR output and a clock C to generate the first mixed clock and a second mixed clock. The mutual exclusion unit 210, is implemented as shown in
In some embodiments, the receiver 204 further comprises a phase adjusting unit 214 to assure that the phase of the clock C lags the XOR output by 180 degrees.
Since the receiver 204 receives one packet per clock B cycle, when clock B is slower than clock A, receiver 204 may miss some packets. Thus, in some embodiments of the invention, the transmitter 202 further comprises a flow control unit 202 to control a packet transmission rate. The flow control unit 216 receives signal R indicating the ratio of the clock rate A over clock rate B. When clock B is slower than clock A, the packet transmission rate is kept substantially the same as one packet per clock B cycle. The flow control unit 216 further activates a read signal to indicate that the transmitter 202 is transmitting packets.
In another aspect of the invention, a network on chip device is provided.
In some embodiments, the transmitter 506 further receives an R signal indicating the ratio of clock rate A over the clock rate B. When the rate of clock B is slower than the rate of clock A, a packet transmission rate is kept substantially at one packet per clock B cycle. The transmitter 504 further activates a read signal to indicate to the first SIP module 502 that the transmitter 504 is transmitting the plurality of packets.
Similarly, the receiver 506 may further generate a write signal to indicate to the second SIP module 508 that the receiver 506 is receiving the plurality of transmitted packets.
In another aspect of the invention, a network on chip device comprising a plurality of SIP modules is provided.
While the invention has been described by way of example and in terms of preferred embodiment, it is to be understood that the invention is not limited thereto. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
