1. Field of the Invention
The present invention relates to a network signal processing apparatus, and more particularly, to a network signal processing apparatus comprising a first sampling rate converter, a second sampling rate converter, and a timing controller, wherein the first and the second sampling rate converters respectively perform signal frequency conversion on signals in a synchronous domain and in an asynchronous domain according to a first timing adjustment signal and a second timing adjustment signal generated by the timing controller in order that the signals in a synchronous domain and in an asynchronous domain have the different operation frequency, respectively.
2. Description of the Prior Art
Generally speaking, a transmitter (TX) and a receiver (RX) in a communication system deliver signals in a synchronous way while the TX transmits signals and the RX receives signals. In practice, it is required to design a clock generator in the RX for generating a clock signal and to analyze the received signal to perform phase adjustment on the clock signal until the clock signal of the RX locks the clock signal of the TX, so as to complete the clock synchronization.
However, it is required to constantly adjust the phase of the clock signal of the RX for the purpose of tracking the clock signal of the TX. Therefore, repeatedly performing operations for converging some values calculated by the system may be required due to the unstable phase, and that could cause the overall system efficiency to be greatly reduced.
It is therefore an objective of the present invention to provide a network signal processing apparatus comprising a first sampling rate converter and a second sampling rate converter that make signals converted from an asynchronous domain to a synchronous domain, or from a synchronous domain to an asynchronous domain so that utilize at least one signal in a synchronous domain to control at least one device in an asynchronous domain.
According to an embodiment of the present invention, a network signal processing apparatus is disclosed. The network signal processing apparatus comprises: a first signal processing module, a first sampling rate converter, a second signal processing module, a second sampling rate converter, and a timing controller. The first signal processing module is operated in an asynchronous domain and is utilized for processing a network signal to output a first processed signal. The first sampling rate converter is coupled to the first signal processing module, and is utilized for performing signal frequency conversion on the first processed signal according to a first timing adjustment signal and outputting a first converted signal. The second signal processing module, which is operated in a synchronous domain and is further coupled to the first sampling rate converter, is utilized for processing the first converted signal to output a second processed signal. The second sampling rate converter is coupled between the first signal processing module and the second signal processing module, and is utilized for performing signal frequency conversion on the second processed signal according to a second timing adjustment signal and outputting a second converted signal to the first signal processing module. And the timing controller is coupled to the first and the second sampling rate converters, and is utilized for generating the first timing adjustment signal to the first sampling rate converter and generating the second timing adjustment signal to the second sampling rate converter so as to adjust the timing of both the first and the second converted signals.
According to an embodiment of the present invention, a network signal processing apparatus is also disclosed. The network signal processing apparatus comprises: a first signal processing module, a sampling rate converter, a second signal processing module, and a timing controller. The first signal processing module is operated in an asynchronous domain, and is utilized for processing a network signal to output a first processed signal. The sampling rate converter is coupled to the first signal processing module, and is utilized for performing signal frequency conversion on the first processed signal according to a timing adjustment signal and outputting a converted signal. A second signal processing module, which is operated in a synchronous domain and is further coupled to the sampling rate converter, is utilized for processing the converted signal to output a second processed signal. A timing controller is coupled to the second signal processing module, and is utilized for generating the timing adjustment signal according to the second processed signal so as to adjust the timing of the converted signal.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Please refer to
First, please refer to the first signal processing module 110 shown in
As shown in
Please refer to the second signal processing module 120 shown in
As shown in
Please refer to
Please refer to
It should be noted that problems such as frequency offset or phase offset are not considered in the above-mentioned embodiments. If the frequency offset or phase offset problems need to be considered, the timing controller can provide a compensation quantity via the timing adjustment signal to compensate the sampling rate converter dynamically. It is assumed that the first sampling rate converter 130 and the second sampling rate converter 140 are both interpolators and the frequency conversion is performed by means of interpolation. According to a compensation amount Offset provided through the first timing adjustment signal Sadj1, the timing controller 150 controls the time step of the interpolation that the first sampling rate converter 130 performs on the first processed signal Sp1, in order to compensate the first sampling rate converter 130 dynamically. Similarly, According to a compensation amount Offset provided through the second timing adjustment signal Sadj2, the timing controller 150 controls the time step of the interpolation that the first sampling rate converter 130 performs on the second processed signal Sp2, in order to compensate the second sampling rate converter 140 dynamically, so as to make the timing of second converted signal Sc2 substantially equal to the timing of first processed signal Sp1. For example, the time step of the interpolation performed by the first sampling rate converter 130 is fixed at 1.25 units when the frequency offset or the phase offset problems are not considered; nevertheless, when the frequency offset or the phase offset problems are considered, the time step of the interpolation performed by the first sampling rate converter 130 will become equal to (1.25+Offset) units. Moreover, the methods of dynamic compensation can be further divided into the methods utilizing a phase-locked loop (PLL) and the methods utilizing a voltage controlled oscillator (VCO). When the method utilizing a PLL is applied, only some of the time steps are equal to (1.25+Offset) units, while the others are still fixed at 1.25 units, wherein the compensation amount Offset is a constant value. When the method utilizing a VCO is applied, all the time steps are equal to (1.25+Offset) units, and the timing controller 150 is continuously updating the value of the compensation amount Offset. Please note that since the detailed operations and apparatus about how to use the PLL and the VCO to compensate the time step are well known to those skilled in the art, further description is omitted here for the sake of brevity.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
Number | Date | Country | Kind |
---|---|---|---|
97104194 A | Feb 2008 | TW | national |
Number | Name | Date | Kind |
---|---|---|---|
5539739 | Dike et al. | Jul 1996 | A |
6075830 | Piirainen | Jun 2000 | A |
6308229 | Masteller | Oct 2001 | B1 |
6487672 | Byrne et al. | Nov 2002 | B1 |
6560716 | Gasparik | May 2003 | B1 |
6762630 | Fibranz et al. | Jul 2004 | B2 |
6848060 | Cook et al. | Jan 2005 | B2 |
6961863 | Davies et al. | Nov 2005 | B2 |
7394608 | Eleftheriou et al. | Jul 2008 | B2 |
7395450 | Karaki | Jul 2008 | B2 |
7433142 | Bui et al. | Oct 2008 | B2 |
7522367 | Eleftheriou et al. | Apr 2009 | B2 |
7596176 | Eleftheriou et al. | Sep 2009 | B2 |
7739628 | Manohar et al. | Jun 2010 | B2 |
7900078 | Manohar et al. | Mar 2011 | B1 |
20070047121 | Eleftheriou et al. | Mar 2007 | A1 |
20070098061 | Eleftheriou | May 2007 | A1 |
Number | Date | Country | |
---|---|---|---|
20090199035 A1 | Aug 2009 | US |