Claims
- 1. A neural digital processor (10), comprising:
- a. an input (13) for receiving digital data and generating an output signal,
- b. a neural unit (12) coupled to the input for calculating neural potentials, from the output signal, according to a function of the output signal and synaptic coefficients, said synaptic coefficients are weight connections either between neurons or between neurons and the input,
- c. memory (16) for storing said synaptic coefficients,
- d. means (14) for subjecting at least one of the neural potentials, designated POT, to at least one approximative non-linear activation function ANLF which is formed by n segments in order to produce at least one neural state, said means (14) comprising another neural digital processor which comprises:
- I. means (20) for calculating n combinations, M.sub.j =H.sub.j .multidot.POT+Th.sub.j, where
- n is an integer;
- j is an integer such that 1.ltoreq.j.ltoreq.n;
- H.sub.j are predetermined synaptic coefficients; and
- Th.sub.j are thresholds,
- II. means (22) for calculating states S.sub.j =F(M.sub.j), using another non-linear function CNLF which is formed by
- A. a segment F(x), where x is a running independent variable, which segment is not constant when x is situated in an interval (-x.sub.min, x.sub.max), and
- B. two segments F(x)=F.sub.max and F(x)=-F.sub.min when x.gtoreq.x.sub.max and x.ltoreq.-x.sub.min, respectively,
- III. means (24) for linearly combining the states with further synaptic coefficients D.sub.j in order to produce said at least one neural state STAT.
- 2. A processor as claimed in claim 1, wherein the means (22) for calculating the states comprises:
- means (36.sub.1, 36.sub.2, 64) for detecting whether the combinations M.sub.j are situated within the interval (-x.sub.min,x.sub.max) or outside this interval,
- means (37) for calculating the states in this interval, and
- means (37) for assigning, to the states, values F.sub.max and -F.sub.min, respectively, when M.sub.j .gtoreq.x.sub.max and M.sub.j.ltoreq.-x.sub.min, respectively.
- 3. A processor as claimed in claim 2, wherein the means (37) comprises a table which stores predetermined values F(M.sub.j) at addresses M.sub.j.
- 4. A processor as claimed in claim 2, wherein
- said other non-linear function CNLF is a ramp, and
- the means (37) comprises transfer means (38,65) that apply the potential values M.sub.j to the states S.sub.j.
- 5. A processor as claimed in claim 1, wherein the other neural digital processor also comprises means (75) for calculating a derivative F' of the non-linear activation function ANLF.
- 6. A processor as claimed in claim 5, wherein the means (75) comprises at least one table which stores predetermined values of the states S'.sub.j =F'(M.sub.j) when the combinations M.sub.j are situated within the interval (-x.sub.min, x.sub.max) and a value zero outside said interval.
- 7. A processor as claimed in claim 5, wherein
- said other non-linear function CNLF is a ramp,
- the means (75) comprises a block (70) that copies, for each state S'.sub.j =F'(M.sub.j), value of the corresponding synaptic coefficient H.sub.j.
- 8. A processor as claimed in claim 5, wherein
- said other non-linear function CNLF is a ramp,
- the means (26) stores values H.sub.j and D.sub.j, for the calculation of the non-linear function ANLF, and values H.sub.j and D.sub.j .multidot.H.sub.j for the derivative of the non-linear function ANLF, and
- the means (75) comprises a block (70) whose inputs receive data of unit value.
- 9. A processor as claimed in claim 1, wherein the means (22) is used for successively calculating applications according to the non-linear function ANLF and according to ANLF's derivative.
- 10. A processor as claimed in claim 1, wherein the neural unit (12) and the other neural processor (14) have common neurons.
- 11. A data processing system comprising a neural network comprising:
- a. a unit for creating a neural potential from input data received by the unit, wherein the neural potential represents a sum of products, each respective one of the products resulting from a respective multiplication of a respective one of the input data by a respective synaptic coefficient;
- b. non-linear function means for applying a non-linear function to the neural potential to create neuron output data, the non-linear function means comprising:
- I. a plurality of further units, each respective one of the further units being for
- A. supplying a respective further product resulting from multiplying the neural potential by a respective factor; and
- B. applying a respective further non-linear function to the further product to create a respective outcome; and
- II. combining means for linearly combining the respective outcomes to provide a value of the first non-linear function associated with said neural potential
- said neural potential being an intermediate signal within a single neuron function whose external signal output is said neuron output data.
- 12. The system of claim 11, wherein each of said respective further non-linear functions comprises a respective ramp between two saturation values.
- 13. The system of claim 11 integrated in a single IC device.
- 14. A non-linear function device for use in creating at least one neuron output in a neural network processor, the device comprising:
- a. means for receiving a neural potential signal which results from the sum of the products of a plurality of respective synaptic coefficients to a plurality of respective neuron input signals, which neural potential signal is an intermediate signal within a same neuron function as the at least one neuron output;
- b. a plurality of means for sequentially applying a plurality of respective basic transfer functions to the neural potential signal for creating respective intermediate outcomes; and
- c. combining means for linearly combining the respective outcomes to produce at least one non-linear output signal, said at least one non-linear output signal being an output of the at least one neuron.
- 15. A neural digital processor comprising:
- a. input means for receiving digital data;
- b. first means for storing a first plurality of synaptic coefficients;
- c. a first neural unit for applying the first plurality of synaptic coefficients to an output signal of the input means, according to a stored neuron configuration to create at least one neural potential signal;
- d. means for applying at least one respective first non-linear function to each of the at least one neural potential signal to create at least one respective neuron output, said means for applying at least one first non-linear function comprising another neural digital processor coupled to the first neural unit, said other neural digital processor comprising:
- I. second means for storing a second plurality of synaptic coefficients;
- II. a second neural unit for applying the second plurality of synaptic coefficients to the output signal of the first neural unit; and
- III. means for applying at least one second non-linear function to an output signal of the second neural unit, said at least one second non-linear function being simpler than the non-linear function,
- wherein each of the at least one neural potential signal is an intermediate signal within a respective single neuron function whose ultimate output is created by the means for applying at least one first respective non-linear function.
- 16. The processor of claim 15 further comprising feedback means coupling the means for applying at least one first non-linear function and the first neural unit, so that the at least one first non-linear function is iteratively appliable to realize neuron outputs of successive layers of the stored neuron configuration.
- 17. The processor of claim 15, wherein each of the at least one second non-linear function is a respective ramp.
Priority Claims (1)
Number |
Date |
Country |
Kind |
91 15373 |
Dec 1991 |
FRX |
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Parent Case Info
This is a continuation of application Ser. No. 07/980,829, filed on Nov. 24, 1992, now abandoned.
US Referenced Citations (14)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2236608 |
Apr 1991 |
GBX |
Non-Patent Literature Citations (2)
Entry |
C. Alippi et al., "Simple Approximation of Signmoidal Functions: Realistic Design of Digital Neural Networks Capable of Learning", 1991 IEEE International Symposium on Circuits and Systems, Jun. 11-14, 1991, vol. 3, pp. 1505-1508. |
Martinez et al, "Digital Neural Networks", Proceedings of the 1988 IEEE, Inter. Conf. on Systems. Man and Cybernetics, Aug. 8-12, 1988. |
Continuations (1)
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980829 |
Nov 1992 |
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