Patent Application
20220092408
This disclosure generally relates to accelerators for machine learning models and, more particularly, to neural network weight distribution using a tree direct-memory access (DMA) bus.
Neural networks are increasingly being used to implement machine learning (ML) techniques to solve a wide variety of problems including, but not limited to, object identification, feature classification, or content-driven image processing. Some neural networks, which may be referred to as convolutional neural networks, include one or more convolutional layers. In a convolutional neural network (CNN), the convolutional layers typically account for the vast majority of the computations performed and the data movement within the CNN and/or between the CNN and other elements of an ML model, making them a performance bottleneck. Therefore, existing ML accelerators focus on using high compute parallelism along with an optimized data orchestration throughout the memory hierarchy to speed up the processing of convolutional layers. However, existing ML accelerators may not perform well when implemented within edge devices that have strict power consumption constraints and that run inference exercises using previously trained models in real time. For example, existing ML accelerators may not perform well within artificial reality systems for virtual reality (VR), augmented reality (AR), mixed reality (MR), or hybrid reality implemented on standalone head-mounted displays (e.g., on AR/VR headsets), mobile devices or other edge computing devices.
In particular embodiments, a tree direct-memory access (DMA) controller and DMA bus structure may be used to selectively broadcast, multicast, or unicast neural network weights across multiple tensor processor units distributed throughout a machine learning (ML) accelerator. Specifically, the tree DMA controller may serve as a centralized hub through which neural network weights are distributed to tensor processor units throughout the ML accelerator. Individual tensor processor units are grouped into several clusters, or “tensor processor clusters.” Each tensor processor cluster includes its own local memory (e.g., used to store weights) and several tensor processor units individually capable of performing neural network operators. The tree DMA controller may receive one or more addresses from a compiler indicating locations in memory (e.g., SRAM) where weights are stored. The tree DMA controller may also receive distribution instructions from the compiler regarding how the weights are to be distributed across tensor processor clusters for processing input (e.g., input features). The tree DMA controller may access the one or more addresses to retrieve the weights and then distribute the weights across tensor processor clusters via the DMA bus structure, or “tree DMA bus,” according to the distribution instructions provided by the compiler.
Weights may be broadcast to all tensor processor clusters, multicast to a subset of tensor processor clusters, or unicast to a singular tensor processor cluster. For example, the tree DMA controller may access a memory address provided by the compiler to retrieve a set of weights and then broadcast the set of weights via the tree DMA bus to each tensor processor cluster for processing input features. In this instance, each tensor processor cluster may process the input features in synchronized lockstep such that when the tensor processor clusters have completed processing, they may each provide a token to the tree DMA controller indicating that the input features have been processed. In response to receiving the tokens, the tree DMA controller may retrieve additional weights from memory and distribute the additional weights to the tensor processor clusters via the tree DMA bus. By structuring the tree DMA bus according to a tree network topology (e.g., rather than a star or ring topology), the tree DMA controller may distribute neural network weights to each tensor processor cluster directly, thereby minimizing latency and overall power consumption. As such, the machine learning accelerator may be suitable for AR/VR applications or other applications that require feature processing with minimal latency within a finite power budget.
Innovative aspects of the subject matter described in this specification may be embodied in a system, a method, and computer-readable non-transitory storage media for receiving, by a tree direct-memory access (DMA) controller of a machine learning (ML) accelerator, a memory address indicating a location in a memory storing a set of weights associated with a machine-learning model; receiving, by the tree DMA controller, a distribution instruction indicating one or more tensor processor clusters of a plurality of tensor processor clusters of the ML accelerator selected to receive the set of weights for processing, in parallel, different partitioned portions of an input feature; retrieving the set of weights from the location in the memory indicated by the memory address; and sending, via a tree DMA bus, the set of weights in at least one DMA packet addressed to the one or more tensor processor clusters according to the distribution instruction.
In one or more of the disclosed embodiments, each of the plurality of tensor processor clusters includes: a plurality of tensor processor units, each of the plurality of tensor processor units configured to perform a neural network operator on the input feature using the set of weights, each of the plurality of tensor processor units including a local memory; and a cluster-level controller configured to: store the set of weights into the local memory of one or more tensor processor units of the plurality of tensor processor units according to the distribution instruction; generate a token indicating that the input feature was processed; and send the token to the tree DMA controller.
In one or more of the disclosed embodiments, each of the plurality of tensor processor units is communicatively coupled to the tree DMA controller via a plurality of sub-branches of the tree DMA bus.
In one or more of the disclosed embodiments, the at least one DMA packet includes: a destination bitmap indicating the one or more tensor processor clusters selected to receive the set of weights for processing the input feature; and the set of weights for processing the input feature.
In one or more of the disclosed embodiments, the system, method, and computer-readable non-transitory storage media further includes: directing, by a DMA router of the ML accelerator, the at least one DMA packet to the one or more tensor processor clusters according to the distribution instruction.
In one or more of the disclosed embodiments, each of the plurality of tensor processor clusters is communicatively coupled to the tree DMA controller via the tree DMA bus.
In one or more of the disclosed embodiments, the distribution instruction comprises at least one of: a broadcast distribution, wherein the plurality of tensor processor clusters comprises the one or more tensor processor clusters selected to receive the set of weights for processing the input feature; a multicast distribution, wherein a subset of the plurality of tensor processor clusters comprises the one or more tensor processor clusters selected to receive the set of weights for processing the input feature; and a unicast distribution, wherein a singular tensor processor cluster of the plurality of tensor processor clusters comprises the one or more tensor processor clusters selected to receive the set of weights for processing the input feature.
The embodiments disclosed herein are only examples, and the scope of this disclosure is not limited to them. Particular embodiments may include all, some, or none of the components, elements, functions, operations, or steps of the embodiments disclosed above. Embodiments according to the invention are in particular disclosed in the attached claims directed to a method, a storage medium, a system and a computer program product, wherein any element mentioned in one claim category, e.g., method, can be claimed in another claim category, e.g., system, as well. The dependencies or references back in the attached claims are chosen for formal reasons only. However, any subject matter resulting from a deliberate reference back to any previous claims (in particular multiple dependencies) can be claimed as well, so that any combination of claims and the elements thereof are disclosed and can be claimed regardless of the dependencies chosen in the attached claims. The subject-matter which can be claimed comprises not only the combinations of elements as set out in the attached claims but also any other combination of elements in the claims, wherein each element mentioned in the claims can be combined with any other element or combination of other elements in the claims. Furthermore, any of the embodiments and elements thereof described or depicted herein can be claimed in a separate claim and/or in any combination with any embodiment or element described or depicted herein or with any of the elements of the attached claims.
Embodiments of the invention may include or be implemented in conjunction with an artificial reality system. Artificial reality is a form of reality that has been adjusted in some manner before presentation to a user, which may include, e.g., a virtual reality (VR), an augmented reality (AR), a mixed reality (MR), a hybrid reality, or some combination and/or derivatives thereof. Artificial reality content may include completely generated content or generated content combined with captured content (e.g., real-world photographs). The artificial reality content may include video, audio, haptic feedback, or some combination thereof, and any of which may be presented in a single channel or in multiple channels (such as stereo video that produces a three-dimensional effect to the viewer). Additionally, in some embodiments, artificial reality may be associated with applications, products, accessories, services, or some combination thereof, that are, e.g., used to create content in an artificial reality and/or used in (e.g., perform activities in) an artificial reality. The artificial reality system that provides the artificial reality content may be implemented on various platforms, including a head-mounted display (HMD) connected to a host computer system, a standalone HMD, a mobile device or computing system, or any other hardware platform capable of providing artificial reality content to one or more viewers.
Before discussing the present embodiments in detail, it may be beneficial to first provide some background information regarding neural networks and machine learning (ML) models in general. A neural network, or neural net, is a nodal network of interconnected neurons, where each neuron represents a node in the network. Groups of neurons may be arranged in layers, with the outputs of one layer feeding forward to a next layer in a multilayer perception (MLP) arrangement. MLP may be understood to be a feedforward neural network model that maps a set of input data onto a set of output data.
Typically, each neuron (or node) produces a single output that is fed forward to neurons in the layer immediately following it. However, each neuron in a hidden layer may receive multiple inputs, either from the input layer or from the outputs of neurons in a preceding hidden layer, such as the immediately preceding hidden layer or an earlier hidden layer. In general, each node may apply a function to its inputs to produce an output for that node. Nodes in hidden layers, including layers referred to as learning layers, may apply the same function or a different function to their respective input(s) to produce their respective output(s). Some nodes, however, such as the nodes in the input layer 100 may receive only one input and may be passive, meaning that each node may simply relay the value of its single input to its output(s) thus providing a copy of the input to the output(s).
In the example neural network illustrated in
Typically, except for the input layer, a node (neuron) may receive as input the outputs of nodes in its immediately preceding layer. Each node may calculate its output by, e.g., multiplying each of its inputs by each input's corresponding interconnection weight, summing the products of it inputs, adding (or multiplying by) a constant defined by another weight or bias that may be associated with that particular node, and applying a function, such as a non-linear or logarithmic function, to the result. The non-linear function may be referred to as an activation function or transfer function. Multiple activation functions are known in the art, and selection of a specific activation function is not critical to the present discussion. It is noted, however, that operation of the ML model, or behavior of the neural net, is dependent upon weight values, which may be learned so that the neural network provides a desired output for a given input.
During a training, or learning, stage, the neural network may learn, e.g., may be trained to determine, appropriate weight values to achieve a desired output for a given input. Before the neural network is trained, the weights may be individually assigned an initial value, such as a random, and optionally non-zero, value. Various methods of assigning initial weights are known in the art. The weights are then trained, or optimized, so that for a given training vector input, the neural network produces an output close to a desired, e.g., a predetermined, training vector output. The desired output against which the current output is compared may be referred to as a label for the input data. A training vector input and its corresponding training vector output may be termed an input-output training pair, and a training data set may include multiple input-output training pairs, e.g., tens to millions, or more. In this manner, the weights may be incrementally adjusted in thousands of iterative cycles, such as by a technique termed back-propagation. Several back-propagation techniques are known in the art, including several based on gradient descent, such as batch gradient descent, stochastic gradient descent (SGD), which may include mini-batch gradient descent, distributed synchronous and asynchronous SGD, elastic averaging stochastic gradient descent (EASGD), Hogwild, etc. The different back-propagation techniques may differ in how specific aspects of gradient descent are implemented, but in general, irrespective of the back-propagation technique used, in each cycle of back-propagation, a training input (e.g., vector input) is fed forward through the neural network to determine its actual output (e.g., vector output). An error for each output neuron, or output node, is then calculated based on the actual neuron output and a target or desired training output for that neuron. The process then propagates back through the neural network (in a direction from the output layer back to the input layer), updating the weights based on how much effect each weight has on the overall error so that the output of the neural network moves closer to the desired training output. This cycle may then be repeated until the actual output of the neural network is within an acceptable error range of the desired training output. In machine learning, an epoch typically refers to one complete pass, including back-propagation, if applicable, of the full training dataset to be learned through the machine-learning model. In one epoch, the full training dataset may be submitted to the learning algorithm in a single training iteration, in which case a “batch” of training data is used, or the full training dataset may be submitted in the aggregate after multiple training iterations, each using a subset of the training dataset referred to as a “mini-batch”.
Construction of a neural network model, or a machine-learning model in general, may include a learning stage, which may also be referred to as a training stage, and an inference stage, which may also be referred to as an operational, execution, or service stage. In the learning stage, the neural network may be trained for a specific purpose and may be provided with a set of training examples, including training inputs and training outputs provided as input-output training pairs, and optionally including a set of validation examples to test the progress of the training. During this learning process, various weights associated with nodes and node-interconnections (e.g., links) in the neural network may be incrementally adjusted in order to reduce the error between an actual output of the neural network and the desired training output. In this manner, a multi-layer feed-forward neural network, such as that discussed above, may be made capable of approximating any measurable function to any desired degree of accuracy. The result of the learning stage is a machine learning model that has been trained. In the inference stage, an input with unknown outputs may be submitted to the trained machine learning model, e.g., to server or edge device executing the trained ML model, which may apply what has been learned to process the input to produce an output prediction.
For ease of illustration, some aspects of a neural network framework may be disclosed herein within the context of practical example implementations. Due to real-world hardware limitations, neural networks may have practical size limits. For example, some ML models may achieve large sizes of 10 GB, or more, which may require a long time to train and complicate their hardware implementation. Therefore, in particular embodiments, an ML model may be distributed among multiple similar machines, e.g., machines having identical or substantially similar architectures, using various distributive techniques. Furthermore, it is typically desirable that the hardware, e.g., a computing system, used to train an ML model be tailored to the ML model itself and that all training be done on the same computing system. At times, a computing system used to train an ML model may include fast computing devices optimized for computational capacity and remote memory banks, e.g., parameter servers, that may hold interim parameter values, e.g., weight values.
As used herein, the terms “feature” or “features” may refer to input data or output data associated with a convolution operation. In particular embodiments, the output of each layer of a convolutional neural network may be represented by features that no longer resemble the original input in content, size, and/or shape. For example, an input image including 10×10 pixels with RGB channels may be represented by 10×10×3 features. After one round of convolution, the output may be represented by 4×4×2 features that might or might not look like an image. After a second round of convolution in which the 4×4×2 features are processed, the output may be represented by a lxi feature that looks nothing like an image, in this example. Features organized in a 3D manner may be referred to herein as a “tensor” having dimensions of height (x), width (y), and a number of channels (z). Note that image data is a very specific type of input that is commonly processed using machine learning and neural networks, but it is by no means the only type of data that can be processed using these techniques and using the ML accelerators described herein. For example, the input data processed by a convolutional neural network may represent a depth map, parameterized user information, a heat map for weather forecasting, etc.
Computing systems and system configurations may be tailored not only for particular types of machine learning models and training algorithms, but also for the types of data the machine learning model is designed to process. For example, machine learning models may receive different types of inputs or features, such as dense inputs, which are typically long vectors, sparse inputs, or a combination of both. Dense feature vectors may be used to represent dense inputs and sparse feature vectors may be used to represent sparse inputs. A dense feature vector may be represented by a mostly-populated vector, e.g., a vector having mostly non-zero entries/cells. A common example of a dense feature vector is image data. As another example, a dense feature vector may include determinable descriptors common to or determinable for most users or circumstances, depending upon the specific application, which may be gleaned from multiple sources. For example, dense features may include personal information associated with a user, information identifying a source of the input information, or other contextual information, such as a location, a time-of-day, etc. It is noted that some dense features may be obtained by user-provided input, while others may be collected from user-related demographic or geographic information, user-device status information, user network activity, or other observable user-related sources. A dense input may be thought of as a collection of multiple, definitely determinable descriptors, where each descriptor may be given a numeric value. Because dense inputs may comprise many descriptor types, e.g., many signal/value sources, that together may characterize, describe, or represent a user or circumstance, a dense input may be a large, dense vector with one or more cells/dimensions/entries in the dense vector being designated to each descriptor type.
A sparse input may reflect more semantic information related to a particular task objective. The sparse input may be defined by a sparse feature vector that identifies selections within a larger list(s) of options, such as lists that may further be divided/grouped into different categories. This may be the case when the list of identifiers that comprises the sparse input identifies individual selections from a larger list of options, such as those provided by the dense vector. As a result, a sparse vector may be characterized by having mostly zero entries, and a few non-zero entries. Consequently, a sparse vector may be represented as a series of indexes pointing to select cell positions in the larger list having non-zero values, along with each index's corresponding non-zero value for that position, with the understanding that all other positions not identified by index have a default zero value. Sparse inputs may not necessarily be directly descriptive of a user or circumstance but may instead provide auxiliary information indirectly related to the user or circumstance. Typically, because of their many zero-entry cells, sparse vectors may not be well-suited for direct input to a neural network.
As shown in
[x][y][zout]+=activations[x+kx][y+ky][zin]*weights[kx][ky][zin][zout]
In the illustrated example, there is one 3D filter 406 for each channel (zout) in Zout. More specifically, the illustrated multi-channel convolution uses four 3D filters 406 to generate elements for each x/y position in each of four output channels, respectively, while sweeping the appropriate 2D kernels across and down the elements of input feature map 400 in each of the input channels. For example, the value of element 410 of output feature map 416 is determined by applying highlighted 3D filter 406-1 to the highlighted portion 402 of input feature map 400, i.e., 27 activations including 9 activations in respective x/y positions in each of 3 input channels zin. Similarly, the value of element 408 of output feature map 416 is determined by applying 3D filter 406-4 to the highlighted portion 402 of input feature map 400.
Traversing input feature map 400 in the x dimension involves sweeping the highlighted portion 402 across the input feature map such that element 404 moves one position to the right to identify a next set of activations for each successive iteration in the x dimension. For example, the value of element 414 of output feature map 416 is determined by applying 3D filter 406-1 to the highlighted portion 402 of input feature map 400 after the highlighted portion has been moved from the initial position in which it is shown in
Performing the multi-channel convolution illustrated in
In particular embodiments, the generation of scalar addresses identifying the input and output elements for each 2D convolution is performed by the compiler when generating the tensor instructions that represent the multi-channel convolution. In particular embodiments, the generation of scalar addresses for each of the corresponding input tensors (activation addresses), weight tensors (weight addresses), and output tensor (output address) may be performed in hardware, such as within the ML accelerators described herein, in accordance with the following:
As noted above, in a convolutional neural network, the convolutional layers typically account for the vast majority of the computations performed and the data movement within the CNN and/or between the CNN and other elements of an ML model, making them a performance bottleneck. Therefore, modern CNN accelerators focus on using high compute parallelism along with an optimized data orchestration throughout the memory hierarchy to speed up the processing of convolutional layers. Conventionally, individual tensor processor units within a machine learning accelerator may asynchronously perform convolution operations (e.g., multiplication, accumulation, pooling, and the like) on image data or another type of input feature map, or a portion thereof that has been spatially partitioned. However, effectively harnessing the compute power of these accelerators may require the design of a particular mapping scheme that dictates when (i.e., at which processing cycle) and where (i.e., at which compute data path among hundreds to thousands of them) each operation (i.e., each multiply-and-accumulate, or MAC) is performed. The design of such a mapping scheme may, in turn, have an impact on the hardware architecture design, as the hardware would need to be able to deliver data at the right time and in the right format to the right compute data path so that it can be operated on in the right cycle.
The ML accelerators described herein employ a multi-level control architecture designed to optimally exploit parallelism provided by tensor processor units in the ML accelerator. These machine learning accelerators may include one or more tensor processor clusters, each of which may include multiple tensor processor units. Each tensor processor may be a single-instruction-multiple-data (SIMD) machine that includes a compute array capable of performing vector operations to implement data parallelism or model parallelism at the tensor processor or tensor processor cluster level. Each tensor processor cluster may include a shared controller that controls and synchronizes the operations of the tensor processor units within the cluster so that they perform a common series of operations in parallel and in lockstep. As described in more detail herein, the multi-level control architecture may support more flexibility in parallelism for computations of neural network layers than is possible using existing ML acceleration schemes, while lowering hardware costs due to the physical circuit area and/or power consumed by various tensor instructions. The multi-level apparatus may be used to implement any of a variety of neural network solutions to machine learning problems including, but not limited to, object identification, feature classification, or content-driven image processing. The multi-level apparatus may be particularly well suited for implementation within edge devices that have strict power consumption constraints and that run inference exercises using previously trained models in real time, such as in AR/VR headsets.
In particular embodiments, the compiler 600 may analyze a workload to be performed by the neural network and determine respective coarse-grained tensor instructions to be sent to each tensor processor cluster of ML accelerator 614 using a SIMD and/or single-program-multiple-data (SPMD) approach to distribute the workload. The compiler 600 may distribute the workload based on the architecture of the neural network, the number of tensor processor clusters, the number and processing capacity of the tensor processor units in each tensor processor cluster, the input and output feature dimensions, the number and types of convolutions and other operations to be performed at different layers of the neural network, and/or the relationships between the output features produced at each layer and the input features required at the next layer. The workload distribution decisions may maximize the reuse of locally available feature sets and weights once they are loaded into the memories of particular tensor processor units, reduce the amount of data movement required between and within tensor processor clusters, and optimize resource utilization in ML accelerator 614.
In one embodiment, tree DMA controller 718 may comprise a system, device, or apparatus generally operable to distribute neural network weights to tensor processor clusters 724 for processing input features. For example, tree DMA controller 718 may distribute weights 612 (illustrated in
In one embodiment, tensor instructions received by tree DMA controller 718 from the compiler may include one or more memory addresses indicating locations in memory where neural network weights are stored. For example, tree DMA controller 718 may receive tensor instructions 606 from compiler 600 (illustrated in
In one embodiment, tensor instructions received by tree DMA controller 718 from the compiler may include one or more distribution instructions indicating which tensor processor clusters 724 have been assigned to receive a set of weights. In particular, a distribution instruction may indicate to tree DMA controller 718 which tensor processor clusters 724 have been selected by the compiler to process an input feature using the set of weights stored in shared RAM 708. In one embodiment, distribution instructions may indicate a broadcast distribution, multicast distribution, and/or a unicast distribution. A broadcast distribution instruction indicates to tree DMA controller 718 that the compiler has selected each tensor processor cluster 724 in ML accelerator 700 to receive a set of weights for processing an input feature in parallel. For example, a broadcast distribution instruction from the compiler may prompt tree DMA controller 718 to instruct tree DMA 704 to broadcast a set of weights stored in shared RAM 708 to each tensor processor cluster 724-A through D. A multicast distribution instruction indicates that the compiler has selected a subset tensor processor clusters 724 in ML accelerator 700 to receive a set of weights for processing an input feature in parallel. For example, in response to receiving a multicast distribution instruction from the compiler, tree DMA controller 718 may instruct tree DMA 704 to multicast a set of weights stored in shared RAM 708 to tensor processor clusters 724-A through C, thereby excluding tensor processor cluster 724-D from receiving the set of weights. A unicast distribution instruction indicates to tree DMA controller 718 that the compiler has selected a singular tensor processor cluster 724 to receive a set of weights for processing an input feature. For example, tree DMA controller 718 may instruct tree DMA 704 to unicast a set of weights stored in shared RAM 708 to tensor processor cluster 724-D only, thereby excluding tensor processor clusters 724-A through C from receiving the set of weights. By allowing each tensor processor cluster 724, a subset of tensor processor clusters 724, or a singular tensor processor cluster 724 to receive a set of weights, distribution instructions afford an increased granularity in processing workflow.
In one embodiment, the compiler may base distribution instructions, in part, on partitioning schemes associated with input features at compile time. For instance, input features may be spatially-partitioned or batch-partitioned to facilitate an optimized workflow for processing the input features. In some embodiments, this optimized workflow may require tensor processor clusters 724 of ML accelerator 700 to process different partitioned portions of input features in parallel with respect to one another. For example, each tensor processor cluster 724A through D may process respective batch-partitioned input features, or portions of the same spatially-partitioned input feature, in lockstep with one another to minimize latency and maximize throughput. The compiler may select a partitioning scheme (e.g., batch-partitioned, spatially-partitioned, and the like) that best exploits parallelism across multiple tensor processor clusters 724. For example, an input feature comprising a large digital image may be spatially-partitioned into four smaller portions (i.e., quartered) such that each tensor processor cluster 724A through D is assigned to process a quarter of the overall digital image. Here, because each tensor processor cluster 724 receives a portion of the same digital image, distribution instructions from the compiler may instruct tree DMA controller 718 to distribute a set of weights in a broadcast distribution for processing respective portions of the digital image in parallel. In another example, an input feature comprising an RGB image (comprised of red, green, and blue neural network channels) may be batch-partitioned such that tensor processor clusters 724-A, B, and C receive the red, green, and blue neural network channels, respectively. In this example, distribution instructions from the compiler may instruct tree DMA controller 718 to unicast three respective sets of weights (i.e., corresponding to red, green, and blue neural network channels) to tensor processor clusters 724-A, B, and C for processing the RGB image in parallel.
In one embodiment, tree DMA controller 718 may distribute a set of weights to tensor processor clusters 724 in one or more DMA packets. In particular, tree DMA controller 718 may instruct tree DMA 704 to generate a DMA packet that includes the set of weights to be sent to tensor processor clusters 724 via tree DMA bus 712. In one embodiment, each DMA packet may include a destination bitmap, a payload address, and a payload. The destination bitmap may be or include a header of the DMA packet in which each tensor processor cluster 724 is represented by a bit, or bits, within the destination bitmap. In one embodiment, the destination bitmap may be comprised of four bits, where each bit is used to represent a respective tensor processor cluster (e.g., tensor processor clusters 724-A through D) selected to process an input feature using the set of weights. In another embodiment, the destination bitmap may be comprised of 16 bits, where each bit is used to represent a respective tensor processor unit 726 (shown in
In the example illustrated in
In one embodiment, each DMA router 711 may comprise a system, device, or apparatus generally operable to direct DMA packets from shared RAM 708 to one or more tensor processor clusters 724 via tree DMA bus 712. In the example illustrated in
In one embodiment, each tensor processor cluster 724 may comprise a system, device, or apparatus generally operable to process input features. In particular, each tensor processor cluster 724 may be configured to perform various neural network operators (e.g., convolution, bias-add, normalization, residual addition, and the like) on an input feature received from shared RAM 708. In the example illustrated in
In one embodiment, cluster-level controller 730 may comprise a system, device, or apparatus generally operable to interpret coarse-grained tensor instructions received from a compiler, such as compiler 600 illustrated in
In the example illustrated in
Convolutional neural networks used in AR/VR applications must typically support input and output feature maps with a wide variety of shapes and sizes, especially along the channel dimension. With existing ASIC accelerators, supporting this diversity can result in decreased hardware utilization and a corresponding loss of performance and energy efficiency. The tensor processor units described in this application address this problem using flexible hardware resources and flexible computation-to-hardware mapping. For example,
In the illustrated example, multi-bank activation memory 736 includes local memory elements that store the input feature map elements to be provided to various ones of the subarrays 740. The first crossbar 738 is a first flexible many-to-many crossbar that reads input feature map elements (e.g., pixel values) from multi-bank activation memory 736 and provides them to the appropriate subarrays 740 in each cycle. In the illustrated example, weight buffer 746, which may be implemented as a register file, includes local memory elements that store the filter weights to be provided to various ones of the subarrays 740. The second crossbar 748 is another flexible crossbar that loads filter weights from weight buffer 746 and provides them to the appropriate subarrays 740 in each cycle.
In particular embodiments, each of the four compute subarrays 740 includes an array of multiply-and-accumulate (MAC) computation units of a given size that operate in parallel to apply the weights defined for a given 2D kernel of a given 3D convolution filter to portions of an input feature map and produce portions of an output feature map. The output feature map may have a different shape than the input feature map. A local controller 750 within tensor processor unit 726 may, e.g., in conjunction with a shared cluster-level controller, such as shared cluster-level controller 730 illustrated in
In particular embodiments, the optional output buffer 742 stores intermediate outputs from one or more subarrays 740 such that partial results may be accumulated prior to passing them through a reduction module, thus reducing the scope and/or complexity of the reduction operation. In particular embodiment, the multi-lane non-linearity unit 744 is a flexible reduction module configurable to take an intermediate computation output from the subarrays 740 and perform a reduction (i.e., addition) of subarray outputs to produce an output for tensor processor unit 726 as a whole, where appropriate.
This disclosure contemplates any suitable number of computer systems 900. This disclosure contemplates computer system 900 taking any suitable physical form. As example and not by way of limitation, computer system 900 may be an embedded computer system, a system-on-chip (SOC), a single-board computer system (SBC) (such as, for example, a computer-on-module (COM) or system-on-module (SOM)), a desktop computer system, a laptop or notebook computer system, an interactive kiosk, a mainframe, a mesh of computer systems, a mobile telephone, a personal digital assistant (PDA), a server, a tablet computer system, an AR/VR reality device, or a combination of two or more of these. Where appropriate, computer system 900 may include one or more computer systems 900; be unitary or distributed; span multiple locations; span multiple machines; span multiple data centers; or reside in a cloud, which may include one or more cloud components in one or more networks. Where appropriate, one or more computer systems 900 may perform without substantial spatial or temporal limitation one or more steps of one or more methods described or illustrated herein. As an example, and not by way of limitation, one or more computer systems 900 may perform in real time or in batch mode one or more steps of one or more methods described or illustrated herein. One or more computer systems 900 may perform at different times or at different locations one or more steps of one or more methods described or illustrated herein, where appropriate.
In particular embodiments, computer system 900 includes a processor 904, memory 906, storage 908, an input/output (I/O) interface 910, a communication interface 912, a bus 914, and an ML accelerator 902. Although this disclosure describes and illustrates a particular computer system having a particular number of particular components in a particular arrangement, this disclosure contemplates any suitable computer system having any suitable number of any suitable components in any suitable arrangement.
In particular embodiments, processor 904 includes hardware for executing instructions, such as those making up a computer program. As an example, and not by way of limitation, to execute instructions, processor 904 may retrieve (or fetch) the instructions from an internal register, an internal cache, memory 906, or storage 908; decode and execute them; and then write one or more results to an internal register, an internal cache, memory 906, or storage 908. In particular embodiments, processor 904 may include one or more internal caches for data, instructions, or addresses. This disclosure contemplates processor 904 including any suitable number of any suitable internal caches, where appropriate. As an example, and not by way of limitation, processor 904 may include one or more instruction caches, one or more data caches, and one or more translation lookaside buffers (TLBs). Instructions in the instruction caches may be copies of instructions in memory 906 or storage 908, and the instruction caches may speed up retrieval of those instructions by processor 904. Data in the data caches may be copies of data in memory 906 or storage 908 for instructions executing at processor 904 to operate on; the results of previous instructions executed at processor 904 for access by subsequent instructions executing at processor 904 or for writing to memory 906 or storage 908; or other suitable data. The data caches may speed up read or write operations by processor 904. The TLBs may speed up virtual-address translation for processor 904. In particular embodiments, processor 904 may include one or more internal registers for data, instructions, or addresses. This disclosure contemplates processor 904 including any suitable number of any suitable internal registers, where appropriate. Where appropriate, processor 904 may include one or more arithmetic logic units (ALUs); be a multi-core processor; or include one or more processors 904. Although this disclosure describes and illustrates a particular processor, this disclosure contemplates any suitable processor.
In particular embodiments, ML accelerator 902 may be similar to ML accelerator 614 illustrated in
In particular embodiments, memory 906 includes main memory for storing instructions for processor 904 to execute or data for processor 904 to operate on. As an example, and not by way of limitation, computer system 900 may load instructions from storage 908 or another source (such as, for example, another computer system 900) to memory 906. Processor 904 may then load the instructions from memory 906 to an internal register or internal cache. To execute the instructions, processor 904 may retrieve the instructions from the internal register or internal cache and decode them. During or after execution of the instructions, processor 904 may write one or more results (which may be intermediate or final results) to the internal register or internal cache. Processor 904 may then write one or more of those results to memory 906. In particular embodiments, processor 904 executes only instructions in one or more internal registers or internal caches or in memory 906 (as opposed to storage 908 or elsewhere) and operates only on data in one or more internal registers or internal caches or in memory 906 (as opposed to storage 908 or elsewhere). One or more memory buses (which may each include an address bus and a data bus) may couple processor 904 to memory 906. Bus 914 may include one or more memory buses, as described below. In particular embodiments, one or more memory management units (MMUs) reside between processor 904 and memory 906 and facilitate accesses to memory 906 requested by processor 904. In particular embodiments, memory 906 includes random access memory (RAM). This RAM may be volatile memory, where appropriate. Where appropriate, this RAM may be dynamic RAM (DRAM) or static RAM (SRAM). Moreover, where appropriate, this RAM may be single-ported or multi-ported RAM. This disclosure contemplates any suitable RAM. Memory 906 may include one or more memories 906, where appropriate. Although this disclosure describes and illustrates particular memory, this disclosure contemplates any suitable memory.
In particular embodiments, storage 908 includes mass storage for data or instructions. As an example, and not by way of limitation, storage 908 may include a hard disk drive (HDD), a floppy disk drive, flash memory, an optical disc, a magneto-optical disc, magnetic tape, or a Universal Serial Bus (USB) drive or a combination of two or more of these. Storage 908 may include removable or non-removable (or fixed) media, where appropriate. Storage 908 may be internal or external to computer system 900, where appropriate. In particular embodiments, storage 908 is non-volatile, solid-state memory. In particular embodiments, storage 908 includes read-only memory (ROM). Where appropriate, this ROM may be mask-programmed ROM, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), electrically alterable ROM (EAROM), or flash memory or a combination of two or more of these. This disclosure contemplates mass storage 908 taking any suitable physical form. Storage 908 may include one or more storage control units facilitating communication between processor 904 and storage 908, where appropriate. Where appropriate, storage 908 may include one or more storages 908. Although this disclosure describes and illustrates particular storage, this disclosure contemplates any suitable storage.
In particular embodiments, I/O interface 910 includes hardware, software, or both, providing one or more interfaces for communication between computer system 900 and one or more I/O devices. Computer system 900 may include one or more of these I/O devices, where appropriate. One or more of these I/O devices may enable communication between a person and computer system 900. As an example, and not by way of limitation, an I/O device may include a keyboard, keypad, microphone, monitor, mouse, printer, scanner, speaker, still camera, stylus, tablet, touch screen, trackball, video camera, another suitable I/O device or a combination of two or more of these. An I/O device may include one or more sensors. This disclosure contemplates any suitable I/O devices and any suitable I/O interfaces 910 for them. Where appropriate, I/O interface 910 may include one or more device or software drivers enabling processor 904 to drive one or more of these I/O devices. I/O interface 910 may include one or more I/O interfaces 910, where appropriate. Although this disclosure describes and illustrates a particular I/O interface, this disclosure contemplates any suitable I/O interface.
In particular embodiments, communication interface 912 includes hardware, software, or both providing one or more interfaces for communication (such as, for example, packet-based communication) between computer system 900 and one or more other computer systems 900 or one or more networks. As an example, and not by way of limitation, communication interface 912 may include a network interface controller (NIC) or network adapter for communicating with an Ethernet or other wire-based network or a wireless NIC (WNIC) or wireless adapter for communicating with a wireless network, such as a WI-FI network. This disclosure contemplates any suitable network and any suitable communication interface 912 for it. As an example, and not by way of limitation, computer system 900 may communicate with an ad hoc network, a personal area network (PAN), a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), or one or more portions of the Internet or a combination of two or more of these. One or more portions of one or more of these networks may be wired or wireless. As an example, computer system 900 may communicate with a wireless PAN (WPAN) (such as, for example, a BLUETOOTH WPAN), a WI-FI network, a WI-MAX network, a cellular telephone network (such as, for example, a Global System for Mobile Communications (GSM) network), or other suitable wireless network or a combination of two or more of these. Computer system 900 may include any suitable communication interface 912 for any of these networks, where appropriate. Communication interface 912 may include one or more communication interfaces 912, where appropriate. Although this disclosure describes and illustrates a particular communication interface, this disclosure contemplates any suitable communication interface.
In particular embodiments, bus 914 includes hardware, software, or both coupling components of computer system 900 to each other. As an example, and not by way of limitation, bus 914 may include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a front-side bus (FSB), a HYPERTRANSPORT (HT) interconnect, an Industry Standard Architecture (ISA) bus, an INFINIBAND interconnect, a low-pin-count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCIe) bus, a serial advanced technology attachment (SATA) bus, a Video Electronics Standards Association local (VLB) bus, or another suitable bus or a combination of two or more of these. Bus 914 may include one or more buses 914, where appropriate. Although this disclosure describes and illustrates a particular bus, this disclosure contemplates any suitable bus or interconnect.
Herein, a computer-readable non-transitory storage medium or media may include one or more semiconductor-based or other integrated circuits (ICs) (such, as for example, field-programmable gate arrays (FPGAs) or application-specific ICs (ASICs)), hard disk drives (HDDs), hybrid hard drives (HHDs), optical discs, optical disc drives (ODDs), magneto-optical discs, magneto-optical drives, floppy diskettes, floppy disk drives (FDDs), magnetic tapes, solid-state drives (SSDs), RAM-drives, SECURE DIGITAL cards or drives, any other suitable computer-readable non-transitory storage media, or any suitable combination of two or more of these, where appropriate. A computer-readable non-transitory storage medium may be volatile, non-volatile, or a combination of volatile and non-volatile, where appropriate.
Herein, “or” is inclusive and not exclusive, unless expressly indicated otherwise or indicated otherwise by context. Therefore, herein, “A or B” means “A, B, or both,” unless expressly indicated otherwise or indicated otherwise by context. Moreover, “and” is both joint and several, unless expressly indicated otherwise or indicated otherwise by context. Therefore, herein, “A and B” means “A and B, jointly or severally,” unless expressly indicated otherwise or indicated otherwise by context.
The scope of this disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments described or illustrated herein that a person having ordinary skill in the art would comprehend. The scope of this disclosure is not limited to the example embodiments described or illustrated herein. Moreover, although this disclosure describes and illustrates respective embodiments herein as including particular components, elements, feature, functions, operations, or steps, any of these embodiments may include any combination or permutation of any of the components, elements, features, functions, operations, or steps described or illustrated anywhere herein that a person having ordinary skill in the art would comprehend. Furthermore, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Additionally, although this disclosure describes or illustrates particular embodiments as providing particular advantages, particular embodiments may provide none, some, or all of these advantages.
