Patent Application
20180211158
Disclosed is a neuromimetic circuit comprising: a primary single photon optoelectronic neuron; a synapse in optical communication with the primary single photon optoelectronic neuron; and an axonic waveguide in optical communication with the primary single photon optoelectronic neuron and the synapse such that the axonic waveguide optically interconnects the primary single photon optoelectronic neuron and the synapse.
Also disclosed is a process for performing neuromimetic computing, the process comprising: receiving a primary signal by a primary single photon optoelectronic neuron; producing an axonic photonic signal by the primary single photon optoelectronic neuron; communicating the axonic photonic signal to a synapse; receiving the axonic photonic signal by the synapse; producing a dendritic signal in response to receipt of the axonic photonic signal; communicating the dendritic signal from the synapse to a secondary single photon optoelectronic neuron; receiving the dendritic signal by the secondary single photon optoelectronic neuron; producing a second axonic photonic signal in response to receipt of the dendritic signal to perform neuromimetic computing.
The following descriptions should not be considered limiting in any way. With reference to the accompanying drawings, like elements are numbered alike.
A detailed description of one or more embodiments is presented herein by way of exemplification and not limitation.
It has been discovered that a neuromimetic circuit includes neurons interconnected by integrated photonic waveguides, wherein neurons receive photonic signals from other neurons. Individual neurons sum received signals on a waveguide-integrated photon detector. When a signal exceeds a threshold, a current pulse is delivered to a waveguide-integrated photon source that delivers a signal downstream to other neurons. A strength of connection between two neurons can selectively be varied in hardware or dynamically. The neuromimetic circuit can receive a classical light level and include reverse-biased p-i-n photodetectors with conventional digital electronics components to threshold. Further, the neuromimetic circuit can receive a few-photon signals and can include superconducting single photon detectors to threshold.
In an embodiment, with reference to
Neuromimetic circuit 200 can include axonic waveguide 220 that communicates axonic photonic signal 218 from primary single photon optoelectronic neuron 210 to synapse 222. Secondary single photon optoelectronic neuron 228 is in optical communication with synapse 222 such that synapse 222 interconnects primary single photon optoelectronic neuron 210 and secondary single photon optoelectronic neuron 228. Here, dendritic communication path 226 is in optical communication with synapse 222 and secondary single photon optoelectronic neuron 228, wherein dendritic communication path 226 interconnects synapse 222 and secondary single photon optoelectronic neuron 228. In this manner, dendritic communication path 226 communicates dendritic signal 224 from synapse 222 to secondary single photon optoelectronic neuron 228, and secondary single photon optoelectronic neuron 228 can produce axonic photonic signal 230 that is communicated to recipient 234 via axonic waveguide 232.
An arrangement or number of primary single photon optoelectronic neuron 210, synapse 222, and secondary single photon optoelectronic neuron 228 can selected, e.g., based on a desired performance of neuromimetic circuit 200, e.g., for performing neuromimetic computing or to achieve a selected architecture. In an embodiment, with reference to
In an embodiment, with reference to
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An exemplary axonal waveguide arbor 221 is shown in
It is contemplated that primary single photon optoelectronic neuron 210 can include axonic waveguides 220 and axonal waveguide arbors 221 to route photonic signals and 220 and 221 can be nanophotonic waveguides made of silicon, silicon nitride, or other materials with index of refraction larger than the containing material or vacuum. It is contemplated that primary single photon optoelectronic neuron 210 can include synapses 222 utilizing superconducting photon detectors 250 to convert optical signals to electrical signals, and these synapses may be superconducting-nanowire single-photon detectors made from materials such as WSi, NbN, NbTiN, MoSi, or other superconducting materials. The synapses 222 may also include optically absorptive materials. The synapses 222 may also include electronic circuit elements such as resistors, inductors, capacitors, and Josephson junctions. In particular, Josephson junctions may play the role of converting photons to fluxons which can then be stored in the integrator 258.
It is contemplated that primary single photon optoelectronic neuron 210 can include photon emitters 284 to produce light or to redirect light from an external light source. The photon emitters 284 could be light-emitting diodes, lasers, or optical modulators.
It is contemplated that primary single photon optoelectronic neuron 210 can include superconducting voltage amplifiers 280 to produce sufficient voltage to produce light from a semiconductor or redirect light from an external source. These voltage amplifiers 280 could be elements making use of the superconducting-to-normal phase transition by heating a wire above its critical temperature or by exceeding a wire's critical current density. These voltage amplifiers 280 could also be comprised of Josephson junction amplifiers such as Suzuki stacks.
It is contemplated that primary single photon optoelectronic neuron 210 can include an axonal waveguide arbor 221 which routes photonic signals from neurons 210 or 228 to other neurons 228. The axonal waveguide arbor 221 may contain multiple planes of waveguides. The axonal waveguide arbor 221 may contain components such as in-plane waveguide crossings 290, inter-planar transitions 292, photonic beam taps 294, and axonal arbor waveguides 296.
In neuromimetic circuit 200, primary signal 212 can include external light sources, external current sources, external voltage sources, or photonic or electrical signals generated on chip to activate primary single-photon optoelectronic neuron and can include a light or electrical source.
In neuromimetic circuit 200, primary input communication path 214 can include free-space optical communication, fiber optics, waveguides, on-chip waveguides, or electrical wires to produce an optical or electrical signal and can be any optical or electrical communication path.
In neuromimetic circuit 200, primary source 216 can include can include external light sources, external current sources, external voltage sources, or photonic or electrical signals generated on chip to activate primary single-photon optoelectronic neuron and can include a light or electrical source.
In neuromimetic circuit 200, axonic photonic signal 218 can include photonic signals or any nature at any frequency to communicate between primary single photon optoelectronic neuron 210 and any other secondary single photon optoelectronic neuron 228 and can be electromagnetic radiation.
In neuromimetic circuit 200, axonic waveguide 220 can include a propagation path in free space or a dielectric medium, a dielectric waveguide made of silicon, silicon nitride, or other dielectric, insulating, metallic, or superconducting waveguide material to communicate axonic photonic signal 218 and can be a material to guide electromagnetic radiation.
In neuromimetic circuit 200, synapse 222 can include photon detectors, photon absorbers, photon sources, resistors, inductors, capacitors, superconducting circuit elements, Josephson junctions, and the like to modify a photonic signal and can be superconducting photon detectors, superconducting wires, Josephson circuits, or like device.
In neuromimetic circuit 200, dendritic signal 224 can include optical or electrical signals to communicate from the synapse 222 to the neuron 228 and can be photons, currents, supercurrents, or voltages.
In neuromimetic circuit 200, dendritic communication path 226 can include waveguides, electrical wires, superconducting wires, or free space to carry dendritic signal 224 and can be waveguides, electrical wires, superconducting wires, or free space.
In neuromimetic circuit 200, secondary single photon optoelectronic neuron 228 can include superconducting photon detectors, waveguides, electrical components such as resistors, capacitors, inductors, superconducting circuit elements, Josephson junctions, electrical wires, light sources such as light-emitting diodes and lasers to integrate signals and produce an output and can be semiconductors, metals, superconductors, dielectrics, or insulators.
In neuromimetic circuit 200, axonic photonic signal 230 can include light and electrical signals to communicate between secondary single-photon optoelectronic neurons 228 and can be photons, electrical currents, or electrical voltages.
In neuromimetic circuit 200, axonic waveguide 232 can include a propagation path in free space or a dielectric medium, a dielectric waveguide made of silicon, silicon nitride, or other dielectric, insulating, metallic, or superconducting waveguide material to communicate photonic signal 230 and can be a propagation path in free space or a dielectric medium, a dielectric waveguide made of silicon, silicon nitride, or other dielectric, insulating, metallic, or superconducting waveguide material.
In neuromimetic circuit 200, recipient 234 can include photon detectors or electrical signal detectors to receive the signal output from a neuron 210 or 228 and can be a superconducting photon detector, a semiconducting photon detector, a superconducting circuit, a waveguide, a wire, or a secondary single photon optoelectronic neuron 228.
In neuromimetic circuit 200, receiver 240 can include superconducting photon detectors, waveguides, electrical components such as resistors, capacitors, inductors, superconducting circuit elements, Josephson junctions, electrical wires, light sources such as light-emitting diodes and lasers to receive axonic photonic signals 218 and can be superconducting photon detectors, waveguides, electrical components such as resistors, capacitors, inductors, superconducting circuit elements, Josephson junctions, electrical wires, light sources such as light-emitting diodes and lasers.
In neuromimetic circuit 200, threshold signal 242 can include photonic signals, electrical currents, electrical voltages to communicate that a threshold has been reached and can be photonic pulses, electrical current pulses, or electrical voltage pulses.
In neuromimetic circuit 200, superconducting wire 244 can include superconducting wires, films, and materials to transmit electrical signals and can be Nb, WSi, NbN, NbTiN, Al, or other superconducting materials.
In neuromimetic circuit 200, transmitter 246 can include semiconductor lasers, semiconductor light emitting diodes, other semiconductor light sources, modulators, or switches to produce or redirect light and can be semiconductor light-emitting diodes or semiconducting switches.
In neuromimetic circuit 200, superconducting photon detector 250 can include semiconducting or superconducting photon detectors to produce electrical signals due to the presence of photons and can be superconducting nanowire single photon detectors or semiconducting photodiodes operating in photovoltaic or photoconductive mode.
In neuromimetic circuit 200, superconducting transfer synapse 252 can include electrical circuits to convert a photonic signal to the electrical domain and can be resistors, inductors, capacitors, Josephson junctions, or other superconducting circuit elements.
In neuromimetic circuit 200, synaptic signal 254 can include an electronic signal to communicate the output of superconducting transfer synapse 252 to integrator 258 and can be a photonic or electrical signal.
In neuromimetic circuit 200, integrator 258 can include electrical components to integrate the electrical signals 254 and can be superconducting wires, capacitors, inductors, or superconducting loops.
In neuromimetic circuit 200, integrator 268 can include electrical components to integrate the electrical signals 258 and can be superconducting wires, capacitors, inductors, or superconducting loops.
In neuromimetic circuit 200, integrated signal 260 can include an electrical supercurrent to store the inputs 254 and can be a superconducting electrical device such as a superconducting loop or wire.
In neuromimetic circuit 200, thresholding member 264 can include superconducting devices to detect a current or voltage threshold corresponding to a number of received photons or photonic detection events and can be a Josephson junction, nTron, yTron, superconducting wire, constriction, capacitor, or thermal sensor.
In neuromimetic circuit 200, photonic transfer synapse 266 can include photonic absorbers, generators, or switches to modify the axonic photonic signal 230 and can be an electro-absorption modulator, phase change material, quantum well structure, graphene, semiconductor gain medium, mechanically tunable coupler, or electrooptic modulator or switch.
In neuromimetic circuit 200, synaptic axon waveguide 270 can include a propagation path in free space or a dielectric medium, a dielectric waveguide made of silicon, silicon nitride, or other dielectric, insulating, metallic, or superconducting waveguide material to communicate optical signals and can be a propagation path in free space or a dielectric medium, a dielectric waveguide made of silicon, silicon nitride, or other dielectric, insulating, metallic, or superconducting waveguide material.
In neuromimetic circuit 200, synaptic dendrite waveguide 272 can include a propagation path in free space or a dielectric medium, a dielectric waveguide made of silicon, silicon nitride, or other dielectric, insulating, metallic, or superconducting waveguide material to route light and can be a propagation path in free space or a dielectric medium, a dielectric waveguide made of silicon, silicon nitride, or other dielectric, insulating, metallic, or superconducting waveguide material.
In neuromimetic circuit 200, superconducting voltage amplifier 280 can include superconducting and semiconducting circuit elements to produce sufficient voltage to generate or route light and can be a Suzuki stack, an hTron, an nTron, a yTron, or other circuit elements.
In neuromimetic circuit 200, transmitter electrical signal 282 can include electrical voltage or current pulses to drive the photon emitter 284 and can be an electrical voltage or current pulse.
In neuromimetic circuit 200, photon emitter 284 can include semiconducting light emitters such as LEDs and lasers, optical modulators, switches, and microwave sources to produce electromagnetic radiation and can be any source of electromagnetic radiation.
In an embodiment, a process for making neuromimetic circuit 200 includes a wafer on which devices will be fabricated; lithography; deposition; etching; cleaning; and packaging. In an embodiment, a process for making neuromimetic circuit 200 includes producing photon emitter 284; disposing axonic waveguides 220 and axonal waveguide arbor 221 on photon emitter 284 on substrate; disposing superconducting photon detector 250 on axonic waveguides; stacking and interspersing waveguiding and superconducting device layers with cladding layers in between; disposing superconducting wiring layers for superconducting wires 244, integrator 258/268, thresholding member 264, and superconducting voltage amplifier 280 on or in between waveguide and superconducting photon detector layers; packaging of devices with electrical and/or photonic connectivity.
Producing photon emitter 284 includes creating a p-n or p-i-n junction in a semiconducting material such as Si, GaAs, InGaAs, or other material with similar properties. Creating junction includes implanting of dopants and annealing. Producing emitter includes making electrical contact with metals or superconductors.
Disposing axonic waveguides 220 and axonal waveguide arbor 221 includes depositing dielectric waveguide material and optional cladding material on wafer containing photon emitter 284. Depositing materials can be performed at a temperature from 20° C. to 400° C. using plasma-enhanced chemical vapor deposition or sputtering. Disposing axonic waveguides 220 can include etching a selected shape or pattern in the deposited materials. Etching can include patterning with photolithography or electron-beam lithography followed by pattern transfer via reactive ion etching.
Disposing superconducting photon detector 250 on axonic waveguides includes depositing superconducting material and can be performed at a temperature from 20° C. and 400° C. using sputtering. Disposing 250 can include etching specific shapes and patterns in the deposited materials. Etching can include patterning with photolithography or electron-beam lithography followed by pattern transfer via reactive ion etching. Disposing axonic waveguides 220 and superconducting photon detectors 250 can be repeated multiple times, achieving multiple layers of waveguides and detectors, optionally with cladding layers in between. Planarizing between layers using chemical mechanical polishing can be performed.
Disposing superconducting wiring layers for superconducting wires 244, integrator 258/268, thresholding member 264, and superconducting voltage amplifier 280 on or in between waveguide and superconducting photon detector layers can include deposition of wire materials using sputtering or electron-beam evaporation. Patterning will utilize lift-off or etching lithographic techniques.
Packaging of devices with electrical or photonic connectivity can include mounting chips in packages with electrical or photonic connectivity. Making electrical or photonic connections to the devices on the chip can be performed.
Neuromimetic circuit 200 has numerous beneficial uses, including performing neuromimetic computing. According to an embodiment, a process for performing neuromimetic computing includes: receiving primary signal 212 by primary single photon optoelectronic neuron 210; producing axonic photonic signal 218 by primary single photon optoelectronic neuron 210; communicating axonic photonic signal 218 to synapse 222; receiving axonic photonic signal 218 by synapse 222; producing dendritic signal 224 in response to receipt of axonic photonic signal 218; communicating dendritic signal 224 from synapse 222 to secondary single photon optoelectronic neuron 228; receiving dendritic signal 224 by secondary single photon optoelectronic neuron 228; producing axonic photonic signal 230 in response to receipt of dendritic signal 224 to perform neuromimetic computing.
The process for performing neuromimetic computing further can include producing, by receiver 240, threshold signal 242 in response to receipt of primary signal 212.
In the process for performing neuromimetic computing, producing, by receiver 240, threshold signal 242 can include detecting, by superconducting photon detector 250, a photon; producing synaptic signal 254 based on detection of the photon; integrating synaptic signal 254 to produce integrated signal 260; and producing threshold signal 242 based on integrated signal 260.
In the process for performing neuromimetic computing, producing, by receiver 240, threshold signal 242 can include detecting, by photonic transfer synapse 266, primary signal 212; producing a photon in response to detection of primary signal 212; detecting, by superconducting photon detector 250, the photon; producing a signal based on detecting the photon; and producing threshold signal 242 based on the signal from superconducting photon detector 250.
The process for performing neuromimetic computing further can include receiving, by transmitter 246, threshold signal 242; and producing axonic photonic signal 218 in response to receipt of threshold signal 242.
The process for performing neuromimetic computing further can include amplifying, by transmitter 246, threshold signal 242; producing transmitter electrical signal 282 from threshold signal 242; and emitting axonic photonic signal 218 based on production of transmitter electrical signal 282.
In the process for performing neuromimetic computing, producing dendritic signal 224 in response to receipt of axonic photonic signal 218 can include receiving, by synaptic axon waveguide 270, axonic photonic signal 218; communicating axonic photonic signal 218 from synaptic axon waveguide 270 to synaptic dendrite waveguide 272; and producing dendritic signal 224 in response to receipt of axonic photonic signal 218 by synaptic dendrite waveguide 272.
The articles and processes herein are illustrated further by the following Examples, which are non-limiting.
Neural networks have proven effective for solving many difficult computational problems, yet implementing complex neural networks in software is computationally expensive. To explore the limits of information processing, it is necessary to implement new hardware platforms with large numbers of neurons, each with a large number of connections to other neurons. Here, a hybrid semiconductor-superconductor hardware platform for the implementation of neural networks and large-scale neuromorphic computing is described. The platform combines semiconducting few-photon light-emitting diodes with superconducting-nanowire single-photon detectors to behave as spiking neurons. These processing units are connected via a network of optical waveguides, and variable weights of connection can be implemented using several approaches. The use of light as a signaling mechanism overcomes fanout and parasitic constraints on electrical signals while simultaneously introducing physical degrees of freedom which can be employed for computation. The use of supercurrents achieves the low power density (1 mW/cm2 at 20-MHz firing rate) necessary to scale to systems with enormous entropy. Estimates comparing the proposed hardware platform to a human brain show that with the same number of neurons (1011) and 700 independent connections per neuron, the hardware presented here may achieve an order of magnitude improvement in synaptic events per second per watt.
Photons, based on their noninteracting bosonic nature, provide advantages over electrons for achieving spike-based communication over networks with a large number of connections between nodes. That is to say, photonic fanout overcomes limitations of electronic fanout. Superconducting circuits provide lower power densities than semiconducting circuits for systems with a larger number of processing units and greater total complexity. In a hardware platform, integrating photonic with superconducting devices includes a highly scaled, multiphysical system for computing complexity and experiments in information physics. A representation of such a device is shown in
The optoelectronic hardware platform is based on waveguide-integrated semiconductor light emitters working with superconducting detectors and electronics to implement weighted, directed networks. Optical signals between neurons are communicated through reconfigurable nanophotonic waveguides. Utilization of light-emitting semiconductors allows efficient access to photonic degrees of freedom (frequency, polarization, mode index, intensity, statistics, and coherence), which achieve complex functionality analogous to chemical signaling in biological organisms and possibly with information-processing capabilities far beyond. Light enables massive interconnectivity with no need for time-multiplexing schemes that can limit the event rates of complementary metal-oxide-semiconductor (CMOS) systems. Photonic signals are received and integrated by superconducting single-photon detectors. Firing thresholds and gain are controlled by a dynamic superconducting network, and neuron-generated photonic signals can reconfigure this current-distribution network. By employing superconducting electronics, we can approach zero static power dissipation, extraordinary device efficiencies, and utilize Josephson-junction circuits including single-flux-quantum devices.
Within this hardware platform, memory can be implemented via several means. These include temporally fixed synapses achieved with branching waveguides, synaptic weight variation via the actuation of locally suspended waveguides or through the use of magnetic Josephson junctions, or other magnetic and flux-storage components. The suspended waveguides that we explore in more detail in this work are reconfigurable on a time scale of 1 μs. None of these approaches draw power in the steady state.
The combination of efficient faint-light sources and superconducting-nanowire single-photon detectors interacting in an integrated-photonics environment enables neuronal operation with excellent energy efficiency, enormous intra- and inter-chip communication bandwidth, light-speed-limited latency, compact footprint, and relatively simple fabrication. The optoelectronic hardware platform is predicted to achieve 20 aJ/synapse event. By comparison, many CMOS systems are on the order of 20 pJ/synapse event, or in more recent work, hundreds of femtojoules per synapse event. For these reasons, the proposed platform appears promising for advanced neuromorphic computing at the highest level of performance, while the compact nature and room-temperature operation of CMOS circuits will inevitably remain better suited for a wide range of neuromorphic applications.
Information in neural systems is often referred to as “spike encoded,” as interconnected neurons transmit information to one another in pulses. An individual neuron (also referred to as a “processing unit,” or simply, “unit”) receives pulses from a number of upstream neurons. The neuron's input-output relation will be nonlinear, and if the integrated upstream signals exceed a certain threshold, the neuron may itself fire a pulse to its downstream connections. Superconducting optoelectronic circuits emulate several biological neural responses. These circuits use integrated light-emitting diodes (LEDs) as transmitters with optical detectors as receivers. Detectors and LEDs are included in this platform, and energy per firing event is calculated.
With regard to detector, a neuron that uses photonic signals requires both a source of photons and a photon detector. The choice of detector involves design and analysis consideration of the hardware platform. The hardware platform achieves massive scaling to large numbers of interacting neurons. Therefore, simple waveguide integration, extreme energy efficiency, high yield, and small size are concerns. Superconductors detectors provide single-photon detection in the infrared with zero static power dissipation and single-photon sensitivity to provide operation at the shot-noise limit. Because a system based on superconducting detectors provides operation in this limit, it offers a useful platform to test noise in learning and evolution of complex, dynamical systems.
There is an additional energy cost associated with cooling superconducting detectors to cryogenic temperatures for operation. Therefore, an alternative is to move away from low-light levels and use integrated detectors such as Si, Si defect, Ge-on-Si, or III-V detectors, either bonded to Si or on a fully III-V platform. Such detectors have low signal-to-noise ratio requiring operation with significantly higher optical powers than if superconducting detectors are employed. We choose superconducting-nanowire single-photon detectors (SNSPDs) due to the high efficiencies (>90%) at wavelengths below the Si band gap, simple on-chip waveguide integration, compact size, and speed. While operation at cryogenic temperatures imparts a fixed energy cost, the energy cost per operation is significantly decreased by allowing integration with superconducting electronics. Therefore, cryogenic systems are of use in a subset of neuromorphic applications where the required system size is sufficiently large that the savings in chip power outweigh the cryocooling cost. Additionally, low-temperature operation allows the use of certain LED designs that are not possible at room temperature.
With regard to an integrate-and-fire circuit, to encode information, the nodes of a neural network must have a nonlinear input-output relationship. In the system, that nonlinearity is achieved via the transition of wires from the superconducting phase to the normal-metal phase. These phase transitions can be induced by absorption of a photon or by exceeding the critical current. A single SNSPD can be designed to fire with close to unity efficiency upon absorbing a single photon. We can think of this as an integrate-and-fire neuron in the limit of a single-photon threshold. In order to obtain an integrate-and-fire response with a threshold photon number larger than one, SNSPDs can be configured in parallel (step response) or series (continuous response). In
The minimum duration of a spike event is determined by the emitter lifetime. The integration time of the neuron can be engineered to be within the range of a few hundred picoseconds up to seconds.
To model the spike probability of this circuit, we conduct Monte Carlo simulations of the device. The critical number of absorbed photons nc is given by
nc=NNW−Ibic, (1)
where NNW is the number of nanowires in the array, Ib is the bias current for the entire array, and ic is the critical current of a single wire. Although each individual firing event generates the same current pulse across the LED (i.e., a step response), a given number of input photons causes only the neuron to fire with some probability. This is due to the stochastic nature of the photon-absorption events. The results of these simulations are shown in
In
The simple model of
With regard to a differentiable response circuit, in biological systems, the neuron response is not that of a step function but rather a nonlinear response taking the form of a sigmoid. For certain neural-network back-propagation algorithms, the response is continuous and differentiable.
We use this circuit in a very different operating regime to detect a single photon with near-unity efficiency, wherein an SNSPD is driven close to its critical current, and the ensuing voltage pulse is measured across a 50-Ω resistor in parallel with the SNSPD. When a photon is absorbed, a 1-kΩ hot spot is produced, and nearly all current is diverted to the 50-Ω load. For the application at hand, the device is not intended to observe events of one or a few photons but rather hundreds to thousands. Thus, diverting the current through a high-impedance diode with I-V relationship approximated by Eq. (D1) enables thresholding with some dynamic range for higher numbers of absorbed photons. The model of this SND-based neuron considers simple joule heating behavior in that each photon-absorption event results in the same hot-spot resistance, when in reality, the hotspot resistance depends on the current through that branch of the circuit, which depends on the temporal dynamics of the preceding absorption events. A thorough study of these dynamics is the subject of future work.
The electro-optic performance of the SND is analyzed in
Based on the analysis of
Both the PND-based integrate-and-fire circuit of
The SND device lends itself to hundreds or thousands of connections. In this case, we can expect the thresholding number of photons to be approximately 1000, and, therefore, we select a nanowire with the length of 1000 hot spots. Given the hot-spot length of 100 nm, the entire length of the nanowire is on the order of 100 μm, as simulated in
With regard to an nTron current amplifier, introducing an amplifier into the circuits decouples firing threshold and LED gain. In a superconducting circuit, amplification can be achieved using the nTron, a three-terminal supercurrent amplifier. When the current in the gate terminal exceeds the critical current, the path from the source to drain is driven normal, diverting the bias current to the parallel load. This recently developed device has been used to drive loads of tens of kilohms, making it suitable for this application.
In
With regard to other neuromorphic circuits, we introduce several variants on those cells which enable diverse functionality desirable for neuromorphic computing.
Another functionality of neuromorphic circuits is that of inhibitory connections. Most neuronal connections provide feedforward excitation wherein an action potential produced by upstream neurons increases the probability of action potentials being produced by downstream neurons. But biological systems also exhibit connections wherein the firing of upstream neurons suppresses the probability of firing events by downstream neurons.
From an architectural standpoint, it may also be useful to establish purely electrical inhibitory connections. In
It is also advantageous to have a means by which a single neuron can moderate its own firing activity. Such behavior is straightforward to implement, as is shown in
In addition to self-feedback, biological neurons send both downstream signals as well as upstream signals when an action potential fires. The upstream signals are believed to be critical for spike-timing-dependent plasticity and synchronization of circuit behavior via threshold modification. To briefly hint at how self-feedback may be implemented in the proposed platform, the green arrow leaving the LED in
We describe several superconducting optoelectronic neuromorphic circuits covering a wide range of functions. We refer to members of this class of circuits as single-photon optoelectronic neurons (SPONs). We now proceed to discuss additional aspects of their performance.
With regard to energy consumption, SPON circuits are included in the neuromorphic computing platform, and we estimate the energy required for a firing event. A neuron firing event includes supplying current to the inductors associated with superconducting wires (including the detectors), charging the capacitor associated with the LED p-i-n junction, and driving current through the LED to produce light. For the case of the PND circuit of
In this model, we assume one inductor LSNSPD in the PND array for each photon, as well as a series inductance to achieve the desired temporal response. We assume each element of the PND is 500 squares, while the entire receiver array is in series with 5000 squares of inductance. At low photon numbers, the energy consumption from inductance is dominated by the series inductance, but for higher numbers, it is dominated by the PND array and grows linearly. The energy required for photon production is calculated simply as Egnv/η, where Eg is the band gap of Si, nv is the number of photons created, and η is the efficiency. Thus, within this model, the contribution to energy consumption due to photon creation is linear throughout. We use Eg in this model because it is an upper bound on the photon energy. Any photon transmitted through a Si waveguide will have energy below the band gap. We assume a superconducting material with a sheet inductance of 400 pHL/Υ (such as WSi), and a parallel-plate capacitive model for the LED.
In
In
In the case of the SND circuit of
An LED with 1% system efficiency operates in a nanophotonic environment at cryogenic temperature and with faint-light levels. We use 20 aJ/photon as a representative number for what this platform may achieve. We use the energy per photon as the energy per firing event per synapse (commonly referred to as the energy per synapse event) because the system produces neurons that threshold on a number of photons roughly equivalent to the number of connections made by the neuron. A neuron receiving 100 signals from upstream will threshold on 100 photons. It will produce 100 photons in a firing event and distribute them amongst 100 downstream synapses. Therefore, the energy per synapse event is calculated as the total energy of the firing event divided by the number of connections. In our case, for systems with 100 to 10 000 connections per unit, 20 aJ/synapse event is a realistic number.
The second law of thermodynamics informs us that to keep a system at 2 K, 150 W of cooling power is used per watt of power dissipated at 2 K. Assuming a 15% efficient cooling system, this gives an estimate of 1 kW of cooling power per watt of device power. Multiplying our conservative estimate of 20 aJ/synapse event by this factor of 103, the hardware achieves an energy consumption of 20 fJ/synapse event. Similarly, while the human brain uses 20 W to perform roughly 1014 synapse events per second, a power budget of 20 W corresponding to 20 mW of device power will enable our system to achieve 1015 synapse events per second. Success in developing LEDs with higher efficiency, reduction of the device inductance, and utilization of superconducting materials operating at higher temperatures will further increase the advantage. Additionally, while transistor technologies inevitably leak current, superconducting devices can be engineered to draw no power in the steady state and can be dc biased without loss using Josephson junctions.
With regard to an electrically injected light source, we analyze the operation and performance of the LED. We target operation efficiencies of around 10%. This efficiency is relatively easy to attain in III-V semiconductors such as GaAs and InP. However, for the application at hand, massive scaling is a priority, and massive scaling involves photonic electronic process integration. A single source with 100% efficiency is less desirable than the ability to scale to millions (and eventually billions) of sources each with 1% efficiency. We also use low-loss waveguides with the potential for reconfigurability.
One option is to implement these devices on a GaAs or InP substrate. These have been the materials of choice for photonic integrated circuits where light sources are of the utmost importance. Quantum-dot-well LED lasers can be electrically injected with high efficiency on this platform and combined with high-index (III-V) waveguides to form the synaptic connections. Another option is to implement the light sources in the III-V material and then couple to low-temperature deposited materials with low-loss waveguides such as a-Si or SiN. A III-V platform has the advantage of high-efficiency light sources, but massive scaling on III-V substrates has historically been more difficult and expensive than on Si substrates.
Another option is hybrid III-V silicon integration. Hybrid III-V silicon has followed one of three approaches: direct mounting, wafer bonding, or III-V material grown on Si. While direct mounting or wafer bonding are currently the preferred methods for optical interconnect applications, these applications typically require a single source that can be diverted to multiple components. For the proposed neuromorphic computing platform, we desire a separate electrically injected source for each neuron. Direct mounting, therefore, is not an option, but wafer bonding may be able to achieve the yield and reproducibility required for this application. Direct heteroepitaxial growth offers the most promise for hybrid integration with this system. In this case, the desired light source is templated III-V quantum dots grown in the intrinsic region of a lateral Si p-i-n junction. Promisingly, electrically injected single-photon emission has been demonstrated in these materials. While single-photon emission is not a requirement for the present application, a desirable property of the emitters is that they have low-photon-number variance (defined as the standard deviation of the number of photons output for a given input current pulse over an ensemble of measurements).
A light source is emissive centers in Si. These have proved unattractive for optical interconnects due to very low efficiencies at room temperature. Much work in this area was motivated by the prospect of room-temperature light sources for CMOS and telecommunications and, in particular, room-temperature lasers. This includes various point defects in Si including Er and other emissive centers giving rise to electric-dipole-mediated transitions as well as band-edge or Si nanocrystal-based emission processes. While the efficiencies of many of these emitters fall off exponentially with increasing temperature, the SNSPDs required for this application operate at cryogenic temperatures where many point defects have suitable efficiencies. A large number of emissive centers are under consideration for this application.
A challenge is integration of large numbers of emitters with the ultimate goal being billions integrated in a system. Many emissive centers can be easily fabricated in a CMOS-compatible process via ion implantation and annealing. A schematic of the desired device is depicted in
With co-implantation of multiple impurities, additional (color) degrees of freedom can be included in the platform. Similarly, on a III-V platform, we can take advantage of inhomogeneous broadening of the quantum-dot spectrum and tuning of dot size via templating or growth conditions.
The neuromorphic computing platform is not tied to any one of these light sources, and other possible light sources can be used that we have not discussed. For the calculations throughout the present work, we assume LEDs with 1% efficiency at 1.22 μm in a waveguiding medium with index of 3.52 with a cladding of 1.46 above and below.
A network of waveguides connects the processing units. Optical waveguides can provide improved performance over electrical connections by allowing individual neurons to integrate signals from many sources without the need for time multiplexing. Because of the additional energy cost associated with the capacitance of additional wires, electrical neurons use shared wires. Voltage pulses from different neurons on the same bus will interact. To prevent this, pulses can be delayed in time.
A network of optical waveguides can be implemented to form the connections between the SPON circuits presented. Each neuron has a waveguide exiting the LED and leading to many branching waveguides, which we liken to the axon and its arbor, and another set of integrating waveguides combining signals received from upstream neurons, which we liken to the dendritic arbor, as shown schematically in
With regard to a dendritic arbor, the dendritic arbor of a neuron collects signals from upstream neurons. For optoelectronic neurons, the equivalent of this is a waveguide network that combines optical signals from many other neurons to the neuron for detection. At each neuron, the device must be designed to combine the modes from a large number of waveguides on a PND or SND with low loss.
A schematic of the first approach is presented in
The second proposed design is better suited to scaling to larger numbers of inputs. It is shown in
For threshold-based computation, processing units with large numbers of connections are advantageous. Biological systems achieve massive interconnectivity with 3D branching networks and dedicated wires for each connection. To achieve this level of massive interconnectivity, we can use multilayer photonics. For massive scaling, we can use waveguide routing networks and dendritic arbors spanning several—and up to tens—of photonic and superconducting layers. A hybrid of the aforementioned spider web and stingray neuron designs can be implemented in which higher vertical-mode orders are utilized as well as higher lateral-mode orders, and massively multimode waveguides deliver their photon pulses to SNSPD receivers. These receivers can be implemented between waveguiding layers. The fully 3D multilayer photonic approach can be included in the neuromorphic platform for scaling, but such sophisticated processing can be included in advanced systems with 2D interconnectivity supporting hundreds of high-bandwidth connections per unit.
With regard to the axon and its arborization, the output waveguide (axon) from a unit's LED can split into as many branches as there are connections to be made. While such a power splitter may seem to be the time-reversed case of the dendritic arbor, the initial conditions make this device significantly easier to implement. In the case of the dendritic arbor, one cannot assume the optical field will populate the arbor modes in a particular manner. Thus, while a power splitter can readily couple from a single-mode waveguide into many other single-mode waveguides, multiple single-mode waveguides cannot simply merge their power into a single-mode waveguide unless a particular distribution of power is present in the input waveguides. Such power splitters can be made with a small footprint and low loss. Power splitters can be made in the third dimension with multilayer photonics, and such an implementation provides thousands of synapses with a volume of 10 μm3/synapse.
With regard to learning, reconfiguration, and plasticity, a neuromorphic computing system includes a strength of interaction between the connected units. These connection strengths, often referred to as the weight matrix, affect memory and learning. This weight matrix determines how much light from the firing of a particular neuron is coupled into any other neuron, analogous to the synaptic strength between two neurons in a biological system.
As a first implementation, fixed connection weights are useful for computing applications. This can be accomplished by branching the output waveguide from one neuron and routing those waveguide branches to various downstream target-neuron input waveguides.
While fixed interaction weights are useful, we develop a system in which the interaction strengths are variable. At cryogenic temperatures, modulators that rely on the thermo-optic effect or free-carrier injection may be ineffective, while electro-optic switches use a lot of space for this application. We include the electromechanically actuated waveguide couplers shown in
To assess the utility of such synapses for neuromorphic computing, one can specify a target application. Two classes of applications include supervised and unsupervised systems. For supervised systems, an input stimulus is injected into the system, the output is recorded, and the weight matrix is updated through a training algorithm to improve the output relative to a target. For such an application, one anticipates using control electronics to interface with the neuromorphic system, and arbitrary voltages can be applied to the various synaptic elements.
For more highly scaled implementations emulating the behavior of biological organisms, we turn our attention to unsupervised systems. Each synapse can be small as possible to enable massive scaling, but voltages can be modest because we want the activity in the circuits to be capable of reconfiguring the synapses. In particular, we want firing events from upstream neurons followed closely by firing events by downstream neurons to place charge on this MEMS capacitor (waveguide coupler) and thereby decrease the gap between the two waveguides and increase the optical coupling and, therefore, the synaptic strength. This coordinated charging of the membrane will accomplish spike-timing-dependent plasticity, an important learning and memory reinforcement mechanism in biological neural systems. In this mode of operation, we envision eliminating external control circuits and achieving the capacitor charging using integrated superconducting circuits to distribute current based on photon-absorption events. The storage of charge on a capacitor required for this device operation is very similar to dynamic random-access memory (DRAM), which is a mature technology. While implementing what is essentially spike-timing-dependent DRAM with suspended waveguide membranes presents a technical challenge, it offers a promising means to implement truly neuromorphic learning within this optoelectronic platform.
While the size of mechanical waveguide couplers and the voltages required for their operation are commensurate with the requirements for scaling this technology, an implementation of variable synaptic weights which does not rely on mechanically mobile components will be advantageous. It may be possible to implement synapses in the electronic domain by making use of superconducting circuit elements or magnetic elements such as magnetic tunnel junctions or magnetic Josephson junctions. Such an approach to memory will be investigated in future work. Additionally, we note that a variable weight can be achieved with a tunable Mach-Zehnder interferometer. However, the size of such devices makes them poorly suited to highly scaled systems.
With regard to networks and scaling, in
We now illustrate how the circuits can be used in systems by considering multilayer perceptron (MLP) and a general discussion of SOEN scaling.
With regard to multilayer perceptron, MLP provides insight into other applications of this platform in terms of quantities such as speed, size, and dynamic range. The MLP can include inputs incident on a weight matrix (array of synapses) that feed into a layer of neurons. The output of this layer of neurons projects to at least one more layer of weights and neurons, and often several, before being output from the system. In
Several factors determine the functionality of a MLP. These include the dynamic range of the inputs, the speed with which the inputs can be received, the bit depth of the synaptic weights, and the speed with which the weights can be reconfigured. From
The number of inputs, the number of connections per neuron, and the number of MLP layers all affect the size and complexity of MLP that can be fabricated on a given die. In
With regard to scaling of the MLP (or other similar neuromorphic computing systems), we consider the number of neurons in an area of 1 cm2 versus the number of connections per neuron, Nconn.
While the scaling to 10000 connections per neuron is formidable, the range of Nconn=100-1000 is promising and technologically consequential. As is the case for scaling CMOS neuromorphic platforms, utilization of die tiling plays a role in this technology. For this purpose, the SOEN platform is in an excellent position. Die can be tiled in 2D with several types of connectivity to adjacent die including electrical, single-flux-quantum, and photonic communication over interdie bridge waveguides. Additionally, tiling in the third dimension is possible with the usual bump-bonding approach for electrical connectivity as well as with free-space optical signals sent from one chip using vertical grating couplers and received by a chip above or below using SNSPD arrays. Information over such links can be encoded temporally, spatially, or in frequency with forgiving alignment tolerances. From
To analyze long-term scaling, we consider a system on the scale of the human brain. To this end, we envision tiling a 215×215 array of these die in a sheet to build a system with 32×106 neurons. Such a sheet will be approximately 1 mm thick. To achieve the scale of the brain, 2150 such sheets need to be stacked with inter-sheet coupling to construct a cube 2.15 m on a side and with a total volume of 10 m3. The system then comprises 7×1010 neurons or roughly the number contained in the human brain.
To achieve such a system, we envision sheets of die mounted in trays with in-plane fiber-optic connections leaving from the perimeter of the trays and out-of-plane free-space grating-to-SNSPD interconnects, thus, enabling the trays to slide laterally. Achieving inter-sheet connectivity without physical bonds enables access to die within the volume of the cube for diagnostics, repair, and local iteration and evolution. Massive interconnectivity between neurons on different die can be accomplished using such grating interconnects.
Of greater importance than the size of highly scaled systems is the power consumption. We again consider a system of SPONs with 700 connections each. Such a device consumes 2×10−17 J/synapse event, and with 700 connections, each firing event consists of 700 synapse events. Information processing in neuromorphic systems requires sparse event rates, so for the SOEN hardware wherein 20 MHz is achievable based on device limitations, 20 kHz represents a sparse rate. Note that this rate is a factor from (2×104) to (2×105) faster than biological event rates and a factor of 1000 faster than the CMOS demonstration which achieved 26 pJ/synapse event and was limited by time multiplexing. For the system under consideration, we have 7×1010 processing units which we consider to be firing at this rate with this energy per firing event, giving a total device power consumption of 20 W. These numbers give 5×1016 synapse events per second per watt. The system must be kept around 2 K, so we also include an additional 1 kW of cooling power per watt of device power. While this cooling power does not affect the power density (which ultimately limits scaling), and this 20 kW is minuscule compared to the tens of megawatts of a modern supercomputer, if we include this additional power in the calculation, we find that we achieve 5×1013 synapse events per second per watt.
To put this in perspective, the human brain also uses 20 W of device power, but by analogy to the inclusion of the cooling power in the above calculation, one must include the human's total power of 100 W which is necessary to sustain the brain's operational state. The brain has roughly 1011 neurons with roughly 7×103 synapses per neuron firing between 0.1 and 1 Hz. For the purposes of this calculation, we generously assume the rate is 1 Hz. This equates to 7×1012 synapse events per second per watt. Even with the 1-kW/W cooling power of the cryostat, we find that the number of synapse events per second per watt of the SOEN system exceeds that of the brain by an order of magnitude. The size of the SOEN system (10 m3, 2.15 m on a side) is, however, much larger than the biological brain.
Because signaling occurs predominantly in the optical domain, firing events can be directly imaged with a camera. For massively scaled systems, this direct optical imaging becomes a powerful metrological tool. Such a measurement technique can be used to monitor device and system performance across spatial and temporal scales in a manner analogous to functional magnetic resonance imaging of biological organisms.
With regard to cryogenics for a 1-m3 SOEN system. We seek a 4He sorption refrigerator capable of cooling a 1 m3 volume to 2 K with 20 W of cooling power. While this is a relatively large cryostat, it is certainly well within the realm of possibility. No new physical principles of operation need to be developed; it is simply a question of scaling up existing 4He cryogenic systems. Additionally, if suitable SNSPD materials can be found which operate at 4 K with high yield, 20 W of cooling power is straightforward to achieve. We are of the opinion that with the advancement of single-flux-quantum processors, superconducting qubit devices, and SOENs, large-scale cryogenic technology will advance significantly in the coming years. Presently, many conversations in advanced computing debate whether the technology which proves victorious will operate within a cryostat or at room temperature. A supercomputer can leverage optoelectronic devices on various material platforms to employ quantum principles, neuromorphic principles, and digital logic principles across various temperature stages. The device designer is faced with the task of optimizing hardware performance at each temperature stage.
With regard to advantages of optoelectronic neural networks, the unparalleled performance of the brain emerges from the enormous number of connections between neurons and the numerous complex signaling mechanisms available to the neurons. Optical signaling has an advantage over electronics in terms of the ability to route noninteracting signals in three dimensions without wiring parasitics.
The two components to enable photonic fanout and routing at an intradie level are multilayer waveguide power dividers and in-plane waveguide crossings. Both of these devices occupy a small area and operate with low loss and no RC penalty. Implementing these devices with roughly ten waveguiding layers appears optimal, comparable to the number of back-end-of-line metal layers used in CMOS for interconnect. With ten waveguiding layers, the desired routing between optoelectronic neurons involves in-plane waveguide crossings. The ability to implement multilayer power dividers and in-plane waveguide crossings with low loss and low cross talk allows dedicated communication lines for each interneuron connection.
On the receiving end, signals from an arbitrary number of SPONs can be received simultaneously, and time multiplexing is unnecessary. The system is conducive to encoding of information in both spike rate and timing. On an electronic platform, the length of an electronic signal line increases as the number of connections grows, resulting in a larger RC time constant. This increase in RC time constant with number of connections forces a speed or connectivity trade-off, leading most electronic neuromorphic implementations to share communication lines. Such a shared interconnect can transmit only a single voltage pulse within a time window, and this involves the number of connections between neurons and the firing rate of each neuron.
Other approaches that leverage phenomena unique to optics for neuromorphic computing have employed optical devices such as lasers and integrated microresonators. Laser cavities with strong light-matter interaction can be leveraged to realize complex nonlinear dynamics which can emulate the behavior of neurons. The frequency selectivity of integrated ring resonators can be used to achieve synaptic weights. Optical neural networks and spiking neurons based on these effects have been proposed and demonstrated. The SOEN platform operates in the few-photon regime with compact, energy-efficient components, enabling a large degree of scalability.
With regard to a visual cortex, a simple neural network (the MLP) can be built with SPONs, and the SOEN platform can be used in complex systems. The visual cortex is the most thoroughly studied region of the mammalian brain, yet there is still a great deal to be understood about information encoding from the retina through the thalamus and on to the visual cortex. A nonbiological experimental test bed is highly desirable to explore hypotheses. Biologically realistic supercomputer simulations of the brain can simulate only a small fraction of the brain cells in a small mammal at significantly reduced speed. The massive parallelism enabled by a scalable, biologically realistic hardware implementation of the many thousands of neurons involved in the visual system can provide more quick and efficient simulations, which may give further insight into the visual system, while also offering potential for image-processing applications.
An exemplary application of the hardware platform is a built-in retina that includes integrated SNSPDs, which are used as a pixel array for monolithic image acquisition and analysis. In
At the left of
From the retina, a small number of pixels project to each neuron in the thalamus without a large amount of branching. Similarly, the neurons of the thalamus project to the first layer of the visual cortex with minimal branching. Importantly, some of these connections are inhibitory and some are excitatory. While inhibitory connections are known to play a central role in information encoding in the visual system, the full scope of that role remains the subject of investigation. The biologically realistic mechanism for implementing inhibitory connections, as illustrated in
The granular layer receives feedforward signals from the thalamus, projects feedforward signals to the supragranular layer, and receives feedback from the supragranular layer. While still only minimally recurrent, neurons in the granular layer branch more heavily to form a larger number of connections across more neurons in the supragranular layer. The supragranular layer projects its output to other regions of the cortex and is also heavily recurrent. At the right of
For an initial SOEN visual system, we envision implementing the retina and thalamus on a single die, with a separate chip of 700 neurons being employed for the granular layer and a third chip of 700 mutually interacting neurons representing the supragranular layer. This experimental test bed may offer insight into outstanding questions such as how and why concentric circular patterns of retinal response are mapped to bars for processing in the visual cortex. With a simple system like that illustrated in
It is contemplated that neuromorphic systems can find trends and extract features from large and noisy data sets, reducing the dimensionality of those data sets. They can learn over time based on the temporal evolution of the data under consideration. Several societal challenges require this type of analysis of large numbers of complex, interacting units—exactly the type of system for which neuromorphic computing excels. These applications include monitoring of markets, Internet traffic metrology, detection of hacking attacks, modeling of climate systems, and phenotypic prediction from genomic data. For these applications, supercomputers at the limit of what is possible with CMOS implementations of the von Neumann architecture are presently in use. For many computational tasks, massively scaled systems employing parallel computation in a neuromorphic architecture can play a role in which the system can be used.
Another likely solution to the current bottlenecks facing supercomputers is superconducting electronics. In particular, Josephson-junction processors with single-flux-quantum logic are poised for use in the next generation of supercomputers. These processors can provide an improvement over CMOS in speed by roughly a factor of 100 with extremely high-energy efficiency. Our platform integrates into supercomputers, offering neuromorphic capability to von Neumann implementations and additional degrees of freedom to neuromorphic Josephson-junction systems, which are purely electronic. In addition, the SOEN platform may offer a means to transduce single-flux quantum pulses to the optical domain, for interconnects between chips and with the outside world (cryostat I/O) via photonic signaling.
With regard to integration time and refractory period, an integration time of a SPON is the time from the absorption of a photon until the receiver no longer has a memory of that absorption event. The behavior of integrate-and-fire devices with integration times less than infinity are referred to as leaky integrate-and-fire neurons. In the context of SPON devices, in the most basic case, this integration time is determined by the hot-spot relaxation time of the superconductor, which depends on the material quasiparticle dynamics which are governed by the electron-phonon coupling and the thermal conduction to the substrate. This thermal relaxation is a material-dependent quantity and can be as fast as 200 ps in NbN. In WSi, it is closer to 1 ns, and there may be materials for which it is even slower. Additionally, the bias current is shown to affect the quasiparticle recombination time. The choice of superconducting material and substrate may be leveraged to tune the integration time to a desired value in hardware, and the bias current may be used to modify it dynamically.
Further, the PND circuit shown in
The cylindrically symmetric nanowire arrays of
We note that in biological systems, the integration time is set by the RC time constant of the membrane and is typically approximately 1 ms or approximately 10-4-10-5 the firing period. Taking the 1-ns quasiparticle lifetime as the integration time, this corresponds to operating the system with (10-100)-kHZ event rates, a range that is straightforward to achieve.
The refractory period of a neuron refers to the time following a firing event during which the neuron cannot fire again. For a standard SNSPD, this dead time is governed by the L/R time constant of the series inductance of the SNSPD and the resistance across which the voltage pulse is being measured. In the case of WSi, this L/R time constant is usually 50 ns. This resistance is usually 50Ω, but in the present case, it is the impedance of the LED, which will be several kilohms, giving a shorter refractory period. If an application requires a longer refractory period, an additional series inductance can be added to achieve the desired delay. We note that in some SNSPD material systems, the L/Rtime constant must be chosen sufficiently large to avoid latching, while in the present application, the feedback circuit of
With regard to threshold condition for the PND array, we derive the expression of Eq. (1). The number of nanowires in the PND array is denoted by NNW. The number of nanowires driven normal by photons is denoted by nabs. The critical number of nanowires driven normal is denoted by nabsc. The bias current through the entire array is denoted by Ib. The current through a single wire of the array is denoted by i. The critical current of a single wire is denoted by ic.
In the steady state, before any photons are absorbed, nabs=0, and i=Ib/NNW. Upon absorption of a single photon, nabs=1 and i=Ib/(NNW−1). In the general case that n nanowires are driven normal by photons, nabs=n and i=Ib/(NNW−n). The condition for nabsc is i=ic=Ib/(NNW−nabsc). Rearranging gives nabsc=NNW−(Ib/ic).
With regard to integration of superconducting and wire detectors, the behavior of the SNSPD receivers are analyzed by optical absorption and statistical behavior of waveguide-integrated SNSPDs. We calculate the attenuation of light as a function of propagation length for 200-nm-thick waveguides (tWG) in the asymptotic slab regime. The waveguide refractive index is 3.52, the cladding index is 1.46, and our calculations are at a wavelength of 1220 nm. The nanowire is assumed to be 4 nm thick, 300 nm wide with a 50% fill factor, and n=3.25+2.19i. In
In
To address the design requirements of the PND, we consider the absorption statistics as calculated via Monte Carlo simulations. We perform 1000 trials each for different photon numbers incident on a PND with 40 SNSPDs.
μx(np,α)=1NNWNNWΣi=1xi, (C1)
where xi is the number of photons absorbed in the ith nanowire. From these values, the mean number of photons absorbed per nanowire μ−x is then calculated as the mean of the means (grand mean) in Eq. (C1).
The absorption probability in the PND has a mean number of absorbed photons per nanowire per pulse and the standard deviation of this number are both less than or equal to 1. In
σx(np,α)=√1NNWNNWΣi=1(xi−μx)2, (C2)
where μx is given by Eq. (C1). The mean of these standard deviations over the 1000 Monte Carlo trials (σ−x) is calculated, as is the standard deviation of the standard deviations. The center trace of each curve in
In
Consider the case where 40 photons are incident. We want all 40 of these photons to be absorbed by the 40 nanowires of the array, and, therefore, we want μ−x to be near unity. In
With regard to p-n junction model of the light-emitting diode, to model the performance of the emitters, we work with an analytical model of a p-n junction. Within this model, the current-voltage relationship for the junction is given by
Ip−n(V)=eA(√Dpτppn+√Dnτnnp)(eeV/kBT−1). (D1)
In Eq. (D1), the electron and hole diffusion coefficients are given by Dn=μn(kT/e) and Dp=μp(kT/e), where μn (μp) is the mobility of electrons (holes). The electron and hole lifetimes are given by τn and τp, respectively, which we take to be 40 ns. np is the concentration of electrons on the p-doped side of the junction, and pn is the concentration of holes on the n-doped side of the junction. To achieve low-temperature operation, we assume degenerate doping, and, therefore, a low mobility is to be expected. We use a value of 100 cm2/(V s) for both electron and hole mobilities. Because this value will be limited by ionized impurity scattering, it is likely to change little as the temperature decreases to 1 K.
From the electronic current, we calculate the photonic current as
Iv(V)=ηIp−n(V)e. (D2)
This model for the current through the diode is derived for an abrupt p-n junction, yet for the waveguide-integrated LED, one employs a p-i-n junction. Also, the present model breaks down at low temperature. We use T=300 K in Eq. (D1) because our measurements inform us that in the degenerate doping regime, the behavior is relatively constant to low temperature. Therefore, we use this model only as an approximation, and a more thorough numerical and experimental investigation of the devices to be used in the platform is the subject of future investigation. With this in mind, we approximate the capacitance of the junction using a simple parallel-plate model where the capacitance is given by C=εA/d, where ε is the material permittivity. A is the capacitor area, and d is the distance between the plates. We assume ε=12ε0. A=10 μm×100 nm, and d=300 nm. The energy associated with charging this capacitor is then calculated as Ec=1/2CV2. We note that for all values of photon number generated by the LEDs within this model, the applied voltage is below the built-in potential of the junction, so true forward-bias operation is not required. We anticipate that for the case of a p-i-n junction, the voltages required to achieve the same number of photons will increase slightly, but this can easily be accommodated by utilizing nanowires with larger critical currents.
With regard to waveguide design for the dendritic arbor, in
Having selected 200 nm as our waveguiding layer thickness, we consider the lateral mode spectrum, as shown in
We select a minimum inter-waveguide gap that avoids undesired coupling of modes in space. To do this, we calculate the supermode propagation constants as a function of the waveguide gap, as shown in
With regard to scaling, a length of an MLP layer is
L1=(Lt+Lg+Lx)NnNWG+2LWGNWG+Ln, (F1)
where Lt is the length of a single tap (or synapse) taken to be 10 μm; Lg is the length of a gap between two vertically running waveguides taken to be 5 μm, which is sufficiently wide to allow for undercut of the mechanically mobile synapses; Lx is the length of an intraplane waveguide crossing taken to be 3 μm; Nn is the number of neurons in a MLP layer [four in
Application of Shannon's theory of communication to neural systems provides quantification of information-processing capacity. The mutual information (in bits) between a neural system and a stimulus can be represented as
Im=∫ds∫drP[s]P[r|s] log 2(P[r|s]P[r]). (G1)
In Eq. (G1), P[r] is the probability of spike rate r occurring given a stimulus s, P[s] is the probability of stimulus s occurring from the set of all possible stimuli, and P[r|s] is the conditional probability of response rate r being evoked when the system is presented with stimulus s. With a neuromorphic computing platform, one wants to maximize the mutual information. Because Im within this model is calculated simply as a double integral over stimuli and response rates, we can maximize this quantity by increasing the limits of the integral. Because the proposed devices can operate at 20 MHz—and potentially up to 1 GHz by employing superconductors with faster thermal recovery—they can achieve response rates as well as receive stimulus across this entire bandwidth. The intrinsic speed of SPONs is greater than biological systems by a factor of 104, and this affects both the stimulus and response bandwidths in the double integral.
In addition to increasing the double integral by increasing the bandwidths, we can also maximize the bit depth. Signals can be discretized into roughly 11 bits. However, it is possible to increase this number further at the expense of size and efficiency.
We discuss the s and r in Eq. (G1) with the photonic input to the receiver array and photonic output pulse rate of the transmitter in mind, but the neuron of
Equation (G1) is derived by considering the difference between the entropy of a neuron's responses to a given stimulus and the noise entropy. As such, it is a measure of the information content at the device level and not at the system level. Information content of a population grows with the size of that population. Therefore, the high bandwidth of SPON devices, the ability to scale to units with large numbers of connections, and the ability to scale to systems with large numbers of units while maintaining a low power density points to the potential for complex systems with enormous information content. We note that these attributes are enabled by photonic signaling and superconducting electronics.
A photonic routing architecture efficiently uses space of a multi-plane (3D) photonic integration. A wafer with three planes of amorphous silicon waveguides was fabricated and characterized, demonstrating less than 3×10−4 dB loss per out-of-plane waveguide crossing, 0.05±0.02 per interplane coupler, and micro-ring resonators on three planes with a quality factors up to 8.2×104. We also explore a phase velocity mapping strategy to mitigate the cross talk between co-propagating waveguides on different planes. These results expand the utility of 3D photonic integration for applications such as optical interconnects, neuromorphic computing and optical phased arrays.
An advantage of photonic integration is the ease with which signals can be routed over a wide range of distances without incurring excessive power penalties, losses, or cross talk. Photonic interconnects are an approach for applications including massive connectivity, such as phased arrays and optical transceivers. The field of neuromorphic computing using photonics may realize all-to-all connectivity at the scale of 103 synaptic connections per neuron. The footprint of the interconnections is minimized if signals can cross paths at least a similar number of times. For single-plane photonics, compact multimode waveguide crossings with 0.02 dB loss per crossing have been demonstrated, allowing several dozen such junctions in a path without significantly impacting the power budget. However, to achieve connectivity orders of magnitude greater, multi-planar (3D) photonic integration becomes necessary to minimize the crossing loss and to increase the maximum photonic waveguide density.
Once the decision to expand vertically has been made, we are faced with many more choices concerning the platform: waveguide materials, confinement strength, interplane pitch, and interplane coupler (IPC) mechanism. These elements are intricately related through their impact on the critical metrics of crossing loss, cross talk, and the horizontal and vertical waveguide density that can be attained. To minimize the crossing loss and cross talk between out-of-plane waveguides, the optical modes must be sufficiently far apart to avoid scattering or evanescent coupling. However, increasing the interplane pitch also compromises size and efficiency of the IPCs. Previous work has demonstrated a two-plane crystalline/amorphous (c-Si/a-Si) platform with a 1.12 μm interplane pitch. Such a large separation allows reasonable mitigation of cross talk and crossing loss. However, it also poses a challenge for the IPC, which suffered from high loss (0.49 dB) and large dimensions (˜200 μm length). To overcome these penalties, smaller pitches and weaker modal confinement can be pursued instead. A silicon-nitride two-plane platform with a pitch of 900 nm was bridged with a 100 μm long adiabatic taper with <<0.01 dB loss per coupler. However, a consequence of the reduced inter-plane isolation was a severe penalty of 0.167 dB loss per out-of-plane waveguide crossing. With even smaller gaps, considerably shorter couplers can be achieved with similar loss performance, but nothing is done to address the issues of cross talk and crossing loss. One way to circumvent these issues is to employ an additional intermediate routing plane to allow efficient coupling between smaller gaps, while maintaining a large separation in crossing areas; this has been realized with 3.1×10−3 dB per crossing while co-integrating modulators and detectors on the same platform, showcasing the utility of 3D integration for high-density interconnect and transceiver applications. For interconnect applications including a few photonic planes, the need to utilize an entire plane to augment the interplane pitch may not significantly impact the cost or complexity of the system. However, it does not take full advantage of the surface area present in each layer, which could be used to attain even greater performance. Furthermore, for interconnects requiring many planes, the impact of doubling them is a consideration.
Much research has focused on crossing loss mitigation, and cross talk is generally avoided with the assumption of perpendicular (or significantly angled) waveguide orientations at overlapped regions on the wafer, to limit evanescent coupling-induced cross talk. Such a routing/layout scheme inherently has poor utilization of the available surface area and is incompatible with conventional, Manhattan-type routing layouts in which nearby paths will lie parallel to each other for considerable distances. An interconnect layout that prohibits co-propagation of out-of-plane waveguides will also increase the number of crossings and thus increase the optical loss.
The ideal 3D photonic integration architecture allows fully packed waveguide integration (density-limited by lateral coupling) on each additional plane, allows Manhattan-style routing with both perpendicular and parallel paths for different planes, and realizes compact, low-loss crossings and transitions, allowing maximum flexibility to the routing layout—a crucial consideration for further scaling. To realize these goals, we propose a 3D integration strategy comprising an efficient IPC design and a robust optical routing technique. We experimentally demonstrate the system's performance in the key performance metrics of crossing loss, cross talk, and interplane coupling loss. Additionally, to assess the film properties of the stack, we fabricate and characterize micro-ring resonators on each of the three planes. The platform is represented in
The platform was prototyped at the Boulder Microfabrication Facility at NIST. The fabrication flow is shown in
The fabricated devices were characterized via a tunable laser source and detector system. Light was coupled on- and off-chip via fully etched grating couplers and single-mode fibers at a nominal wavelength of 1540 nm. Statistical uncertainties are reported as the standard deviation in transmitted optical power for sets of reference paths consisting of two grating couplers and a waveguide.
With regard to micro ring resonators, the waveguiding performance and material quality of each of the three planes (P1-P3) was assessed by fabricating and measuring micro-ring resonators with radii of 30 μm (
Qa=6.1×104,Qb=6.4×104; P1:
Qa=6.2×104,Qb=8.2×104; P2:
Qa=2.5×104,Qb=3.2×104. P3:
Based on the Q-factor of 8.2×104 measured from the P2 resonator, a corresponding propagation loss of 7.4 dB per cm was observed. These values are likely predominantly limited by pattern and etch-induced sidewall roughness (based on the earlier observed slab propagation loss of 1.4 dB per cm), which was not optimized in this work.
With regard to inter-plane couplers, interplane pitch of 900 nm, combined with the high-confinement a-Si core, poses a challenge for the IPC. State-of-the-art IPCs for similar interplane pitches exhibit typical lengths between 100 and 200 μm, or compromise the efficiency for shorter device lengths (˜1 dB over a 60 μm long coupler).
An effective IPC design, consisting of a tapered width transition between two waveguides, should behave adiabatically (which enhances bandwidth and tolerance to fabrication errors) but should also be designed to enhance the evanescent coupling strength between the two waveguides. This can be achieved with narrower waveguides to reduce the mode confinement. For large interplane pitches, the average waveguide width throughout the transition should be minimized to the point that it does not introduce losses due to sidewall roughness. However, a simple linear taper of the waveguide width between the maximum and minimum values results in excessively long couplers, since little coupling occurs until the waveguide dimensions are significantly narrowed. We have thus implemented a two-level IPC design, making use of a “fast” initial taper to rapidly compress the waveguide width at the outer regions, combined with a “slow” extended taper region over which a much smaller width transition occurs [
With regard to waveguide crossings, we investigate the performance of perpendicular out-of-plane waveguide crossings. Test devices
With regard to cross talk, to effectively utilize the space available, and to avoid dilemmas in the routing, the cross talk between co-propagating waveguides on different planes must be managed. We now explore the performance of phase velocity mapping of waveguides on adjacent planes via a small difference in waveguide width. This was done by co-propagating P1 and P2 or P3 waveguides for a variable distance and measuring the maximum ratio of upper-waveguide power to the total power from both arms. For P1/P2 devices, both cases of Δww=0 nm and Δww=80 nm were considered, while the P1/P3 case utilized the same nominal waveguide widths. Test devices [
For efficient photonic routing in 3D-integrated systems, a prototype implementation was experimentally realized with three planes of amorphous silicon waveguides. Detailed characterization reveals exceptional performance in the critical performance metrics of out-of-plane crossing loss, interplane coupler loss, and cross talk. Micro-ring resonators were fabricated on all three planes, showing a quality factor up to 8.2×104. An out-of-plane waveguide crossing loss of 3×10−3±7×10−4 dB per crossing for adjacent planes (P1/P2) was observed, and for double-spaced planes (P1/P3), the crossing loss was below the measurement limit of 3×10−4 dB per crossing. The large interplane pitch was bridged with a compact and efficient two-stage interplane coupler (IPC) design, showing a peak performance of 0.05±0.02 dB per coupler at λ=1526 nm. Next, anticipating that Manhattan-style routing will be a necessary feature of high-density 3D optical interconnects, we investigated a means of enabling waveguides on adjacent planes to be propagated parallel to each other for arbitrary distances, without introducing excessive cross talk. By slightly modifying the waveguides on alternate planes to be 80 nm wider, continuous constructive interference is disrupted. Directly overlapped waveguides employing this technique showed a nearly six-fold reduction in cross talk compared to those with identical widths. This could later be combined with a simple constant horizontal offset (half of the intraplane pitch) that will lead to <<−33 dB cross talk between P1/P2 waveguides. These results, showing drastically increased layout flexibility and space-efficiency, bolster the case for 3D integrated photonics.
While one or more embodiments have been shown and described, modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustrations and not limitation. Embodiments herein can be used independently or can be combined.
Reference throughout this specification to “one embodiment,” “particular embodiment,” “certain embodiment,” “an embodiment,” or the like means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of these phrases (e.g., “in one embodiment” or “in an embodiment”) throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, particular features, structures, or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments.
All ranges disclosed herein are inclusive of the endpoints, and the endpoints are independently combinable with each other. The ranges are continuous and thus contain every value and subset thereof in the range. Unless otherwise stated or contextually inapplicable, all percentages, when expressing a quantity, are weight percentages. The suffix “(s)” as used herein is intended to include both the singular and the plural of the term that it modifies, thereby including at least one of that term (e.g., the colorant(s) includes at least one colorants). “Optional” or “optionally” means that the subsequently described event or circumstance can or cannot occur, and that the description includes instances where the event occurs and instances where it does not. As used herein, “combination” is inclusive of blends, mixtures, alloys, reaction products, and the like.
As used herein, “a combination thereof” refers to a combination comprising at least one of the named constituents, components, compounds, or elements, optionally together with one or more of the same class of constituents, components, compounds, or elements.
All references are incorporated herein by reference.
The use of the terms “a” and “an” and “the” and similar referents in the context of describing the invention (especially in the context of the following claims) are to be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. “Or” means “and/or.” Further, the conjunction “or” is used to link objects of a list or alternatives and is not disjunctive; rather the elements can be used separately or can be combined together under appropriate circumstances. It should further be noted that the terms “first,” “second,” “primary,” “secondary,” and the like herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The modifier “about” used in connection with a quantity is inclusive of the stated value and has the meaning dictated by the context (e.g., it includes the degree of error associated with measurement of the particular quantity).
This application claims the benefit of U.S. Provisional Patent Application Ser. No. 62/450,266 filed Jan. 25, 2017, the disclosure of which is incorporated herein by reference in its entirety.
This invention was made with United States Government support from the National Institute of Standards and Technology (NIST), an agency of the United States Department of Commerce. The Government has certain rights in the invention. Licensing inquiries may be directed to the Technology Partnerships Office, NIST, Gaithersburg, Md., 20899; voice (301) 301-975-2573; email tpo@nist.gov; reference NIST Docket Number 17-001US1.
| Number | Date | Country | |
|---|---|---|---|
| 62450266 | Jan 2017 | US |
