The disclosure relates to a semiconductor device, more particularly to a nitride based semiconductor device.
In recent years, with improvements in technology and efficiency, ultraviolet light emitting diodes (UV LEDs), with their longer lifespan and smaller volume, have been slowly replacing mercury lamps of lower efficiency. With the Minamata Convention on Mercury coming into effect in 2020, the global ban on mercury would further expedite the rise of application of the UV LEDs.
A conventional deep UV LED has an aluminum nitride (AlN)-based buffer layer.
Therefore, the object of the disclosure is to provide a semiconductor device that can alleviate at least one of the drawbacks of the prior art.
According to the disclosure, a nitride based semiconductor device includes a buffer layer, a three-dimensional stress tuning layer formed on the buffer layer, a first-type semiconductor layer formed on the three-dimensional stress tuning layer, an active layer formed on the first-type semiconductor layer, and a second-type semiconductor layer formed on the active layer.
The three-dimensional stress tuning layer and the buffer layer cooperatively define an interface therebetween. The interface has a three-dimensional composition distribution.
Other features and advantages of the disclosure will become apparent in the following detailed description of the embodiment with reference to the accompanying drawings, of which:
Referring to
In this embodiment, epitaxial growth of the buffer layer 220, the three-dimensional stress tuning layer 260, the first-type semiconductor layer 230, the active layer 240 and the second-type semiconductor layer 250 in sequence on the substrate 210 is exemplified to be performed using metal organic chemical-vapor deposition (MOCVD) technique, and the substrate 210 is exemplified to be a sapphire substrate.
The buffer layer 220 formed on the substrate 210 has a thickness greater than 100 nanometers. In certain embodiments, the thickness is between 1000 nanometers and 3000 nanometers. The three-dimensional stress tuning layer 260 and the buffer layer 220 cooperatively define an interface 270 therebetween. The buffer layer 220 has an irregular top surface that is connected to the three-dimensional stress tuning layer 260 and that cooperates with the three-dimensional stress tuning layer 260 to define the interface 270. The irregular top surface of the buffer layer 220 includes a base portion 221 and a plurality of protruding portions 222 protruding from the base portion 221, each of the protruding portions 222 having a height larger than 10 nanometers from the base portion 221. In certain embodiments, the width of each protruding portion 222 is larger than 100 nanometers. The irregular top surface of the buffer layer 220 may be formed under growth conditions including a relatively low growth temperature and a relatively high ratio of Group V/III, where the growth temperature is between 1000° C. and 1350° C. and the ratio of Group V/III is larger than 1500. An excess of ammonia gas may cause pre-reaction problems for organic metal sources for forming the buffer layer 220. In this embodiment, the growth temperature is exemplified to be at 1200° C. and the ratio of Group V/III is exemplified to be between 2000 and 3000.
The three-dimensional stress tuning layer 260 grown on the buffer layer 220 has a growth temperature between 1000° C. and 1300° C., a thickness between 100 nanometers and 5000 nanometers, and has a lattice constant larger than that of the buffer layer 220. The three-dimensional stress tuning layer 260 may have a structure formula of AlxGayIn1-x-yN, where x≥0, y>0, and x+y≤1. The flux of aluminum and gallium may be controlled to modify the lattice constant of the three-dimensional stress tuning layer 260. In this embodiment, x is between 0.2 and 0.9. In certain embodiments, x is between 0.5 and 0.9.
The n-type semiconductor layer for the first-type semiconductor layer may have a structure formula of Alx1Ga1-x1N where x1 is between 0.5 and 1.
The active layer 240 has a quantum well structure with a structural formula of Alx2Ga1-x2N/Alx3Ga1-x3N, wherein x2<x3, x2 is between 0.3 and 0.9, and x3 is between 0.6 and 1. In certain embodiments, x2 is 0.4 and x3 is 0.6.
The second-type semiconductor layer 250 may include a p-type aluminum gallium nitride (AlGaN) barrier layer having a structural formula of Alx4Ga1-x4N, where x4 is between 0.3 and 0.9, a magnesium-doped p-type AlGaN layer also having a structural formula of Alx4Ga1-x4N, and a magnesium-doped p-type gallium nitride (GaN) layer.
In this embodiment, the interface 270 has a three-dimensional composition distribution.
In this embodiment, the lattice constant of the stress tuning layer 260 is between that of the buffer layer 220 of AlN and the first-type semiconductor layer 230 of Alx1Ga1-x1N. If the stress tuning layer 260 is grown at a relatively high temperature, the adjustment of the aluminum content may be based on a growth parameter of the first-type semiconductor layer 230. For example, a flux of trimethyl aluminum (TMAl) may be fixed while a flux of trimethyl gallium (TMGa) is varied. For example, when the flux of TMGa for growing the first-type semiconductor layer 230 is designated by f1 and the flux of TMGa for growing the three-dimensional stress tuning layer 260 is designated by f2, the f1 and f2 may satisfy the relation of 0<f2<f1. Alternatively, the f1 and f2 may satisfy an equation of f2=f1/2. The flux of TMGa may be fixed while varying the flux of the TMAl in a similar manner.
In this embodiment, the aluminum content may also be controlled by controlling the respective growth temperatures of the buffer layer 220 of AlN, three-dimensional stress tuning layer 260 of AlxGa1-xN and the first-type semiconductor layer 230 of Alx1Ga1-x1N. For example, when the growth temperature of the stress tuning layer 260 is designated to be T1, the growth temperature of the buffer layer 220 is designated to be T2, and the growth temperature of the first-type semiconductor layer 230 is designated to be T3, the T1, T2 and T3 may satisfy a relation of T3<T1<T2. Alternatively, the T1, T2 and T3 may satisfy an equation of T1=(T2+T3)/2.
In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiment. It will be apparent, however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. It should also be appreciated that reference throughout this specification to “one embodiment,” “an embodiment,” an embodiment with an indication of an ordinal number and so forth means that a particular feature, structure, or characteristic may be included in the practice of the disclosure. It should be further appreciated that in the description, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects, and that one or more features or specific details from one embodiment may be practiced together with one or more features or specific details from another embodiment, where appropriate, in the practice of the disclosure.
While the disclosure has been described in connection with what is considered the exemplary embodiment, it is understood that this disclosure is not limited to the disclosed embodiment but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
Number | Date | Country | Kind |
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2017 1 0827123 | Sep 2017 | CN | national |
This application is a continuation-in-part (CIP) of International Application No. PCT/CN2018/078652, filed on Mar. 12, 2018, which claims priority to Chinese Invention Patent Application No. 201710827123.6, filed Sep. 14, 2017.
Number | Name | Date | Kind |
---|---|---|---|
20020020850 | Shibata | Feb 2002 | A1 |
20090001409 | Takano | Jan 2009 | A1 |
20140332849 | Jang | Nov 2014 | A1 |
20180145214 | Chen et al. | May 2018 | A1 |
Number | Date | Country |
---|---|---|
105489723 | Apr 2016 | CN |
106784216 | May 2017 | CN |
107634128 | Jan 2018 | CN |
Entry |
---|
Cheng, Kai, et al., “Flat GaN Epitaxial Layers Grown on Si(111) by Metalorganic Vapor Phase Epitaxy Using Step-Graded AlGaN Intermediate Layers.” Journal of Electronic Materials, vol. 35, No. 4, 2006, pp. 592-598., doi:10.1007/s11664-006-0105-1. (Year: 2006). |
He, Chengyu, et al. “Growth and Characterization of Ternary AlGaN Alloy Nanocones across the Entire Composition Range.” ACS Nano, vol. 5, No. 2, 2011, pp. 1291-1296., doi:10.1021/nn1029845 (Year: 2011). |
Search Report issued to PCT application No. PCT/CN2018/078652 by the CNIPA dated May 31, 2018. |
Search Report appended to an Office Action, which was issued to Chinese counterpart application No. 201710827123.6 by the CNIPA dated Oct. 8, 2018, with an English translation thereof. |
Number | Date | Country | |
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20190280160 A1 | Sep 2019 | US |
Number | Date | Country | |
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Parent | PCT/CN2018/078652 | Mar 2018 | US |
Child | 16423492 | US |