Patent Application
20250006861
This application claims priority to Japanese Patent Application No. 2023-105120 filed on Jun. 27, 2023, and Japanese Patent Application No. 2023-144515 filed on Sep. 6, 2023, the disclosures of which are hereby incorporated by reference in their entireties.
The present disclosure relates to a nitride semiconductor light emitting element and a method of manufacturing the same.
The development of a nitride semiconductor light emitting element that emits ultraviolet light has been in progress. For example, Japanese Patent Publication No. H09-153645 discloses a light emitting element having an emission layer that emits ultraviolet light.
There is room for improvement in terms of the light emission output of a nitride semiconductor light emitting element that emits ultraviolet light as compared to a light emitting element that emits visible light.
One object of the present disclosure is to provide a nitride semiconductor light emitting element that emits ultraviolet light with an improved light emission output and a method of manufacturing the same.
A nitride semiconductor light emitting element according to the present disclosure is a light emitting element comprising an n-side semiconductor layer, a p-side semiconductor layer, and an active layer positioned between the n-side semiconductor layer and the p-side semiconductor layer, wherein
A method of manufacturing a nitride semiconductor light emitting element according to the present disclosure includes:
According to an embodiment of the present disclosure a high output nitride semiconductor light emitting element which emits ultraviolet light and a method of manufacturing the same can be provided.
Certain embodiments and examples of the present disclosure will be explained below with reference to the accompanying drawings. The light emitting elements and the methods of manufacturing light emitting elements described below are provided to give shape to the technical ideas of the present disclosure, and do not limit the invention unless otherwise specifically stated.
In the drawings, the same reference numerals denote members having the same functions. To make the features easily understood, the descriptions of the features are distributed among the embodiments and examples, but the constituent elements described in different embodiments can be replaced or combined in part. The explanation of common features already described in embodiments appearing earlier might be omitted in the subsequent embodiments where the explanation is focused only on the differences. The same or similar effects attributable to the same or similar features, in particular, will not be mentioned each time an embodiment or example is discussed. The sizes of and positional relationships between the members shown in each drawing might be exaggerated for clarity of explanation. For example, the drawings accompanying the present specification are primarily schematic diagrams showing the stacked structures, and do not necessarily accurately reflect the thickness of each layer.
As shown in
The active layer 30 includes, successively from the n-side semiconductor layer 20 side, a first barrier layer 31 containing Al and an n-type impurity, a first well layer 32 containing Al and emitting ultraviolet light, a second barrier layer 33 containing Al, and a second well layer 34 containing Al and emitting ultraviolet light, in which the highest n-type impurity concentration peak in the first barrier layer 31 is located closer to the p-side semiconductor layer 50.
The Al composition ratio of the first barrier layer 31 is higher than the Al composition ratio of the second barrier layer 33.
According to the nitride semiconductor light emitting element described above, the light emission efficiency of the first well layer 32 can be improved, increasing the ultraviolet light emission output as described in detail later.
In other words, the nitride semiconductor light emitting element according to this embodiment was created to achieve a high ultraviolet light emission output by focusing on the room for improvement in the light emission efficiency of the well layer located closer to the n-side semiconductor layer 20 than to the p-side semiconductor layer 50 in a nitride semiconductor light emitting element having a multiple quantum well structure and emitting ultraviolet light, and increasing the light emission efficiency in the well layer that is located closer to the n-side semiconductor layer 20.
The substrate 10 and each semiconductor layer will be specifically described below.
For the material for the substrate 10, for example, sapphire, silicon (Si), gallium nitride (GaN), aluminum nitride (AlN), or the like can be used. A substrate 10 formed of sapphire is preferable, as it has a high transmittance with respect to the ultraviolet light from the active layer 30. The semiconductor structure body 100 can be disposed, for example, above C-plane of the sapphire substrate, and is preferably disposed above a face oblique to the C-plane of the sapphire substrate forming a 0.2 to 2 degree angle with the a-axis or the m-axis of the sapphire substrate. The thickness of the substrate 10 can be set, for example, in a range of 150 μm to 800 μm. The nitride semiconductor light emitting element 1 does not have to have a substrate 10.
A semiconductor structure body 100 is a stack structure in which nitride semiconductor layers are stacked. The nitride semiconductor can be any semiconductor obtained by varying the composition ratio x and y within their ranges in the chemical formula InxAlyGa1-x-yN (0≤x 1, 0≤y≤1, x+y≤1).
For an underlayer 11, for example, a layer formed of AlN can be used. The underlayer 11 functions to reduce lattice mismatch between the substrate 10 and the nitride semiconductor layers disposed above the underlayer 11. The thickness of the underlayer 11 can be set, for example, in a range of 0.5 μm to 4 μm, preferably 1.5 μm to 4 μm. The underlayer 11 may include a buffer layer, and the buffer layer is located near the surface of the substrate 10. In the present specification, the thickness of each semiconductor layer refers to the thickness in the stacking direction of the semiconductor structure body 100.
A superlattice layer 12 may be, for example, a multilayer structure in which first semiconductor layers and second semiconductor layers having a different lattice constant from that of the first semiconductor layers are alternately formed. The superlattice layer 12 has the function of reducing the stress occurring in the semiconductor layers disposed above the superlattice layer 12. The superlattice layer 12 can be a multilayer structure in which AlN layers and aluminum gallium nitride (AlGaN) layers are alternately stacked. The number of pairs of first and second semiconductor layers in the superlattice layer 12 can be set to 20 to 50 pairs. In the case in which the first semiconductor layers are AlGaN and the second semiconductor layers are AlN layers, for example, the first semiconductor layer can be 5 nm to 30 nm in thickness, and the second semiconductor layer can be 5 nm to 30 nm in thickness.
An n-side semiconductor layer 20 includes one or more n-type semiconductor layers. Examples of n-type semiconductor layers include semiconductor layers containing an n-type impurity, such as silicon (Si), germanium (Ge), or the like. An n-type semiconductor layer is, for example, an AlGaN layer containing aluminum (Al), gallium (Ga), and nitrogen (N), and may contain indium (In). For example, the n-type impurity concentration of an n-type semiconductor layer containing Si as an n-type impurity is in a range of 5×1018/cm3 to 1×1020/cm3. The n-side semiconductor layer 20 has only to have the function of supplying electrons to the active layer 30, and may include an undoped layer. Here, an undoped layer is a layer not intentionally doped with an n-type impurity or a p-type impurity. In the case where an undoped layer is adjacent to a layer intentionally doped with an n-type impurity and/or a p-type impurity, the undoped layer might contain the n-type impurity and/or the p-type impurity diffused from the adjacent layer.
As shown in
For the undoped layer 21, for example, an undoped AlGaN layer can be used. In the case of using an AlGaN layer as the undoped layer 21, the Al composition ratio of the AlGaN layer can be set, for example, in a range of 25% to 70%.
For the n-side contact layer 22, for example, a layer formed of AlGaN and containing an n-type impurity can be used. In the case of using an AlGaN layer as the n-side contact layer, the Al composition ratio of the AlGaN layer can be set, for example, to 25% to 70%. In the present specification, an AlGaN layer having an Al composition ratio of 50%, for example, means that the composition ratio x in the chemical formula AlXGa1-XN is 0.5. The n-type impurity concentration of the n-side contact layer 22 can be set, for example, in a range of 5×1018/cm3 to 1×1020/cm3. The thickness of the n-side contact layer 22 is preferably greater than the thickness of the undoped layer 21. Making the n-side contact layer 22 thicker than the undoped layer 21 can reduce the forward voltage increase. The thickness of the n-side contact layer 22 can be set, for example in a range of 1.5 μm to 4 μm. The n-side contact layer 22 has an upper face above which no semiconductor layer is disposed. An n-electrode 60 is disposed above a portion of the upper face of the n-side contact layer 22 above which no semiconductor layer is disposed.
An active layer 30 is disposed between an n-side semiconductor layer 20 and a p-side semiconductor layer 50. The active layer 30 emits ultraviolet light. The peak emission wavelength of the ultraviolet light emitted by the active layer 30 is in a range of, for example, 220 nm to 350 nm.
The active layer 30 includes, successively from the n-side semiconductor layer 20 side, a first barrier layer 31 containing Al and an n-type impurity, a first well layer 32 containing Al and emitting ultraviolet light, a second barrier layer 33 containing Al, and a second well layer 34 containing Al and emitting ultraviolet light. Here, the first barrier layer 31 and the second barrier layer 33 both contain Al. The highest n-type impurity concentration peak in the first barrier layer 31 is located closer to the p-side semiconductor layer 50. Moreover, the Al composition ratio of the first barrier layer 31 is higher than the Al composition ratio of the second barrier layer 33. This can increase the light emission efficiency in the first well layer 32. In other words, in this embodiment, the number of holes injected into the first well layer 32 can be increased by making the band gap of the second barrier layer 33 smaller than the band gap of the first barrier layer 31 by making the Al composition ratio of the first barrier layer 31 higher than the Al composition ratio of the second barrier layer 33. Because the band gap of the first barrier layer 31 is larger than the band gap of the second barrier layer 33, the hole trapping effect in the first well layer 32 can be increased. For example, the Al composition ratio of the first barrier layer 31 is 3% to 17% greater than the Al composition ratio of the second barrier layer 33. This can increase the light emission efficiency in the first well layer 32. In this embodiment, the hole trapping effect in the first well layer 32 is further improved by increasing the difference between the band gap of the first barrier layer 31 and the band gap of the first well layer 32 in the valence band by positioning the n-type impurity concentration peak in the first barrier layer 31 closer to the p-side semiconductor layer 50. This can further increase the light emission efficiency in the first well layer 32. There is a concern that doping the first barrier layer 31 with an n-type impurity could degrade the crystallinity of the first barrier layer 31. In this embodiment, however, the barrier at the border between the first well layer 32 and the first barrier layer 31 is made higher while reducing the n-type impurity concentration in the first barrier layer 31 closer to the n-side semiconductor layer 20 by positioning the highest n-type impurity concentration peak in the first barrier layer 31 closer to the p-side semiconductor layer 50. This can reduce the crystallinity deterioration of the first barrier layer 31 as a whole. Here, the highest n-type impurity concentration peak in the first barrier layer 31 positioned closer to the p-side semiconductor layer 50 is, for example, 1×1019 to 6×1019/cm3. Furthermore, the lowest n-type impurity concentration in the first barrier layer 31 is located closer to the n-side semiconductor layer 20 than the highest n-type impurity concentration peak in the first barrier layer 31 is. For example, the lowest n-type impurity concentration in the first barrier layer 31 is 1×1017 to 9×1017/cm3.
Specific examples and preferable examples of barrier layers and well layers in this embodiment will be described below.
For example, a first barrier layer 31 has a first layer 31a and a second layer 31b that is located closer to the p-side semiconductor layer 50 than the first layer 31a is as shown in
Here, the second layer 31b is preferably lesser in thickness than the first layer 31a. The second layer 31b contains the n-type impurity concentration higher than the average value of n-type impurity concentration in an entirety of the first barrier layer 31. Thus, reducing the thickness of the second layer 31b having a relatively high n-type impurity concentration can reduce the crystallinity deterioration of the first barrier layer 31 attributable to a high n-type impurity concentration layer having a large thickness, thereby improving the light emission efficiency. For example, the thickness of the second layer 31b is preferably 5% to 30% of the thickness of the entire first barrier layer 31. This can reduce the crystallinity deterioration of the first barrier layer 31 while improving the hole trapping effect in the first well layer 32.
Moreover, the second barrier layer 33 is preferably lesser in thickness than the second layer 31b. This can increase the supply of holes to the first well layer 32.
The second barrier layer 33 may be undoped, or contain an n-type impurity. Employing an undoped second barrier layer 33 can reduce the crystallinity deterioration of the active layer 30. Allowing the second barrier layer 33 to contain an n-type impurity can reduce the electrical resistance of the second barrier layer 33 to thereby reduce the forward voltage. When the second barrier layer 33 contains an n-type impurity, the n-type impurity concentration of the second barrier layer 33 is preferably lower than the n-type impurity concentration of the second layer 31b and higher than the n-type impurity concentration of the first layer 31a. This can reduce the forward voltage while reducing the crystallinity deterioration of the second barrier layer 33.
Furthermore, the Al composition ratio of the first layer 31a and the Al composition ratio of the second layer 31b are preferably practically the same. This can reduce the band gap difference attributable to the difference between the Al composition ratio of the first layer 31a and that of the second layer 31b, allowing electrons to be supplied to the first well layer 32 efficiently.
Moreover, the first barrier layer 31 is preferably in contact with the n-side semiconductor layer 20, and the Al composition ratio of the first barrier layer 31 substantially the same as the Al composition ratio of the n-side semiconductor layer 20. This can reduce the band gap difference attributable to the Al composition ratio difference between the n-side semiconductor layer 20 and the first barrier layer 31, thereby allowing electrons to be supplied to the first well layer 32 efficiently.
In the case in which the n-side semiconductor layer 20 includes an n-side contact layer 22, and the first barrier layer 31 is in contact with the n-side contact layer 22, the n-type impurity concentration of the n-side contact layer 22 is preferably lower than n-type impurity concentration of the second layer 31b and higher than the n-type impurity concentration of the first layer 31a. This can reduce the resistance of the n-side contact layer 22 while reducing the crystallinity deterioration of the n-side contact layer 22.
The second well layer 34 is preferably lesser in thickness than the first well layer 32. This can increase the supply of holes to the first well layer 32.
The Al composition ratio of the second well layer 34 may be higher than the Al composition ratio of the first well layer 32. As described later, the Al composition ratio of an electron blocking layer 40 is preferably higher than the Al composition ratio of a barrier layer in order to reduce electron overflow. However, in the case in which the Al composition ratio of the layer, that is in contact with the second well layer 34, among the electron blocking layer 40 is high, for example, the second well layer 34 can occasionally be strained to increase the wavelength of the light emitted by the second well layer 34. By making the Al composition ratio of the second well layer 34 higher than the Al composition ratio of the first well layer 32 thereby increasing the band gap of the second well layer 34, the increase in the wavelength of the light from the second well layer 34 can be lessened. The Al composition ratio of the second well layer 34 can be 2% to 10% greater than the Al composition ratio of the first well layer 32.
For the first well layer 32 and the second well layer 34, for example, a layer formed of AlGaN can be used. For the first barrier layer 31 and the second barrier layer 33, for example, a layer formed of AlGaN can be used. The Al composition ratio of the first well layer 32 and the second well layer 34 can be set, for example, to 10% or higher, specifically 10% to 50%, more specifically 30% to 50%. Assuming that the peak wavelength of the light from the first well layer 32 and the second well layer 34 is about 280 nm, an AlGaN layer having about 42% Al composition ratio can be used for the first well layer 32 and the second well layer 34. The Al composition ratio of the first barrier layer 31 and the second barrier layer 33 can be set, for example, to 10% or higher, specifically 10% to 70%, more specifically 30% to 70%.
The thickness of the first well layer 32 can be set, for example, in a range of 3 nm to 6 nm. The thickness of the second well layer 34 can be set, for example, in a range of 1 nm to 4 nm, preferably less than the thickness of the first well layer 32 as descried above. The thickness of the first layer 31a of the first barrier layer 31 is 10 nm to 60 nm, and the thickness of the second layer 31b is 5 nm to 20 nm, for example. The thickness of the second barrier layer 33 is, for example, 1 nm to 5 nm.
Specific examples and preferable examples of barrier layers and well layers have been described above. The thickness and the Al composition ratio of and the amount of an n-type impurity added to the first layer 31a and second layer 31b of the first barrier layer 31 and the second barrier layer 33 can be suitably adjusted based on the aimed specifications, such as the emission wavelength, light emission output, drive voltage, current, and the like, by taking into consideration the specific examples and preferable examples described above. Similarly, the thickness and the Al composition ratio of and the amount of an n-type impurity added to the first well layer 32 and the second well layer 34, or the like can also be preferably adjusted by taking into consideration the specific examples and preferable examples described above.
An electron blocking layer 40 is provided to reduce the overflow of electrons supplied from the n-side semiconductor layer 20. The electron blocking layer 40 can be a multilayer structure including multiple semiconductor layers containing Al. For example, the electron blocking layer 40 can be a multilayer structure having, successively from the active layer 30 side, an AlN layer 41, a first AlGaN layer 42, and a second AlGaN layer 43 as shown in
A p-side semiconductor layer 50 preferably has a high transmittance with respect to the light from the first well layer 32 and the second well layer 34. For example, the p-side semiconductor layer 50 preferably includes an AlGaN layer having a higher Al composition ratio than the Al composition ratios of the first well layer 32 and the second well layer 34. However, an AlGaN layer having a high Al composition ratio has a larger band gap than that of a GaN layer or the like. For this reason, employing an AlGaN layer having a high Al composition ratio as a p-side semiconductor layer 50 tends to result in inadequate conversion of the p-side semiconductor layer 50 into a p-type layer or an increased contact resistance between the p-electrode 70 and the p-side semiconductor layer 50. Thus, for a nitride semiconductor light emitting element using an AlGaN layer having a relatively high Al composition ratio as the first well layer 32 and the second well layer 34, it is necessary to achieve both high light extraction efficiency and low forward voltage. This embodiment makes it possible to achieve a nitride semiconductor light emitting element 1 with high light extraction efficiency and low forward voltage by employing the p-side semiconductor layer 50 described below.
For example, in this embodiment, the p-side semiconductor layer 50 includes, as shown in
Furthermore, the first p-side semiconductor layer 51 and the second p-side semiconductor layer 52 may be of a single layer or one including multiple layers. For example, the first p-side semiconductor layer 51 may include, successively from the active layer 30 side, a first layer formed of AlGaN, a second layer formed of AlGaN with a lower Al composition ratio than that of the first layer, and a third layer formed of AlGaN with a lower Al composition ratio than that of the second layer. In this case, the third layer may be a gradient composition layer in which the Al composition ratio gradually decreases. The second p-side semiconductor layer 52 may include, for example, from the first p-side semiconductor layer 51 side, a fourth layer formed of AlGaN and a fifth layer formed of GaN. Including first to fifth layers as described above can achieve a nitride semiconductor light emitting element 1 having higher light extraction efficiency and lower forward voltage.
An n-electrode 60 is disposed above the n-side contact layer 22 and electrically connected to the n-side semiconductor layer 20. A p-electrode 70 is disposed above the second p-side semiconductor layer 52 of the p-side semiconductor layer 50 and electrically connected to the p-side semiconductor layer 50.
For the n-electrode 60, for example, metals, such as Ag, Al, Ni, Au, Rh, Ti, Pt, Mo, Ta, W, and Ru, or alloys containing these metals as main components can be used. The n-electrode 60 can be a multilayer structure including, successively from the n-side contact layer 22 side, a Ti layer, an Al alloy layer, a Ta layer, and a Ru layer, for example.
For the p-electrode 70, for example, the same or similar metal to that for the n-electrode 60 described above can be used. In the case of allowing the p-electrode 70 to have the function to reflect the light from the active layer 30 that is advancing to the p-electrode 70 towards the n-side semiconductor layer 20, the metal layer among those in the p-electrode 70 that is disposed in contact with the third layer 53 is preferably formed of a metal having a high reflectance with respect to the light from the active layer 30. For example, the metal layer preferably has, for example, a reflectance of 70% or higher, more preferably 80% or higher, with respect to the light from the active layer 30. For such a metal layer, for example, a Rh layer or Ru layer is preferably used. The p-electrode 70 can be a multilayer structure that includes, for example, a Rh layer, an Au layer, a Ni layer, and a Ti layer, or a multilayer structure that includes a Ru layer, an Au layer, a Ni layer and a Ti layer.
When a forward voltage is applied across the n-electrode 60 and the p-electrode 70, a forward voltage applies across the p-side semiconductor layer 50 and the n-side semiconductor layer 20, supplying holes and electrons to the active layer 30 to thereby allow the active layer 30 to emit light.
With respect to this embodiment, as shown in
A method of manufacturing a nitride semiconductor light emitting element according to this embodiment will be explained below with reference to
A method of manufacturing a nitride semiconductor light emitting element according to this embodiment includes:
First, as shown in
The semiconductor layers described later can be epitaxially grown by MOCVD, for example.
Then as shown in
Then as shown in
Then as shown in
Here, in the step of forming a first barrier layer 31 (S2-1), after forming a first layer 31a containing Al and an n-type impurity above the n-side semiconductor layer by using the source gases described above, the flow rate of the monosilane (SiH4) gas is increased to form above the first layer 31a a second layer 31b containing Al and a higher concentration n-type impurity than that of the first layer 31a.
The first well layer 32 is formed by growing an AlGaN layer by using as the source gases a TMA gas, TEGa gas, and ammonia gas, and primarily nitrogen gas as the carrier gas, for example.
The second barrier layer 33 is formed by growing an AlGaN layer by using as the source gases a TMA gas, TEGa gas, and ammonia gas, and primarily nitrogen gas as the carrier gas, for example. In forming the second barrier layer 33, no n-type impurity gas is used, or the flow rate of the n-type impurity gas is set lower than the flow rate of the n-type impurity gas used in the step of forming a first barrier layer 31.
For example, the second well layer 34 is formed in the same or similar manner to the first well layer 32. The second well layer 34 is preferably formed to be lesser in thickness than the first well layer 32. Furthermore, in forming the second well layer 34, the flow rate of the TMA gas is set lower than that in the step of forming a first well layer 32 such that the Al composition ratio of the second well layer 34 is lower than the Al composition ratio of the first well layer 32.
Then as shown in
Then as shown in
Each layer of the p-side semiconductor layer 50 can be formed by setting the temperature in a range of 750° C. to 950° C., for example.
Subsequent to forming the p-side semiconductor layer 50, a portion of the p-side semiconductor layer 50, a portion of the electron blocking layer 40, and a portion of the active layer 30 are removed to expose a portion of the n-side contact layer 22.
Then as shown in
By following the steps described above, a nitride semiconductor light emitting element according to this embodiment can be manufactured.
A specific form of a nitride semiconductor light emitting element according to this embodiment will be described below.
A preferable positional relationship between the n-side semiconductor layer 20 and the p-side semiconductor layer 50 in the nitride semiconductor light emitting element 1 in the top view, and an example of a layout of the electrodes disposed above the n-side semiconductor layer 20 and the p-side semiconductor layer 50 in the positional relationship will be described below.
As shown in
By achieving the positional relationship between the n-side semiconductor layer 20 and the p-side semiconductor layer 50 in the top view shown in
The reason for this will be described below.
In a nitride semiconductor light emitting element having a quadrangular top view shape, because the active layer and the p-side semiconductor layer located above the active layer normally occupy a larger area, they are preferably disposed closely to the outline of the nitride semiconductor light emitting element. However, the present inventors found that, in a nitride semiconductor light emitting element which emits ultraviolet light, disposing the active layer and the p-side semiconductor layer close to the corners of the nitride semiconductor light emitting element can cause the heat generated during light emission to be concentrated in the corners to thereby reduce the reliability of the element.
The positional relationship between the n-side semiconductor layer 20 and the p-side semiconductor layer 50 in the top view shown in
In other words, the exposed portions of the n-side semiconductor layer 20 are arranged along all sides of the nitride semiconductor light emitting element such that the active layer 30 and the p-side semiconductor layer 50 are disposed inward of the exposed portions of the n-side semiconductor layer 20 in the top view. Not disposing the active layer and the p-side semiconductor layer near the four corners of the nitride semiconductor light emitting element can reduce the concentration of the heat generated during light emission at the corners, thereby improving the reliability of the light emitting element.
One example of an electrode structure in the case of the positional relationship between the n-side semiconductor layer 20 and the p-side semiconductor layer 50 shown in
The n-electrode 60 includes an n-side electrode 61 and an n-side pad electrode 62. The p-electrode 70 includes a first p-side electrode 71, a second p-side electrode 72 disposed above the first n-side electrode 71, and a p-side pad electrode 73 disposed above the second p-side electrode 72. The n-side electrode 61 is positioned to overlap the first exposed portion 201, the second exposed portions 202, and the third exposed portions 203 in the top view. The n-side electrode 61 is disposed above the n-side contact layer 22 of the n-side semiconductor layer 20 and electrically connected to the n-side semiconductor layer 20. The first p-side electrode 71 is positioned to overlap the base portion 501 and the extended portions 502 of the p-side semiconductor layer 50 in the top view. The first p-side electrode 71 is disposed above the second p-side semiconductor layer 52 of the p-side semiconductor layer 50 and electrically connected to the p-side semiconductor layer 50. The first p-side electrode 71 is disposed above the upper face of the second p-side semiconductor layer 52. The second p-side electrode 72 is disposed above the upper face of the first p-side electrode 71. The p-side pad electrode 73 is disposed above a portion of the upper face of the second p-side electrode 72. The p-side pad electrode 73 has, for example, a base portion disposed practically above the entire surface of the second p-side electrode 72 located above the base portion 501 of the p-side semiconductor layer 50, and extended portions extending from the base portion along the extended portions 502 of the p-side semiconductor layer 50 as shown in
As shown in
For the n-side electrode 61, for example, metals, such as silver (Ag), Al, nickel (Ni), gold (Au), rhodium (Rh), titanium (Ti), platinum (Pt), molybdenum (Mo), tantalum (Ta), tungsten (W), and ruthenium (Ru), or alloys containing these metals as main components can be used. The n-side electrode 61 can be, for example, a multilayer structure that includes multiple metal layers. The n-side electrode 61 can be a multilayer structure including, successively from the n-side semiconductor layer 20 side, a Ti layer, an Al alloy layer, a Ta layer, and a Ru layer, for example.
For the n-side pad electrode 62, for example, metals, such as Ni, Au, Ti, Pt, and W, or alloys containing these metals as main components can be used. The n-side pad electrode 62 can be a multilayer structure including, successively from the n-side electrode 61 side, a Ti layer, a Pt layer, and an Au layer. The thickness of the n-side pad electrode 62 can be set, for example, in a range of 500 nm to 1500 nm.
For the p-electrode 70, for example, the same or similar metals to those for the n-electrode 60 described above can be used. The p-electrode 70 preferably reflects the light advancing from the active layer 30 to the p-electrode 70 towards the n-side semiconductor layer 20 and thus, for example, a metal having a high reflectance with respect to the light from the active layer 30 is preferably used for at leas one of the first p-side electrode 71 and the second p-side electrode 72. A metal having a high reflectance refers to, for example, a metal having a reflectance of 60% or higher with respect to the light from the active layer 30. For example, Rh or Ru is preferably used for at least one of the first p-side electrode 71 and the second p-side electrode 72.
In the case of using a layer containing Rh or Ru for the first p-side electrode 71, the first p-side electrode 71 preferably further includes an Au layer. This can enhance the adhesion between the first p-side electrode 71 and the p-side semiconductor layer 50 while maintaining a high reflectance as compared to a layer formed only of an Rh or Ru layer. The first p-side electrode 71 can be a multilayer structure including, successively from the p-side semiconductor layer 50 side, an Rh layer, an Au layer, and an Ni layer, or a multilayer structure including an Ru layer, an Au layer, and an Ni layer. Furthermore, the first p-side electrode 71 can be a layer that includes an alloy layer that contains Rh or Ru and contains Au and/or Ni.
For the p-side pad electrode 73, for example, the same or similar metals to those for the n-side pad electrode 62 described above can be used. The p-side pad electrode 73 can be a multilayer structure including, successively from the p-side semiconductor layer 50 side, a Ti layer, a Pt layer, and an Au layer, for example. The thickness of the p-side pad electrode 73 can be set, for example, in a range of 500 nm to 1500 nm.
A nitride semiconductor light emitting element in an Example will be explained below.
As the substrate 10, a sapphire substrate having C-plane as a principal plane was used. An underlayer 11 formed of AlN was formed above the substrate 10 to a thickness of about 2.1 μm.
The temperature was then set at 1175° C., and an Al0.60Ga0.40N layer was formed above the underlayer 11 to a thickness of about 21 nm by using TMA gas, TMG gas, and ammonia gas as source gases. This was followed by forming an AlN layer at 1175° C. to a thickness of about 10 nm by using TMA gas and ammonia gas as source gases. A superlattice layer 12 was formed by stacking 30 pairs of such AlGaN and AlN layers.
Then at 1175° C., an undoped layer 21 was formed above the superlattice layer 12 by growing Al0.60Ga0.40N to a thickness of about 0.5 μm by using TMA gas, TMG gas, and ammonia gas as source gases. This was followed by forming an n-side contact layer 22 at 1175° C. by growing Al0.60Ga0.40N containing an n-type impurity to a thickness of about 2.2 μm by using TMA gas, TMG gas, ammonia gas, and SiH4 gas as source gases. An n-side semiconductor layer 20 including such an undoped layer 21 and an n-side contact layer 22 was formed. The n-type impurity concentration of the n-side contact layer 22 was about 9.5×1018/cm3.
Subsequently, the temperature was set at 950° C. and a first layer 31a was formed above the n-side semiconductor layer 20 by growing Al0.60Ga0.40N containing an n-type impurity to a thickness of about 40 nm by using TMA gas, TMG gas, ammonia gas, and SiH4 gas as source gases. This was followed by forming a second layer 31b at 950° C. by growing Al0.60Ga0.40N to a thickness of about 10 nm by using TMA gas, TMG gas, ammonia gas, and SiH4 gas as source gases. Here, the flow rates of the source gases for forming the first layer 31a were set to: TMA gas 16 sccm, TEGa gas 45 sccm, ammonia gas 10 slm, and SiH4 gas 0.5 sccm. The flow rates of the source gases for forming the second layer 31b were set to: TMA gas 16 sccm, TEGa gas 45 sccm, ammonia gas 10 slm, and SiH4 gas 16 sccm.
In the manner described above, a first barrier layer 31 which included a first layer 31a containing an n-type impurity and a second layer 31b containing more n-type impurity than that in the first layer 31a was formed.
Furthermore, the thicknesses of the first layer 31a and the second layer 31b here are the thicknesses in the manufacturing process, and do not necessarily match the thickness of the first layer 31a having a lower n-type impurity concentration than the average value of that of the entire first barrier layer 31 and the thickness of the second layer 31b having a higher n-type impurity concentration than the average value of that of the entire first barrier layer 31 identified after manufacturing the product.
Then a first well layer 32 was formed at 950° C. by growing Al0.43Ga0.57N to a thickness of about 4.4 nm by using TMA gas, TEGa gas, and ammonia gas as source gases.
Subsequently, a second barrier layer 33 was formed by setting the temperature at 950° C. and growing Al0.53Ga0.47N to a thickness of about 2.5 nm by using TMA gas, TEGa gas, and ammonia gas as source gases. This was followed by forming a second well layer 34 by growing Al0.47Ga0.53N to a thickness of about 2.2 nm at 950° C. by using TMA gas, TEGa gas, and ammonia gas as source gases. In this manner, an active layer 30 which included two well layers and two barrier layers was formed.
Subsequently, the temperature was set at 870° C., and an AlN layer 41 was formed above the active layer 30 to a thickness of about 1.3 nm by using TMA gas and ammonia gas as source gases. This was followed by forming a first AlGaN layer 42 at 870° C. by growing Al0.55Ga0.45N to a thickness of about 1.2 nm by using TMA gas, TEGa gas, and ammonia gas as source gases. This was followed by forming a second AlGaN layer 43 at 870° C. by growing Al0.78Ga0.22N to a thickness of about 4 nm by using TMA gas, TEGa gas, and ammonia gas as source gases. In this manner, an electron blocking layer 40 which included an AlN layer and two AlGaN layers was formed.
Then the temperature was set at 870° C., and an Al0.603Ga0.37N layer containing a p-type impurity was formed above the electron blocking layer 40 to a thickness of about 75 nm by using TMA gas, TEGa gas, ammonia gas, and Cp2Mg gas as source gases. This was followed by forming an Al0.53Ga0.47N layer containing a p-type impurity at 870° C. to a thickness of about 27 nm by using TMA gas, TMG gas, ammonia gas, and Cp2Mg gas as source gases. Then a gradient composition layer containing a p-type impurity was formed at 870° C. to a thickness of about 3 nm by using TMA gas, TEGa gas, ammonia gas, and Cp2Mg gas as source gases while gradually reducing the TMA gas such that the Al composition ratio gradually decreased from Al0.53Ga0.47N to ultimately 0. In the manner described above, a first p-side semiconductor layer 51 was formed.
This was followed by forming an Al0.40Ga0.60N layer containing a p-type impurity at 900° C. to a thickness of about 10 nm by using TMA gas, TMG gas, ammonia gas, and Cp2Mg gas as source gases. Then a GaN layer containing a p-type impurity was formed at 900° C. to a thickness of about 10 nm by using TMA gas, TMG gas, and ammonia gas as source gases. In the manner described above, a second p-side semiconductor layer 52 that included an Al0.40Ga0.60N layer containing a p-type impurity and a GaN layer containing a p-type impurity was formed.
Subsequent to forming each semiconductor layer, a heat treatment was conducted in a nitrogen atmosphere in the reaction chamber at a temperature of about 475° C.
Subsequent to the heat treatment, a portion of the p-side semiconductor layer 50 and a portion of the active layer 30 were removed to expose a portion of the n-side contact layer 22.
Then an n-electrode 60 was formed above the n-side contact layer 22, and a p-electrode 70 was formed above the p-side semiconductor layer 50. For the n-electrode 60, a multilayer structured electrode in which a Ti layer, AlSi layer, a Ta layer, a Ru layer, and a Ti layer were stacked successively from the n-side contact layer 22 side was used. For the p-electrode 70, a multilayer structured electrode in which a Ti layer, a Ru layer, and a Ti layer were stacked successively from the third layer 53 side was used.
The forward voltage of the nitride semiconductor light emitting element prepared as described above was 5.16 V, and the light emission output Po was 172 mW. The forward voltage and the light emission output Po shown here are the values achieved when a 350 mA current was applied.
The position of the highest n-type impurity concentration peak in the first barrier layer 31 was in the second layer 31b. The highest peak value of the n-type impurity concentration in the first barrier layer 31 was about 3×1019/cm3.
The nitride semiconductor light emitting element according to the embodiments of the present disclosure includes the following.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-105120 | Jun 2023 | JP | national |
| 2023-144515 | Sep 2023 | JP | national |
