“Non-uniform Bipolar conduction in Single Finger NMOS Transistors and Implications for Deep Submicron ESD Design”, IRPS—International Reliability Physics Symposium Proceedings for the Year 2000, Kwang-Hoon Oh, Charvaka Duvvury, Craig Salling, Kaustav Banerjee and Robert W. Dutton, Published in 2000, 9 pgs. |
“Process-related Effects on ESD Performance in Deep Submicron Technologies”, Ajith Amerasekera and Vikas Gupta, Published date not available, 10 pgs. |
“Development of Substrate-Pumped nMOS Protection for a 0.13μm Technology”, Craig Salling, Jerry Hu, Jeff Wu, Charvaka Duvvury, Roger Cline and Rith Pok, Published date not available, 13 pgs. |
“ESD-related Process Effects in Mixed-voltage Sub-0.5μm Technologies”, Vikas Gupta, Ajith Amerasekera, Sridhar Ramaswamy and Alwin Tsao. Published date not available, 9 pgs. |
Substrate Triggering and Salicide Effects on ESD Performance and Protection Circuit Design in Deep Submicron CMOS Processes , IEEE Electron Device Meeting Technical Digest, Ajith Amerasekera, Charvaka Duvvury, Vijay Reddy and Mark Rodder, 1995, pp. 547-550. |
“A Novel NMOS Transistor for High Performance ESD Protection Devices in 0.18 μm CMOS Technology Utilizing Salicide Process”, EOS/ESD Symposium 00, Chang-Su Kim, Hong-Bae Park, Young-Gwan Kim, Dae-Gwan, Kang, Myoung-Goo Lee, Si-Woo Lee, Chan-Hee Jeon, Han-Gu Kim, Young-Jae Yoo and Han-Sub Yoon, pp. 407-412. |