NOISE IMMUNE OVER CURRENT PROTECTION WITH INHERENT CURRENT LIMITING FOR SWITCHING POWER CONVERTER

Abstract

A circuit for providing over-current protection, the circuit including a gate driver circuit for controlling a bridge circuit including a half bridge stage having high and low switches. The circuit includes a feedback loop circuit for counting over-current indicators sensed during one or more consecutive PWM cycles; wherein when an over-current indicator is sensed, the low switch is turned OFF for duration of a first time period after which the low switch is turned back ON, to enable determination of an over-current condition where false noise signals are rejected thereby preventing circuit shutdowns due to false over-current condition.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional half bridge circuit with a current sense and a blanking filter circuit over-current scheme;

FIG. 2 is a timing diagram of the conventional over-current scheme of FIG. 1;

FIG. 3 is a block diagram of a half bridge circuit with a current sense and a blanking filter circuit over-current scheme of the present invention; and

FIG. 4 is a timing diagram of the over-current scheme of FIG. 3.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

The present invention proposes an event based feedback loop for the circuit 20 illustrated in FIG. 3. The circuit 20 includes a gate driver circuit or control IC 22 for controlling a bridge stage 14, e.g., a half bridge stage having switches Q1 and Q2 connected at a node N. An inductor L1 is connected between the node N and a node M, which connects series connected capacitors C1 and C2. The switch Q2 is connected between the node N and a resistor R_sense.

As illustrated in FIG. 4, the event based feedback loop turns OFF the switch Q2 for a short fixed time period (Toff) when a comparator circuit 18 fires. The turning OFF of the switch Q2 enables determination of the over-current condition. A pulse generator circuit 28, when enabled generates a signal which is processed together with the PWM signal in an AND circuit 30 before being a controlling signal V_g is sent to a gate of the switch Q2.

The comparator circuit 18 fires when it determines that a user preset threshold V_TH is exceeded by a signal A sensed at the resistor R_sense. When, this happens, a signal B is sent to a counter circuit 24, a clear latch 26, and the pulse generator circuit 28. Turning OFF of the switch Q2 provides better protection by effectively holding the inductor current I constant prior to an actual shut down of the circuit 20 due to the over-current condition. The switch Q2 is then turned back ON for another over-current measurement.

To avoid shutting down of the circuit 20 due to false noise signals and prevent unwanted circuit shutdowns due to misfiring of the comparator circuit 18, the comparator circuit 18 firing events are counted by an event counter circuit 24. The firing events are counted until the number of firing events exceeds a pre-determined number N. Only then, when the number of firing events exceeds the pre-determined number N, does the circuit 20 register occurrence of the over-current condition and enters a shut down mode.

As illustrated in FIG. 4, The counter/latch circuit 26/24 scheme allows the counting of the firing events to be extended over consecutive PWM cycles. Specifically, the watchdog latch circuit 26 is used to reset the event counter maintained by the counter circuit 24 when no firings of comparator circuit 18, i.e., signal B is OFF, occur for some set time i.e., during one PWM ON period.

During a real over-current event, the switch Q2 is repeatedly turned OFF and ON until the event counter of the counter circuit 24 reaches a pre-determined number N. For example, FIG. 4 illustrates the circuit 20 entering a shut down state when the event counter is 4. This, effectively keeps a current I of an inductor L1 constant and is much safer than when a filtering time period is used as in circuit 10 (FIG. 1), where the current I through the inductor L1 keeps increasing during the filtering time period.

In the circuit 20, single or multiple noise spikes, small or large, will be rejected since they are unlikely to cause the counter to reach the pre-determined number N before the counter circuit 24 is reset during a quiet period.

The filtering time period for circuit 22 may be much reduced since individual noise spikes can now be tolerated. Moreover, counting of the spikes can be spread over consecutive PWM ON periods, allowing application of the over-current condition detection of the present invention in high frequency or short duty situations where PWM ON time is minimal.

The over-current condition detection scheme of the present invention counts over-current events over consecutive PWM cycles only up to the pre-determined number N cycles. Therefore, the system does not stay in constant current mode for a longer time.

The over-current condition detection scheme of the present invention is flexible and can be tailored to fit a variety of systems by adjusting

The filtering time period of a blanking filter circuit 16 to be greater than or equal to 0;

The number of over-current events to be counted, i.e., the pre-determined number N,

A watch dog time period (default=one PWM ON period), and

A switch turn OFF time (Toff).

Although the present invention has been described in relation to particular embodiments thereof, many other variations and modifications and other uses will become apparent to those skilled in the art. It is preferred, therefore, that the present invention not be limited by the specific disclosure herein.

Claims

1. A circuit for providing over-current protection, the circuit including a gate driver circuit for controlling a bridge circuit including a half bridge stage having high and low switches, the circuit comprising: a feedback loop circuit for counting over-current indicators sensed during one or more consecutive PWM cycles;wherein when an over-current indicator is sensed, the low switch is turned OFF for duration of a first time period after which the low switch is turned back ON, to enable determination of an over-current condition whereby false noise signals are rejected thereby preventing circuit shutdowns due to false over-current condition.

2. The circuit of claim 1, wherein the bridge circuit further comprises: high and low capacitors parallel connected to the bridge stage;an inductor connected at a first node between the high and low switches and a second node between the high and low capacitors; anda resistor series connected to the low switch for sensing a first current from the inductor through the low switch.

3. The circuit of claim 2, wherein the feedback loop comprises a comparator circuit for generating a comparison signal when the first current exceeds a user provided preset threshold, wherein when the comparison signal is generated the low switch is turned OFF.

4. The circuit of claim 3, wherein the feedback loop further comprises: a counter circuit for counting a number of occurrences of the comparison signal; anda latch circuit for resetting the counter circuit when the comparison signal does not occur for a second time period;wherein the number of occurrences of the comparison signal in excess of the pre-determined number indicates the over-current condition.

5. The circuit of claim 4, wherein the second time period is one PWM ON period.

6. The circuit of claim 4, wherein the over-current condition prompts the circuit to enter a shut down mode.

7. The circuit of claim 3, wherein the feedback loop further comprises: a pulse generator circuit for providing a disabling signal when enabled; andan AND circuit connected to a gate of the low switch for processing the disabling signal and a PWM signal to control the low switch,wherein the pulse generator circuit is enabled when the comparison signal is generated.

8. The circuit of claim 3, further comprising a blanking filter circuit for receiving the comparison signal, the blanking filter having a third time period for registering the comparison signal, wherein the blanking filter circuit provides the comparison signal to the pulse generator, counter, and latch circuits.

9. The circuit of claim 8, wherein the third time period is greater than or equal to 0.

10. The circuit of claim 1, wherein the PWM signal has a high frequency or short duty cycle and minimal PWM ON time.

11. The circuit of claim 1, wherein noise is distinguished over over-current events by counting over-current events over one or more PWM periods.