Claims
- 1. A method of allocating a single-color frame period to an n-bit intensity word, said n-bit intensity word comprised of an object bit, at least one less significant bit and at least one more significant bit, said method comprising the steps of:
- setting a portion of said single-color frame period to a bit period corresponding to said object bit at least equal to a minimum load time; and
- allocating a bit period corresponding to each of said at least one less significant bits and each of said at least one more significant bits, said bit periods corresponding to said less significant and said more significant bits having a binary relationship to said bit period of said object bit, said bit period corresponding to at least one bit of said intensity word other than the object bit being reduced from said binary relationship with said object bit such that a sum of said bit periods corresponding to said object bit and said less significant bits and said more significant bits and any blanking periods is no greater than said single-color frame period.
- 2. The method of claim 1, said allocating step resulting in a Weber's fraction of no more than 11% for all bit transitions for intensity word values above a value corresponding to said object bit.
- 3. The method of claim 1, said allocating step resulting in a Weber's fraction of no more than 6% for all bit transitions for intensity word values above a value corresponding to said object bit.
- 4. The method of claim 1, said allocating step resulting in a Weber's fraction of no more than 2% for all bit transitions above intensity word values above a value corresponding to said object bit.
- 5. The method of claim 1, said allocating step resulting in minimizing Weber's fraction for all bit transitions above intensity word values above a value corresponding to said object bit.
- 6. The method of claim 1, said allocating step comprising:
- decreasing said bit period corresponding to at least one of said more significant bits.
- 7. The method of claim 1, said allocating step comprising:
- decreasing all said bit periods corresponding to said more significant bits.
- 8. A display system comprising:
- a display device having a minimum data load time;
- a timing and control circuit for receiving image data words comprised of data bits including an object bit, and for providing said data bits to said display device for display during bit periods having a length, wherein said object bit has a bit period at least equal to said minimum data load time, said length of bit periods for said data bits of significance less than said object bit and of bit periods for said data bits of significance greater than said object bit having a binary relationship to said object bit, at least one bit period for said data bits of significance greater than or less than said object bit shortened from said binary relationship.
- 9. The display system of claim 8, said timing and control circuit providing said data bits for periods resulting in a Weber's fraction of no more than 11% for any bit transition of said image data words greater than a value of said object bit.
- 10. The display system of claim 8, said timing and control circuit providing said data bits for periods resulting in a Weber's fraction of no more than 6% for any bit transition of said image data words greater than a value of said object bit.
- 11. The display system of claim 8, said timing and control circuit providing said data bits for periods resulting in a Weber's fraction of no more than 2% for any bit transition of said image data words greater than a value of said object bit.
- 12. The display system of claim 8, said timing and control circuit providing said data bits for periods minimizig a Weber's fraction for any bit transition of said image data words greater than a value of said object bit.
- 13. The display system of claim 8, said timing and control circuit providing at least one said data bit of significance greater than said object bit for a period shortened from said binary relationship.
- 14. The display system of claim 8, said timing and control circuit providing all said data bits of significance greater than said object bit for a period shortened from said binary relationship.
Parent Case Info
This application claims priority under 35 U.S.C. .sctn. 119 (c) (1) of provisional application number 60/057,553 filed Aug. 29,1997.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
5510824 |
Nelson |
Apr 1996 |
|
5619228 |
Doherty |
Apr 1997 |
|
Foreign Referenced Citations (2)
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0 689 345 A2 |
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EPX |
0 686 954 A1 |
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