Non-linearity compensation circuit and bandgap reference circuit using the same

Abstract

A non-linearity compensation circuit and a bandgap reference circuit using the same for compensating non-linear effects of a reference voltage are provided. In the non-linearity compensation circuit, the reference voltage is transformed into a temperature independent current. A current mirror mirrors the temperature independent current for biasing a bipolar junction transistor (BJT). Further, two resistors are used for estimating a non-linear voltage, so as to compensate the reference voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a conventional bandgap reference circuit.

FIG. 2 is a concept diagram of compensation of the conventional bandgap reference circuit.

FIG. 3 is the reference voltage-temperature characteristic diagram of the conventional bandgap reference circuit.

FIG. 4 is the reference voltage-temperature characteristic diagram of the conventional bandgap reference circuit under different voltage sources.

FIG. 5 is a circuit diagram of a bandgap reference circuit according to a first embodiment of the present invention.

FIG. 6 is the concept diagram of compensation of the bandgap reference circuit according to the first embodiment of the present invention.

FIGS. 7A and 7B are reference voltage-temperature characteristic diagrams of the first embodiment and the conventional art under the same voltage source respectively.

FIG. 8 is a reference voltage-temperature characteristic diagram of the bandgap reference circuit according to the first embodiment of the present invention under different voltage sources.

FIG. 9 is a circuit diagram of a bandgap reference circuit according to a second embodiment of the present invention.

FIGS. 10A and 10B are the reference voltage-temperature characteristic diagrams of the bandgap reference circuit according to the second embodiment of the present invention.

DESCRIPTION OF EMBODIMENTS

FIG. 5 is a circuit diagram of a bandgap reference circuit according to a first embodiment of the present invention. The bandgap reference circuit 500 of this embodiment at least comprises a PTAT current mirror 505 formed by MOS transistors M501˜M503, operation amplifiers OP501˜503, BJT transistors B501 and B502, resistors R504, R505A, R505B and R506, and a non-linearity compensation circuit 510. The non-linearity compensation circuit 510 at least includes a temperature independent current mirror 515 formed by MOS transistors M504 and M505, an operation amplifier OP504, an MOS transistor M506, a BJT transistor B503, and resistors R501, R502, and R503.

The source of the MOS transistor M501 is connected to a power source VDD, the drain thereof is connected to the emitter of the BJT transistor B501 (i.e., node Va5), and the gate thereof is connected to the output of the operation amplifier OP501 and the gates of the MOS transistors M502 and M503. The source of the MOS transistor M502 is connected to the power source VDD, the drain thereof is connected to the emitter of the BJT transistor B502 (i.e., node Vb5), and the gate thereof is connected to the output of the operation amplifier OP501 and the gates of the MOS transistors M501 and M503. The source of the MOS transistor M503 is connected to the power source VDD, the drain thereof is connected to the positive input terminal of the operation amplifier OP502 and one terminal of the resistor R504, and the gate thereof is connected to the output of the operation amplifier OP501 and the gates of the MOS transistors M501 and M502. The output of the operation amplifier OP501 is coupled to the gates of the MOS transistors M501˜M503. As the MOS transistors M501˜M503 have the same size, they generate the same current.

The positive input terminal of the operation amplifier OP501 is connected to the node Vb5, the negative input terminal thereof is connected to the node Va5, and the output terminal thereof is connected to the gates of the MOS transistors M501˜M503. The positive input terminal of the operation amplifier OP502 is connected to the drain of the MOS transistor M503 and the resistor R504, the negative input terminal thereof is coupled to the output terminal thereof, and the output terminal thereof is coupled to the reference voltage VBG5 via the resistor R505A. The positive input terminal of the operation amplifier OP502 is connected to the node Va5, the negative input terminal thereof is coupled to the output terminal thereof, and the output terminal thereof is coupled to the reference voltage VBG5 via the resistor R505B. Therefore, the voltage VNTC5 is equal to the VBE5A of the transistor B501. As known from FIG. 5, the positive input voltage of the operation amplifier OP502 is V_PTC5+V_NL5, wherein V_PTC5 represents a voltage proportional to absolute temperature, and V_NL5 represents the non-linear dependent voltage.

The emitter of the BJT transistor B501 is connected to the node Va5, and the collector and the base thereof are both grounded. The emitter of the BJT transistor B502 is connected to the node Vb5 via the resistor R506, and the collector and the base thereof are both grounded.

The resistor R504 is coupled between the drain of the MOS transistor M503 and the ground terminal. The resistors R505A and R505B function as a voltage divider circuit to divide V_BG5 from the output voltages of the operation amplifiers OP502 and OP503. The resistors R505A and R505B have the same resistance. The resistor R506 is coupled between the node Vb5 and the emitter of the BJT transistor B502.

The source of the MOS transistor M504 is coupled to the power source VDD, the gate thereof is coupled to its drain and the gate of the MOS transistor M505, and the drain thereof is coupled to the drain of the MOS transistor M506. The source of the MOS transistor M505 is coupled to the power source VDD, the gate thereof is coupled to the gate and the drain of the MOS transistor M504, and the drain thereof is coupled to the emitter of the BJT transistor B503.

The source of the MOS transistor M506 is coupled to the negative input terminal of the operation amplifier OP504 and the resistor R503, the gate thereof is coupled to the output terminal of the operation amplifier OP504, and the drain thereof is coupled to the drain and the gate of the MOS transistor M504.

The positive input terminal of the operation amplifier OP504 is coupled to the reference voltage V_BG5, the negative input terminal thereof is coupled to the source of the MOS transistor M506 and the resistor R503, and the output terminal thereof is coupled to the gate of the MOS transistor M506.

The emitter of the BJT transistor B503 is coupled to the drain of the MOS transistor M505 and the resistors R501 and R502, and the base and the collector thereof are both grounded.

The resistor R501 is coupled between the emitter of the BJT transistor B501 and the emitter of the BJT transistor B503. A current I_NL5 flows through the resistor R501, and the voltage drop across the resistor is V_NL5. The resistor R502 is coupled between the node Vb5 and the emitter of the BJT transistor B503. The current I_NL5 also flows through the resistor R502, and the voltage drop across the resistor R502 is also V_NL5. The resistors R501 and R502 are coupled to each other and have the same resistance. The resistor R503 is coupled between the source of the MOS transistor M506 and the ground terminal.

The output voltage of the operation amplifier OP501 adjusts the MOS transistors M501 and M503, such that Va5=Vb5, which further causes a voltage drop ΔV_BE5 across the resistor R506. The voltage drop ΔV_BE5 across the resistor R506 is represented by the following equation:

ΔV_BE5=V_T*ln(n)   (8)

wherein n is the size ratio of the BJT transistor B502 to the BJT transistor B501 (n:1).

To facilitate the explanation, the current generated by the MOS transistors M501˜M503 is defined as I_PTAT5+I_NL5 hereinafter, wherein I_PTAT5 represents the current proportional to absolute temperature, and I_NL5 represents the non-linear dependent current.

As the output voltage of the MOS transistor M503 is I_PTAT5+I_NL5, a voltage drop across occurs on the resistor R504 is R⁵⁰⁴*(I_PTAT5+I_NL5)=V_PTC5+V_N5, wherein V_PTC5 represents the voltage proportional to absolute temperature, and V_NL5 represents the non-linear dependent voltage. Therefore, the positive input voltage of the operation amplifier OP502 is V_PTC5+V_NL5.

Moreover, as the positive input terminal voltage V_NTC5 of the operation amplifier OP503 is equal to V_BE5A, the following equation can be obtained through the operation of the operation amplifiers OP502 and OP503:

V _BG5=0.5*(V_PTC5+V_NTC5+V_NL5)   (9)

As the transistors B501 and B502 are biased by the PTAT current, α=1. Therefore, V_BE5A and V_BE5B can be represented by the following equation:

V _BE5A =V _BE5B =V _G0−(V_G0−V_BE0)*T/T₀−(η−1)*V_Tln(T/T₀)   (10)

V_BE5A and V_BE5B are negative temperature coefficient dependent voltages. The non-linear voltage V_NL5 still exists in equation 9, so a non-linearity compensation circuit 510 is used to estimate and compensate the non-linear V_NL5 in this embodiment.

As shown in FIG. 5, the reference voltage V_BG5 is fed back to the positive input terminal of the operation amplifier OP504 in the non-linearity compensation circuit 510. The operation amplifier OP504 and the MOS transistor M506 can be considered as a voltage-to-current converting unit for converting the reference voltage V_BG5 into a current I_BG5. The current I_BG5 may be regarded as a temperature independent current. The current mirror 515, which is a temperature independent current generator, mirrors the temperature independent current I_BG5 to the MOS transistor M505 and the BJT transistor B503. As the biasing current of the BJT transistor B503 is a temperature independent current, a can be considered as 0. Therefore,

V _BE5C =V _G0−(V_G0−V_BE0)*T/T₀−(η)*V_Tln(T/T₀)   (11)

Subtract equation (11) from equation (10), and the following equation can be obtained:

$\begin{array}{cc}{V}_{\mathrm{BE}5A}-V_{\mathrm{BE}5C}=V_T\ln \frac{T}{T_0}& \left(12\right)\end{array}$

As known from equation (7), the non-linear term of the reference voltage is V_Tln(T/T₀)=V_NL5. To estimate the value of the non-linear voltage, in this embodiment, let the resistor R501 across between the emitter of the BJT transistor B501 and the emitter of the BJT transistor B503. Therefore, the voltage drop across the resistor R501 (and the resistor R502) is the non-linear voltage V_NL5.

Therefore, the following equation is obtained by rearranging the equations described above,

$\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{BG}5}=\frac{1}{2}\left(V_{\mathrm{NTC}5}+V_{\mathrm{PTC}5}+V_{\mathrm{NL}5}\right)\\ =\frac{1}{2}\times \left[V_{\mathrm{BE}5A}+R504·\left(\frac{\Delta V_{\mathrm{BE}5}}{R506}+\frac{V_{\mathrm{NL}}}{R502}\right)\right]\\ =\frac{1}{2}\times \{\left[V_{\mathrm{BG}5}-\left(V_{\mathrm{BG}5}-V_{\mathrm{BE}0}\right)\frac{T}{T_0}-\left(\eta -1\right)V_T\ln \frac{T}{T_0}\right]+\\ \left[\frac{R504}{R506}·V_T·\ln \left(n\right)\right]+\left[\frac{R504}{R502}V_T\ln \frac{T}{T_0}\right]\}\end{array}& \left(13\right)\end{array}$

The definition of η and V_BE0 are as described above. By selecting appropriate resistance of R504 and R502, the (η−1) is made to be equal to or very close to the ratio of (R504/R502), thus the equation (13) can be simplified into the following equation.

$\begin{array}{cc}{V}_{\mathrm{BG}5}=\frac{1}{2}\times \left\{\left[V_{\mathrm{BG}5}-\left(V_{\mathrm{BG}5}-V_{\mathrm{BE}0}\right)\frac{T}{T_0}\right]+\left[\frac{R504}{R506}·V_T·\ln \left(n\right)\right]\right\}& \left(14\right)\end{array}$

As known from equation 14, after being compensated by the non-linearity compensation circuit 510, the non-linear effect of the reference voltage V_BG5 is well compensated, and can be considered as almost temperature independent.

The non-linearity compensation circuit 510 generates the temperature independent current I_BG5 by using the fed back reference voltage V_BG5 that can be considered as temperature independent. In addition, the two resistors R501 and R502 in the non-linearity compensation circuit 510 are across the transistors B501/B502 (α=1, biased by the current proportional to absolute temperature) and the temperature independent transistor B503(α=0, biased by the temperature independent current), so as to estimate the non-linear voltage V_NL5.

FIG. 6 is the concept diagram of the compensation of the bandgap reference circuit according to the first embodiment of the present invention. As shown in FIG. 6, the generated reference voltage V_BG of the first embodiment is the sum of K3*V_T (proportional to absolute temperature), V_BE (the negative temperature coefficient), and V_NL (the non-linear compensation term), wherein K3 is a constant equal to R504/R506*ln(n). As known from FIG. 6, the non-linear effect originally included in the V_BE is well compensated by V_NL in the first embodiment. Therefore, in the range of operating temperature, the curve (non-ideal) phenomenon in the characteristic diagram of the reference voltage is alleviated in comparison to FIG. 2.

FIGS. 7A and 7B are reference voltage-temperature characteristic diagrams of the first embodiment and the conventional art under the same voltage source (VDD=1.2 V) respectively. Under this condition, the variation range of the reference voltage according to the conventional art is 6.28 mV, and under this condition, the variation range of the reference voltage according to the first embodiment is only 0.711 mV. It is apparent that the variation range of the reference voltage according to the first embodiment is greatly reduced.

FIG. 8 is a characteristic diagram of the measured reference voltage V_GB-temperature according to the first embodiment under different power source VDD (1.0V˜1.5V) when the operating temperature is between −40° C. and 125° C., wherein curves A5˜E5 represent the variation curves of V_GB when VDD=1.5V, VDD=1.4V, VDD=1.3V, VDD=1.2V, and VDD=1.1V respectively.

FIG. 9 is a circuit diagram of a bandgap reference circuit 500′ according to a second embodiment of the present invention. The architecture of the bandgap reference circuits 500′ is similar to that of the bandgap reference circuit 500 shown in FIG. 5, so the same or like reference symbols represent the same or like elements, only except that the operation amplifiers OP502, OP503 and the resistor R504 in FIG. 5 are replaced by the BJT transistor B504′ and the resistor R504′ in FIG. 9.

With the concept of FIG. 5, it can be known that the reference voltage V_BG5′ generated by the architecture of FIG. 9 can be represented by the following equation:

$\begin{array}{cc}\begin{array}{c}{V}_{\mathrm{BG}5^{\prime }}=V_{\mathrm{NTC}}^{\prime }+V_{\mathrm{PTC}}^{\prime }+{\mathrm{VNL}}^{\prime }\\ =\left[V_{\mathrm{BE}5D}+R{504}^{\prime }·\left(\frac{\Delta V_{\mathrm{BE}5^{\prime }}}{R{506}^{\prime }}+\frac{V_{\mathrm{NL}5^{\prime }}}{R{502}^{\prime }}\right)\right]\\ =\{\left[V_{\mathrm{BG}}5^{\prime }-\left(V_{\mathrm{BG}}5^{\prime }-V_{\mathrm{BE}0}\right)\frac{T}{T_0}-\left(\eta -1\right)V_T\ln \frac{T}{T_0}\right]+\\ \left[\frac{R{504}^{\prime }}{R{506}^{\prime }}·V_T·\ln \left(n\right)\right]+\left[\frac{R{504}^{\prime }}{R{502}^{\prime }}V_T\ln \frac{T}{T_0}\right]\}\end{array}& \left(15\right)\end{array}$

In FIG. 9, the elements the same as or similar to the elements in FIG. 5 are represented with similar symbols. As the operation of the bandgap reference circuit 500′ of FIG. 9 can be deduced from the above description for the bandgap reference circuit 500, it will not be described here again.

FIGS. 10A and 10B are the reference voltage-temperature characteristic diagrams of the bandgap reference circuit according to the second embodiment. FIG. 10B is an enlarged partial view of FIG. 10A. It can be known from FIG. 10B that the variation range of the reference voltage is reduced to only 1.46 mV in the second embodiment.

As known from the architectures shown in FIGS. 5 and 9, the non-linearity compensation circuit according to the present invention is applicable in most bandgap reference circuits.

To sum up, the non-linearity compensation circuit according to the present invention can improve the precision of the reference voltage. In addition, the circuit cost of the non-linearity compensation circuit is not high, thus it can be widely applied.

It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims

1. A bandgap reference circuit, comprising: a PTAT current unit, generating a PTAT current and summing a non-linear current;a first transistor, biased by the PTAT current output from the PTAT current unit;a second transistor, biased by the PTAT current output from the PTAT current unit;an amplifier and voltage divider circuit, for outputting a reference voltage in response to a base-emitter voltage, a PTAT voltage, and a non-linear voltage; anda non-linearity compensation circuit, for converting the reference voltage as a temperature independent bias current, wherein the non-linearity compensation circuit comprises: a third transistor, biased by the temperature independent current;a first resistor, coupled to the first transistor and the third transistor, wherein the voltage drop across the first resistor is the non-linear voltage; anda second resistor, coupled to the third transistor, wherein the voltage drop across the second resistor is the non-linear voltage;wherein the non-linear effect and the temperature dependent effect of the reference voltage are compensated by the non-linearity compensation circuit.

2. The bandgap reference circuit as claimed in claim 1, further comprising: a third resistor, coupled between the PTAT current mirror and the second transistor, the voltage drop across the third resistor being VTln(n).

3. The bandgap reference circuit as claimed in claim 2, further comprising: a fourth resistor, coupled between the PTAT current mirror and a ground terminal, wherein the PTAT current and the non-linear current output from the PTAT current mirror flow through the fourth resistor, such that the voltage drop across the fourth resistor is a sum of the PTAT voltage and the non-linear voltage.

4. The bandgap reference circuit as claimed in claim 3, wherein the PTAT current mirror comprises: a fourth transistor, having a source coupled to a power source, a gate, and a drain coupled to the first transistor;a fifth transistor, having a source coupled to the power source, a gate, and a drain coupled to the third resistor; anda sixth transistor, having a source coupled to the power source, a gate, and a drain coupled to the fourth resistor;wherein the fourth, the fifth and the sixth transistors output the PTAT current and the non-linear current.

5. The bandgap reference circuit as claimed in claim 4, further comprising: a first operation amplifier, having a positive input terminal coupled to the third resistor, a negative input terminal coupled to the first transistor, and an output terminal coupled to the gates of the fourth, the fifth, and the sixth transistors;wherein the first operation amplifier adjusts the PTAT current mirror according to the voltage difference between a voltage at the positive input terminal of the first operation amplifier and a voltage at the negative input terminal of the first operation amplifier.

6. The bandgap reference circuit as claimed in claim 4, wherein the amplifier and voltage divider circuit comprises: a second operation amplifier, having a negative input terminal, a positive input terminal coupled to the drain of the sixth transistor and the fourth resistor, and an output terminal being fed back to the negative input terminal;a fifth resistor, coupled between the output terminal of the second operation amplifier and the reference voltage;a third operation amplifier, having a negative input terminal, a positive input terminal coupled to the first transistor, and an output terminal being fed back to the negative input terminal; anda sixth resistor, coupled between the output terminal of the second operation amplifier and the reference voltage;wherein the fifth resistor and the sixth resistor divide the voltages at the output terminals of the second and the third operation amplifiers for generating the reference voltage.

7. The bandgap reference circuit as claimed in claim 4, wherein the non-linearity circuit comprises: a fourth operation amplifier, having a positive input terminal coupled to the reference voltage, a negative input terminal, and an output terminal;a seventh transistor, having a source coupled to the negative input terminal of the fourth operation amplifier, a gate coupled to the output terminal of the fourth operation amplifier, and a drain;a seventh resistor, coupled between the source of the seventh transistor and the ground terminal; anda temperature independent current mirror, coupled to the third transistor and the seventh transistor;wherein the fourth operation amplifier and the seventh transistor convert the reference voltage as the temperature independent bias current, and the temperature independent current mirror mirrors the temperature independent current to the third transistor.

8. The bandgap reference circuit as claimed in claim 7, wherein the temperature independent current mirror comprises: an eighth transistor, having a source coupled to the power source, a gate, and a drain coupled to the drain of the seventh transistor, wherein the gate and the drain of the eighth transistor are coupled to each other; anda ninth transistor, having a source coupled to the power source, a gate coupled to the gate and the drain of the eighth transistor, and a drain coupled to the third transistor.

9. The bandgap reference circuit as claimed in claim 8, wherein the first transistor has: an emitter coupled to the negative input terminal of the first operation amplifier, the positive input terminal of the third amplifier, the drain of the fourth transistor and the first resistor;a base grounded; anda collector grounded.

10. The bandgap reference circuit as claimed in claim 9, wherein the second transistor has an emitter coupled to the second resistor, and a base and a collector both grounded.

11. The bandgap reference circuit as claimed in claim 10, wherein the third transistor has an emitter coupled to the drain of the ninth transistor, the first resistor and the second resistor; and a base and a collector both grounded, wherein the first resistor is coupled between the emitter of the first transistor and the emitter of the third transistor, and the second resistor is coupled between the third resistor and the emitter of the third transistor.

12. A bandgap reference circuit, comprising: a PTAT current unit, generating a PTAT current and summing a non-linear current;a first transistor, biased by the PTAT current output from the PTAT current unit;a second transistor, biased by the PTAT current output from the PTAT current unit; a first resistor, coupled to the PTAT current mirror, wherein the PTAT current and the non-linear current output from the PTAT current mirror flow through the first resistor, such that the voltage drop across the first resistor is a PTAT voltage and a non-linear voltage;a third transistor, coupled to the first resistor, wherein a base-emitter voltage of the third transistor is a negative temperature coefficient voltage, and a reference voltage is output from a node between the first resistor and the PTAT current mirror; anda non-linearity compensation circuit, converting the reference voltage into a temperature independent current, wherein the non-linearity compensation circuit comprises: a fourth transistor, biased by the temperature independent current;a second resistor, coupled to the first transistor and the fourth transistor, wherein the voltage drop across the second resistor is the non-linear voltage; anda third resistor, coupled to the fourth transistor, wherein the voltage drop across the third resistor is the non-linear voltage;wherein the non-linear effect and the temperature dependent effect of the reference voltage are compensated by the non-linearity compensation circuit.

13. The bandgap reference circuit as claimed in claim 12, further comprising: a fourth resistor, coupled between the PTAT current mirror and the second transistor, the voltage drop across the fourth resistor being VTln(n), wherein VT is the threshold voltage of the second transistor, and n is the size ratio of the second transistor to the first transistor.

14. The bandgap reference circuit as claimed in claim 13, wherein the PTAT current mirror comprises: a fifth transistor, having a source coupled to a power source, a gate, and a drain coupled to the first transistor;a sixth transistor, having a source coupled to the power source, a gate, and a drain coupled to the fourth resistor; anda seventh transistor, having a source coupled to the power source, a gate, and a drain coupled to the first resistor;wherein the fifth, the sixth and the seventh transistors output the PTAT current and the non-linear current.

15. The bandgap reference circuit as claimed in claim 14, further comprising: a first operation amplifier, having a positive input terminal coupled to the fourth resistor, a negative input terminal coupled to the first transistor, and an output terminal coupled to the gates of the fifth, the sixth, and the seventh transistors;wherein the first operation amplifier amplifies a voltage difference between a voltage at the positive input terminal of the first operation amplifier and a voltage at the negative input terminal of the first operation amplifier for driving the PTAT current mirror.

16. The bandgap reference circuit as claimed in claim 15, wherein the non-linearity circuit comprises: a second operation amplifier, having a positive input terminal coupled to the reference voltage, a negative input terminal, and an output terminal;an eighth transistor, having a source coupled to the negative input terminal of the second operation amplifier, a gate coupled to the output terminal of the second operation amplifier, and a drain;a fifth resistor, coupled between the source of the eighth transistor and the ground terminal; anda temperature independent current mirror, coupled to the fourth transistor and the eighth transistor;wherein the second operation amplifier and the eighth transistor convert the reference voltage into the temperature independent current, and the temperature independent current mirror mirrors the temperature independent current to the fourth transistor.

17. The bandgap reference circuit as claimed in claim 16, wherein the temperature independent current mirror comprises: a ninth transistor, having a source coupled to the power source, a gate, and a drain coupled to the drain of the eighth transistor, wherein the gate and the drain of the ninth transistor are coupled to each other; anda tenth transistor, having a source coupled to the power source, a gate coupled to the gate and the drain of the ninth transistor, and a drain coupled to the fourth transistor.

18. The bandgap reference circuit as claimed in claim 17, wherein the first transistor has: an emitter coupled to the negative input terminal of the first operation amplifier, the drain of the fifth transistor and the second resistor;a base grounded; anda collector grounded.

19. The bandgap reference circuit as claimed in claim 18, wherein the second transistor has an emitter coupled to the fourth resistor, and a base and a collector both grounded.

20. The bandgap reference circuit as claimed in claim 19, wherein the third transistor has an emitter coupled to the first resistor, and a base and a collector both grounded.

21. The bandgap reference circuit as claimed in claim 20, wherein the fourth transistor has an emitter coupled to the drain of the tenth resistor, the first resistor and the second resistor; and a base and a collector both grounded; wherein the second resistor is coupled between the emitter of the first transistor and the emitter of the fourth transistor, and the third resistor is coupled between the fourth resistor and the emitter of the fourth transistor.

22. A non-linearity compensation circuit, for compensating the non-linear effect and the temperature dependent effect of a reference voltage generated by a bandgap reference circuit, the bandgap reference circuit having a first transistor and a second transistor both biased by a PTAT current, and a first resistor, comprising: an operation amplifier, for receiving the reference voltage;a third transistor, coupled to the operation amplifier, wherein the operation amplifier and the third transistor convert the reference voltage into a temperature independent current;a temperature independent current mirror, coupled to the third transistor, for mirroring the temperature independent current;a fourth transistor, for receiving the temperature independent current generated by the temperature independent current mirror, biased by the temperature independent current;a second resistor, coupled to the first transistor and the fourth transistor, a non-linear voltage being across the second resistor; anda third resistor, coupled to the first resistor and the fourth transistor, the non-linear voltage being across the third resistor.

23. The non-linearity compensation circuit as claimed in claim 22, wherein the operation amplifier has a positive input terminal for receiving the reference voltage, a negative input terminal, and an output terminal.

24. The non-linearity compensation circuit as claimed in claim 23, wherein the third transistor has a source coupled to the negative input terminal of the operation amplifier, a gate coupled to the output terminal of the operation amplifier, and a drain.

25. The non-linearity compensation circuit as claimed in claim 24, wherein: the first transistor has an emitter coupled to the second resistor, and a base and a collector both grounded; andthe second transistor has an emitter coupled to the first resistor, and a base and a collector both grounded.

26. The non-linearity compensation circuit as claimed in claim 25, wherein the fourth transistor has an emitter coupled to the temperature independent current mirror, the second resistor and the third resistor; and a base and a collector both grounded.

27. The non-linearity compensation circuit as claimed in claim 26, wherein the temperature independent current mirror comprises: a fifth transistor, having a source coupled to the power source, a gate, and a drain coupled to the drain of the third transistor, wherein the gate and the drain of the fifth transistor are coupled to each other; anda sixth transistor, having a source coupled to the power source, a gate coupled to the gate and the drain of the fifth transistor, and a drain coupled to the fourth transistor.