Patent Application
20080049876
Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims. The invention will be better understood upon consideration of the specification and the accompanying drawings, in which like reference numerals designate like parts throughout the figures, and wherein:
An objective of the present invention to provide a novel non-redundant DMSK demodulator with double-error correcting capability that overcomes the shortcomings of existing demodulators, as delineated above in the Background discussion. A demodulator according to the present invention includes an error signal generator and an error detection-and-correction (EDAC) unit. The error signal generator may operate in place of the syndrome generator and syndrome register of prior demodulators. The EDAC unit may operate in place of the pattern detector of prior demodulators.
The first stage is differential detector 11. In this stage, demodulator 100 receives the modulated MSK signals. As shown in the example of
PC 27 mixes two signals: a direct received signal 31 and a delay signal 33. Delay signal 33 is the output of k-bit delay 25. The output of PC 27 is a signal Vk(t). When the decision instant occurs at the end of the signaling interval, Vk(t) at the arbitrary ith decision instant, in the absence of error, is given by
where d(i) is either “+1” or “−1” depending on whether the transmitted data are “1” or “0”.
The signal Vk(t) is input to discriminator 29. The logic of discriminator 29 yields a “1” when Vk(t) is positive, and it yields a “0” when Vk(t) is negative. Accordingly, the output Dk(i) of the k-order detector at the instant i in the absence of error can be written as
The next stage in demodulator 100 is the error signal generator 13. This stage replaces the syndrome generator stage and the syndrome register stage of the Masamura demodulator. Recall that in the Masamura demodulator, the outputs of the differential detectors are used in constructing two syndrome values and propagating those syndrome values across the syndrome register to construct a six element syndrome matrix for calculating error patterns.
In error signal generator 13, rather than constructing a syndrome matrix, demodulator I 00 may use the outputs of the k-order differential detectors to construct four error signals of the form Xi, where i=1, 2, 3 or 4. These four signals have the following two characteristics that facilitate the error detection process:
(1) the four error signals are orthogonal for the erroneous bit to be corrected; and
(2) each of all other erroneous bits appears only once in all four error signals.
As shown in
The next stage in demodulator 100 is EDAC 15. EDAC 15 receives the four error signals Xi from the output of error signal generator 13, and sums them algebraically. This operation is depicted in the block diagram of
As shown in
To demonstrate the advantages of a demodulator according to the present invention over double-error correcting DMSK demodulators such as the Masamura demodulator, a comparison of error detection techniques is now provided. Consider the outputs of differential detectors 21, 22 and 23. At an arbitrary instant i, each of these outputs has the form Dk(i) (for k=1, 2, 3). According to equation (2), these outputs may be written as:
D
1(i)=d(i)⊕e1(i)
D
2(i)=d(i)⊕d(i-1)⊕e2(i)
D
3(i)=d(i)⊕d(i-1)⊕d(i-2)⊕e3(i) (3)
In equation set (3), ek (i) (for k=1, 2, 3) represents an error symbol having a value of “1” when an error exists, and having a value of “0” otherwise. In addition, ⊕ is the Exclusive-OR (XOR) operator which yields a value of “0” when its inputs are similar and yields a value of “1” otherwise. In the absence of error, equation set (3) reduces to:
{tilde over (D)}
1(i)=d(i)
{tilde over (D)}
2(i)=d(i)⊕d(i-1)
{tilde over (D)}
3(i)=d(i)⊕d(i-1)⊕d(i-2) (4)
Equation set (4) indicates that in the absence of error the outputs D1(i) of the first order differential detector correspond to the modulated data, and outputs D2(i), D3(i) of the second order and the third order differential detectors are representative of the parity check sum of two and three successive transmitted data bits, respectively.
For comparison purposes, two syndrome values S1(i) and S2(i) are now constructed by combining the outputs D1(i) of the first order differential detector with outputs D2(i), D3(i) of the second order differential detector and third order differential detector, respectively, at the moment i:
S
1(i)=D1(i)⊕D1(i-1)⊕D2(i)
S
2(i)=D1(i)⊕D1(i-1)⊕D1(i-2)⊕D3(i) (5)
Introducing equations sets (3)-(4) into equation set (5) yields:
S
1(i)=({tilde over (D)}1(i)⊕D1(i-1)⊕{tilde over (D)}2(i))⊕(e1(i)⊕e1(i-1)⊕e2(i)) (6)
S
2(i)=({tilde over (D)}1(i)⊕{tilde over (D)}1(i-1)⊕{tilde over (D)}1(i-2)⊕{tilde over (D)}3(i))⊕(e1(i)⊕e1(i-1)⊕e1(i-2)⊕e3(i)) (7)
According to equation set (4), the quantities in the first brackets of equations (6) and (7) vanish, leading to:
S
1(i)=e1(i)⊕e1(i-1)⊕e2(i) (8)
S
2(i)=e1(i)⊕e1(i-1)⊕e1(i-2)⊕e3(i) (9)
From equations (8) and (9), it can be clearly seen that values of syndromes are determined only by the error symbols and not by the modulated digital data.
To correct for e1(i-2), the syndromes S1(i) and S2(i) from equation sets (8) and (9) are used along with their values at two preceding consecutive moments: (i-1) and (i-2), yielding:
S
1(i-1)=e1(i-1)⊕e1(i-2)⊕e2(i-1) (10)
S
1(i-2)=e1(i-2)⊕e1′(i-3)⊕e2(i-2) (11)
S
2(i-1)=e1(i-1)⊕e1(i-2)⊕e1′(i-3)⊕e3(i-1) (12)
S
2(i-2)=e1(i-2)⊕e1′(i-3)⊕e1′(i-4)⊕e3(i-2) (13)
In equations (11)-(13), e1′(i-3) and e1′(i-4) are obtained through delaying the demodulator output e1′(i-2) by T and 2T, respectively. The prime ′ in equations (10)-(13) are placed over erroneous bits which have been already corrected by the demodulator.
Equations (8)-(13) are the equations used in constructing conventional double-error correcting demodulators, such as the Masamura demodulator. Those demodulators focus on correcting e1(i-2). By inspection, equations (8)-(13) are clearly not orthogonal for e1(i-2), that is, e1(i-2) does not appear in all equations (8)-(13). Also, any error of the other errors, e1(i), e1(i-1), e2(i), e2(i-1), e2(i-2), e3(i), e3(i-1) and e3(i-2), may appear in more than one of equations (8)-(13). These characteristics—non-orthogonality, and erroneous bits appearing more than once among all error signals—make it difficult to find simple criteria for detecting the error e1(i-2). Accordingly, in conventional demodulators such as the Masumara demodulator, error—patterns were predetermined and stored in memory to be used in algorithms for detecting the error e1(i-2).
In the present invention, the syndrome equations are transformed to be made orthogonal for e1(i-2), and to ensure that an uncorrected error other than e1(i-2) appears only once. In doing so, equations (10), (11) and (13) are kept unchanged and equation (8) is added to both equation (9) and equation (12) through XOR gates. Then, the resultants are delivered to an AND gate (·) yielding
S
1(i-1)=e1(i-1)⊕e1(i-2)e2(i-1)
S
1(i-2)=e1(i-2)⊕e1′(i-3)⊕e2(i-2)
[S1(i)⊕S2(i)]·[S1(i)⊕S2(i-1)]=[e1(i-2)⊕e2(i)⊕e3(i)]·[e1(i)⊕e1(i-2)⊕e1′(i-3)⊕e2(i)⊕e3(i-1)]
S
2 (i-2)=e1(i-2)⊕e1′(i-3)⊕e1′(i-4)⊕e3(i-2) (14)
The AND gate (·) outputs a value of “1” only when all of its inputs are “1”, and it outputs a value of “0” otherwise. An examination of equation set (14) indicates that they are orthogonal for e1(i-2), and that any error of the errors e1(i), e1(i-1), e2(i), e2(i-1), e2(i-2), e3(i), e3(i-1) and e3(i-2) appears only once in equation set (14). Accordingly, the equations of equation set (14) are implemented in the logic design of the present demodulator, as shown, for example, in the embodiment of
In implementing equation set (14), each equation therein is considered as an error signal Xi (for i=1, 2, 3, 4) that may be generated directly from the outputs e1(i), e2(i) and e3(i) of the differential detectors 21, 22 and 23, respectively. For example, an equation for error signal X1 may be derived from
X
1
=e
1(i-1)⊕e1(i-2)⊕e2(i-1) (15)
Similarly, an equation for error signal X2 may be derived from the output of XOR 47, which is the Exclusive-OR of output e2(i-2) from single bit delay 64 and the output of XOR 45. The output of XOR 45 is the Exclusive-OR of output e1(i-2) from single bit delay 63 and output e1′(i-3) from single bit delay 67. Thus, X2 may be written as:
X
2
=e
1(i-2)⊕e1′(i-3)⊕e2(i-2) (16)
An equation for error signal X3 may be derived from the output of AND gate 52. That output is the Logical-And of the output of XOR 49 and the output of XOR 50. The output of XOR 49 is the Exclusive-OR of output e1(i-2) of single bit delay 63 and the output of XOR 42. The output of XOR 42 is the Exclusive-OR of output e2(i) and e3(i). The output of XOR 50 is the Exclusive-OR of the output of XOR 43 and the output of XOR 45. The output of XOR 43 is the Exclusive-OR of output e3(i-1) of single bit delay 62 and the output of XOR 41. The output of XOR 41 is output e1(i) of detector 21 and output e2(i) of detector 22. The output of XOR 45 is the Exclusive-OR of output e1(i-2) of single bit delay 63 and output e1′(i-3) of single bit delay 67. Thus, X3 may be written as:
X
3
=[e
1(i-2)⊕e2(i)⊕e3(i)]·[e1(i)⊕e1(i-2)⊕e1(i-3)⊕e2(i)⊕e3(i-1)] (17)
Finally, an equation for error signal X4 may be derived from the output of XOR 51, which is the Exclusive-OR of output e1′(i-4) of single bit delay 66 and the output of XOR 48. The output of XOR 48 is the Exclusive-OR of output e3(i-2) of single bit delay 65 and the output of XOR 45 (as recited above). Thus, X4 may be written as:
X
4
=e
1(i-2)⊕e1′(i-3)⊕e1′(i-4)⊕e3(i-2) (18)
In the above error signals Xi in equations (15)-(18), if only e1(i-2) has a value of 1, each error signal will be equal to 1, and the sum of the four error signals will be equal to 4. If e1(i-2) is equal to 1 and an additional error of the other errors e1(i), e1(i-1), e2(i), e2(i-1), e2(i-2), e3(i), e3(i-1), and e3(i-2) is also equal to 1, one of error signals Xi will be equal to zero, and the sum of error signals Xi in equations (15)-(18) will reduce to 3. This determines the threshold level employed by EDAC 15 for detecting and correcting single and double errors.
The demodulator described above as illustrated in
The next step in method 500 is step 506, which reflects the operation of EDAC stage 15. In this step, the orthogonal error signals are summed. Then, in step 508, the resulting sum is compared to a threshold value. In one embodiment, the threshold value is two. The next step is step 510. In step 510, a correction value is output based on the comparison performed in the previous step. In one embodiment, if the sum exceeds the threshold value, the resulting correction value output is a binary one. If, however, the sum does not exceed the threshold value, the resulting correction value output is a binary zero. The final step of this method is step 512, in which the correction value resulting from step 510 is added to output from the differential detection stage to produce demodulated MSK output. In one embodiment, the output from the differential detection stage that is added to the correction value is delayed by a two-bit duration.
In another embodiment of method 500, the converting step 504 uses feedback from the demodulated MSK output along with output from the differential detection stage to produce the orthogonal error signals.
To demonstrate the error correcting capabilities of the present invention, the terms “signal” and “reference” employed in coherent detection of MSK signals is used herein. In differential detection, the received signal acts both as a “signal” and a “reference” simultaneously. The relation between “signal” and “reference” for the present demodulator is shown in the table of
Since the transmitted data are carried by the difference in the phase between two signaling intervals, labels Sig and Ref may be interchanged for any decision. Re-labeling between Sig and Ref in the table of
The table in
As for triple error patterns, they are twenty (three out of six) patterns. Only nine of the twenty patterns are corrected by the demodulator. Furthermore, from
The BER performance of a demodulator according to the present invention was evaluated through testing. In the test, 40,000 digital bits were modulated using MSK modulation. The modulated bits were subjected to additive white Gaussian noise (AWGN), and the phases of the noisy modulated MSK bits were delivered to the demodulator input. Then the outputs of the demodulator were compared against the original non-modulated digital bits to calculate the BER values. The BER values along with their counterparts associated with the conventional DMSK demodulator and the single-error correcting demodulator are depicted as a function of signal to noise ratio (SNR) in
For example,
It is worth noting that the 0.9 dB SNR improvement offered by the present demodulator over the single-error correcting demodulator at the BER value of −60 dB is the maximum improvement that could be offered by the present demodulator over the non-redundant single-error correcting demodulator. On the other hand, the maximum SNR improvement that could be offered by the present demodulator over the conventional DMSK demodulator is on the order of 2.4 dB and it is offered at a BER value of −50 dB.
The invention has been disclosed in an illustrative style. Accordingly, the terminology employed throughout should be read in an exemplary rather than a limiting manner. Although minor modifications of the present invention will occur to those well versed in the art, it shall be understood that what is intended to be circumscribed within the scope of the patent warranted hereon are all such embodiments that reasonably fall within the scope of the advancement to the art hereby contributed, and that that scope shall not be restricted, except in light of the appended claims and their equivalents.
