BRIEF DESCRIPTION OF THE DRAWINGS
The disclosure will present in detail the following description of exemplary embodiments with reference to the following Figures.
FIG. 1 is a schematic top view of a plurality of memory cells arranged according to a conventional virtual-ground wiring scheme.
FIG. 2A-2F illustrate a method for manufacturing a non-volatile memory cell array according to a first embodiment of the present invention via simplified cross-sectional views of a section of a memory cell array with nitride-based non-volatile memory cells in different stages of processing.
FIG. 3 is a simplified cross-sectional view of a section of a non-volatile memory cell array with nitride-based memory cells according to a further embodiment of the invention.
FIG. 4A-4D illustrate a method for manufacturing a non-volatile memory cell array according to another embodiment of the present invention via simplified cross-sectional views of a section of a memory cell array with nitride-based non-volatile memory cells in different stages of processing.
FIG. 5A-5G illustrate a method for manufacturing a non-volatile memory cell array according to a further embodiment of the invention via simplified cross-sectional views.
DETAILED DESCRIPTION
Corresponding numerals in the different figures refer to corresponding layers, structures and features unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the exemplary embodiments and are not necessarily in all respects drawn to scale.
FIG. 1 shows a section of a memory cell array with two-bit non-volatile memory cells being arranged according to a virtual-ground wiring scheme, as for example a “programming by hot hole injection nitride electron storage” (PHINES) memory cell array. A plurality of memory cells is arranged in a matrix having rows and columns. The rows extend horizontally along a word line direction. The columns extend perpendicular to the word line direction in a column direction that corresponds to a bit line direction. Between the columns of memory cells a first, a second and a third bit line 91, 92, 93 are formed. The bit lines 91, 92, 93 connect in each case impurity regions (not shown) of neighboring columns of memory cells.
First, second, third and forth word lines 601, 602, 603, 604 connect in each case control gates (not shown) of memory cells that are arranged along the word line direction. Each memory cell is capable of storing two separated and separately controllable bits 1, 2. A first memory cell 201 and a neighboring second memory cell 202 share the second bit line 92 and are selected by the second word line 602.
Applying a program voltage between the second word line 602 and the respective bit lines 92, 91, triggers programming of bit 2 of the first memory cell 201. By applying a positive voltage on second bit line 92, holes may be generated that may migrate along the word line direction. By band-to-band tunneling induced hot hole injection a part of them is injected into a trapping layer of first memory cell 201, wherein bit 2 of memory cell 201 is programmed. Holes may also migrate in the opposite direction, i.e. to the neighboring second memory cell 202. A part of them may charge by band-to-band tunneling induced hot hole injection bit 1 of memory cell 202. A mis-programming or unintended programming of bit 1 of second memory cell 202 may result. Therefore an inhibit-bias voltage is usually applied to the third bit line 93, wherein the inhibit-bias voltage inhibits or reduces hot hole injection in the region of second memory cell 202.
Holes that are generated in the region of bit 2 of memory cell 201 may also migrate along the column direction such that they may lead to an unintended programming of bit 2 of neighboring memory cells 203, 204 sharing second bit line 92. An inhibit-biasing voltage of for example 0 Volt is therefore typically applied to the unselected word lines 601, 603, 604.
FIG. 2A to 2F illustrate a method of forming split bit lines for a nitride-based non-volatile memory cell array.
Referring to FIG. 2A, first a substrate 10 is provided. Substrate 10 may be a single crystalline semiconductor substrate, such as a silicon wafer. An upper section of the semiconductor substrate 10 may be p-conductive. On a pattern surface 100 of substrate 10 a bottom dielectric layer 211, a trapping layer 212, a top dielectric layer 213, a first gate conductor 22 and a capping layer 23 are successively disposed. A resulting layer stack is patterned by photolithographic means, wherein parallel gate structures 25 are formed. The gate structures 25 extend along a column direction and are separated, a line distance apart from each other, by space. A line distance between neighboring gate structures 25 is essentially equal to a line width of the gate structures 25.
FIG. 2A shows two neighboring gate structures 25 being disposed in each case on pattern surface 100 of substrate 10 and extending in the column direction that is perpendicular to the cross-sectional plane. A space line separates the gate structures 25 from each other. Each gate structure 25 is associated with a memory cell 20.
Each gate structure 25 comprises a bottom dielectric layer 211 adjoining pattern surface 100. Bottom dielectric layer 211 may be of silicon dioxide and may have a thickness of about 4 to 10 Nanometers, for example 6 Nanometers. Trapping layer 212 covers bottom dielectric layer 211. Trapping layer 212 may be of silicon nitride and may have a thickness of 4 to 10 Nanometers, for example 6 Nanometer. Top dielectric layer 213 covers trapping layer 212 and may have a thickness of 6 to 15 Nanometers, for example 9 Nanometer. Top dielectric layer 213 may be of silicon oxide and separates trapping layer 212 from first gate conductor 22. First gate conductor 22 forms at least a section of a control gate (not shown) and may be of doped polycrystalline silicon (polysilicon). The thickness of first gate conductor 22 may be between 20 and 40 Nanometers, for example 35 Nanometers. Capping layer 23 covers first gate conductor 22 and may be of silicon nitride. The width of each gate structure 25 may be between 20 and 100 Nanometers. The width of the space line between neighboring gate structures 25 may be equivalent to the line width of the gate structures ±20%.
Referring now to FIG. 2B, the material of first gate conductor 22 is oxidized in a temper step, wherein a sidewall oxide 24 is formed on lower sections of exposed vertical sidewalls of the gate structures 25.
Through an angled or straight implantation, pocket implants 11, 12 are formed near the edges of the gate structures 25. Via a vertically orientated implantation, connectivity lines 3 are formed between the gate structures 25, wherein the gate structures 25 act as an implantation mask. The pocket implants 11, 12 and in sections the connectivity lines 3 form n+-doped impurity regions representing symmetrical source/drain regions of the memory cells.
Referring to FIG. 2C, a sacrificial material is conformably deposited in a thickness that may be at least a third of the width of the space line. For a space line width of about 95 Nanometer, the thickness of the deposited sacrificial liner may be 40 Nanometer. The deposited sacrificial material is TEOS-based silicon dioxide by way of example. Other materials may be PE-silicon nitride and silicon oxynitride SiON. Then an anisotropic spacer etch is performed, wherein horizontal sections of the deposited sacrificial material are removed, and wherein residual vertical sections of the sacrificial material form sidewall spacers 41 that extend along the vertical sidewalls of the gate structures 25.
Then a dry etch step is performed, wherein the sidewall spacers 41 act as an etch mask shielding underlying sections of the buried connectivity lines 3. Deep, tapered split trenches 42 are formed within substrate 10 by the dry etch step. Each split trench 42 is located symmetrically between two neighboring gate structures 25 and extends to a depth in which substrate 10 is p-conductive. Each split trench 42 separates two opposing bit lines 31, 32 resulting from one connectivity line 3.
As shown in FIG. 2D, sidewall spacers 41 are then removed such that the space lines between neighboring gate structures 25 are void again.
Referring to FIG. 2E, another conformal insulating layer is deposited. The deposited layer material may be LPTEOS-based silicon oxide. The conformal insulating layer may be thinner than the sidewall spacers 41. On the other hand, the thickness should be sufficient to fill the split trenches 42 completely. For a spacer width of 95 nanometers and a thickness of the sidewall spacers 41 of about 40 nanometers, the conformal insulating layer may have a thickness of about 20 nanometers.
As shown in FIG. 2E, the conformal insulating layer is etched in a top-bottom direction, such that first residual sections of the conformal insulator layer form in each case spacer insulators 431 extending along the vertical sidewalls of the gate structures 25. Further residual sections of the conformal insulating layer form separation devices in form of split trench fills 432 of the respective split trenches 42. A small over-etch of the conformal insulating layer may be performed, such that in each case an upper edge of the spacer insulators 431 is drawn back from an upper edge of capping layer 23. First gate conductor 22 remains covered by spacer insulators 431 and the split trench fills 432 remain essentially unaffected from the over-etch. The buried bit lines 31, 32 are exposed in sections. A short deglaze may be performed to clean exposed sections of buried bit lines 31, 32.
As illustrated in FIG. 2F, a layer of conductive material is deposited. The thickness of the deposited layer of conductive material and the thickness of spacer insulator 431 may result in the thickness of sidewall spacer 41. For a sidewall spacer 41 having a thickness of 40 nanometers and a spacer insulator 431 having a thickness of 20 nanometers, the thickness of the deposited layer of conductive material may be about 20 nanometers. The conductive material may be doped silicon, WiSiX, TiN or tungsten. A spacer etch is performed that is effective on the conductive material. The spacer etch is selective to silicon nitride and silicon oxide. Horizontal sections of the conductive material are removed. Remaining sections of the conductive material form first and second bit line shunts 51, 52 that extend along the vertical outer sidewalls of spacer insulators 431. Each bit line shunt 51, 52 is connected in each case to the corresponding buried bit line 31, 32.
A further insulator material is deposited that fills a remaining gap between opposing bit line shunts 51, 52. A chemical mechanical polishing process is performed that may stop at the upper edge of capping layer 23.
As shown in FIG. 2F, remaining sections of the deposited insulator material form inter gate stack fills 50, wherein the gaps between neighboring gate structures 25 are filled completely. In the following, word lines (not shown) may be formed according to conventional techniques.
FIG. 3 is a cross-sectional view of two neighboring non-volatile memory cells 201, 202 that are arranged according to a virtual-ground wiring scheme. A first memory cell 201 is illustrated in the left half of FIG. 3 and a second memory cell 202 is illustrated in the right half of FIG. 3.
Each memory cell 201, 202 comprises a gate structure disposed on a pattern surface 100 of a semiconductor substrate 10 and an active area formed within substrate 10 and adjacent to pattern surface 100. Each gate structure comprises an ONO-stack 21 including a bottom dielectric layer 211, a trapping layer 212 and a top dielectric layer 213. Bottom dielectric layer 211 is formed adjacent to pattern surface 100 and insulates trapping layer 212 from substrate 10. Top dielectric 213 insulates trapping layer 212 from a first gate conductor 22. First gate conductor 22 forms a control gate for addressing the respective memory cell 201, 202. Spacer insulators 431 are formed on vertical sidewalls of the respective gate structure.
The active areas of memory cells 201, 202 comprise two n+-doped impurity regions formed within substrate 10 on opposing sides of the respective gate structure 25. A p-conductive channel region separates the two impurity regions. Each impurity region comprises a lightly doped pocket implant 11, 12 and a heavily doped diffused impurity region. Each heavily doped impurity region is a section of a first or a second buried bit line 31, 32 that extend along a column direction perpendicular to the section plane. Each first and second bit line 31, 32 connects a plurality of impurity regions of a column of memory cells, wherein the memory cells are arranged in a matrix having columns and rows.
Each pair of first 31 and second 32 buried bit line emerge from one contiguous impurity line that is split up by an etch and a subsequent insulator fill process. From the fill process, split trench fills 432 result that form separation devices separating in each case the first 31 and the second 32 buried bit line of one of the pairs of first 31 and second 32 bit lines. Along the vertical outer sidewalls of spacer insulator 431 first and second bit line shunts 51, 52 of a high conductivity material such as heavily doped polysilicon, a metal, a metal nitride or metal silicide extend along the columns of memory cells. Each bit line shunt 51, 52 adjoins pattern surface 100 in a section in which the respective buried bit line 31, 32 is formed within substrate 10 such that each bit line shunt 51, 52 is electrically connected to the respective buried bit line 31, 32. An inter gate stack fill 50 separates opposing bit line shunts 51, 52.
Word lines 6 comprise in each case a second gate conductor 61, a high conductivity layer 62 covering second gate conductor 61, and a word line cap 63 covering high conductivity layer 62 and extend perpendicular to the column direction. Each word line 6 connects the control gates 22 of a plurality of memory cells 201, 202 that are arranged along a row of memory cells. Word lines 6 are line-shaped. Adjacent word lines 6 are separated by insulating inter word line fills (not shown).
Each memory cell 201, 202 is capable of storing electric charge in two separated and separately controllable trapping sections 1, 2. Bit 1 is programmed by applying a positive programming voltage between second buried bit line 32 and control gate 22, wherein a band-to-band tunnel induced injection of hot holes generated near second buried bit line 32 is enabled.
Programming of bit 2 is performed by applying a programming voltage between first buried bit line 31 (positive) and control gate 22 (negative) accordingly. As the holes are generated only in vicinity of the respective buried bit line 31, the neighboring second memory cell 202 remains unaffected. Migration of holes from first buried bit line 31 to second memory cell 202 is essentially suppressed. The size of the memory cell array remains unaffected. Neighboring first and second buried bit lines 31, 32 are switched to different sensing/driving stages or to the same sensing/driving stages at different times.
FIG. 4A to FIG. 4B illustrate a further method of forming the bit lines and the separation devices, wherein the order of implantation and etch process is altered.
FIG. 4A follows FIG. 2A, wherein a sidewall oxide 24 is formed on lower sections of exposed vertical sidewalls of the gate structures 25. Between each pair of neighboring gate structures 25 one joint pocket implant 19 is formed through a vertical orientated implantation. Each joint pocket implant 19 forms a continuous n-doped impurity region in upper sections of substrate 10 beneath the space lines.
Referring to FIG. 4B sidewall spacers 41 are formed, that extend along the vertical sidewalls of gate structures 25 as described above with regard to FIG. 2C. A separation device is formed through a dry etch step, wherein sidewall spacers 41 and gate structures 25 act as an etch mask and shield underlying sections of the buried joint pocket implant 19. Deep, tapered split trenches 42 within substrate 10 emerge from the dry etch step. Each split trench 42 is adjusted symmetrically to the edges of the two neighboring gate structures 25. From each joint pocket implant 19 two separated pocket implants 11, 12 emerge, wherein each single pocket implant 11, 12 is assigned to one of the gate structures 25.
As illustrated in FIG. 4C, sidewall spacers 41 are then removed and another conformal insulating layer is deposited, wherein split trenches 42 are filled with the insulating material. The filled split trenches 42 form separation devices 432. The conformal insulating layer is etched in a top-bottom direction, such that spacer insulators 431 emerge from the conformal insulator layer. Spacer insulators 431 extend along the vertical sidewalls of the gate structures 25 and are thinner than the sidewall spacers 41 were. Sections of the buried pocket implants 11, 12 between the outer edges of spacer insulator 431 and separation device 432 remain exposed. A heavy dose vertical bit line implant 30 is performed, wherein spacer insulator 431 shields sections of the low doped pocket implants 11, 12 near the respective gate structure 25. Buried bit lines 31, 32 are formed through the bit line implant 30 on both sides of separation device 42, wherein the thickness of spacer insulators 431 determine the distance between the gate electrode 25 and the buried bit lines 31, 32.
Referring to FIG. 4D, bit line shunts 51, 52 may be provided as described above.
Referring to FIG. 5A to 5G, a further method is described by means of cross-sectional views illustrating two neighboring memory cells 20 in course of processing.
FIG. 5A corresponds to FIG. 2A and shows gate structures 25 of two adjacent memory cells 20. Each gate structure 25 comprises an ONO-stack 21 including a nitride-based trapping layer 212 sandwiched between a bottom dielectric layer 211 and a top dielectric layer 213. Bottom dielectric layer 211 insulates trapping layer 212 from a semiconductor substrate 10 and top dielectric layer 213 separates trapping layer 212 from a first gate conductor 22 representing at least a section of a control gate. In this stage of processing, a capping layer 23 covers gate conductor 22, which typically consists of silicon nitride. The gate structures 25 have a width of about 95 Nanometers or less and the distance between two adjacent gate structures 25 is essentially identical to the width of the gate structures 25.
As shown in FIG. 5B a thermal oxide forms a sidewall oxide 24 that covers exposed vertical sidewalls of gate conductor 22. Sidewall oxide 24 is grown selectively on exposed vertical sidewalls of first gate conductor 22 by thermal oxidation. The thickness of sidewall oxide 24 may be 5 Nanometers. An anisotropic etch is performed that is effective on the silicon of substrate 10, wherein the gate structures 25 act as an etch mask. Between the gate structures 25, the substrate is etched back to a depth of a few Nanometers. The depth of the resulting shallow grooves may be about 10 Nanometers.
A thin silicon nitride liner is deposited and opened by a spacer etch. The thickness of the thin silicon nitride liner may be 7 Nanometers. Horizontal sections of the thin silicon nitride liner are removed. Vertical sections of the thin silicon nitride liner form a pre-etch liner 70 covering vertical sidewalls of the gate structures 25 and of the shallow grooves.
Referring to FIG. 5C, an anisotropic silicon etch is performed that is selective to silicon nitride. Deep grooves 7 are formed between two adjacent gate structures 25 respectively. The depth of the deep grooves 7 is determined by the specified (predetermined) resistance that should be obtained for the buried bit lines. A thermal oxidation is performed such that an insulator oxide 71 lines a bottom portion of the deep grooves 7. FIG. 4C illustrates further silicon nitride pre-etch liner 70 covering an upper portion of each deep groove 7. The thickness of the insulator oxide 71 may be about 5 Nanometers. The depth of the deep grooves 7 may be 50 Nanometers and more.
Referring to FIG. 5D, a liner deglaze is performed. Pre-etch liner 70 may be removed by a THF 2 nm oxide equivalent removal and a hot phosphoric acid 10 nm silicon nitride equivalent removal. By removal of pre-etch liner 70, the upper portion of the deep grooves 7 is exposed. The exposed sections of substrate 10 are cleaned via a THF chemistry. Then silicon is epitaxially grown selectively on the exposed sections of substrate 10 to a target thickness. The target thickness may be about a third of the space line width.
FIG. 5D shows the silicon extensions 72 adjoining previously exposed sections of substrate 10 in the upper portion of each deep groove 7, wherein the upper portion corresponds to the shallow groove formed before deposition of pre-etch liner 70.
The extensions 72 may in each case form at least in sections an impurity regions of the respective memory cell 20.
As illustrated in FIG. 5E a conformal conductive liner is deposited. The conformal conductive liner may consist of heavily doped polysilicon, titan nitride, tungsten, another metal or conductive metal compound or a combination of them. The thickness of the conductive liner is selected such that a void remains between opposing sections of the conductive liner in the upper section of the deep grooves 7. A spacer etch is performed, such that horizontal sections of the conductive liner on top of capping liner 23 are removed and such that in each deep groove 7 the conductive liner is split up into two separate conductive lines 8.
According to FIG. 5F, a conformal or hyper conformal divot fill is performed, wherein an insulator material such as silicon dioxide, LPTEOS-based silicon oxide or a spin-on dielectric with high electric breakdown strength is deposited forming an inter bit line fill 80 filling the gaps between opposing conductive lines 8. Inter bit line fill 80 is recessed to a lower edge of first gate conductor 22. The recess of inter bit line fill 80 may be self-aligned to the pinching level of the conductive lines 8, wherein the pinching level results from the epitaxial grown silicon sections 72.
Referring to FIG. 5G, exposed upper sections of conductive lines 8 are removed selectively with respect to inter bit line fill 80.
Thus highly conductive, self-aligned first and second 81, 82 bit lines are formed between adjacent gate structures 25.
While the invention has been described in detail with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. Accordingly, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and equivalence.
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List of reference signs
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1
bit 1
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2
bit 2
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3
connectivity line
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8
conductive line
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10
substrate
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11
pocket implant
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12
pocket implant
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19
joint pocket
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20
memory cell
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21
ONO-stack
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22
first gate conductor
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23
capping layer
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24
sidewall oxide
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30
bit line implantation
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31
first bit line
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32
second bit line
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41
sidewall spacer
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42
split trench
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50
inter gate stack fill
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51
first bit line shunt
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52
second bit line shunt
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61
second gate conductor
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62
high conductivity layer
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63
word line cap
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70
pre-etch liner
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71
insulator oxide
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72
extension
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80
inter bit line fill
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81
first bit line
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82
second bit line
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91
bit line 1
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92
bit line 2
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93
bit line 3
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100
pattern surface
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201
memory cell 1
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202
memory cell 2
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203
memory cell 3
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204
memory cell 4
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211
bottom dielectric layer
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212
trapping layer
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213
top dielectric layer
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431
spacer insulator
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432
split trench fill
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601
first world line
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602
second world line
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603
third world line
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604
forth world line
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Patent Application
20070269948
