Claims
- 1. A process for fabricating a programmable non-volatile memory cell comprising the steps of:
- forming a first gate oxide over a channel region in a semiconductor surface;
- forming a conductive layer over said first gate oxide;
- etching said first conductive layer to form a floating gate over a first portion of said channel region;
- forming a pass gate oxide over a second portion of said channel region in said surface and a dielectric layer adjacent said floating gate where said dielectric layer is thicker than said first gate oxide and said pass gate oxide is thicker than said dielectric layer;
- forming a second condutive layer over said dielectric layer and said pass gate oxide and said floating gate;
- etching said second conductive layer to form a control gate and align an edge of said control gate with an edge of said floating gate; and
- forming source and drain regions at the ends of said channel region in said surface, said source and drain aligned to said control gate.
- 2. The process of claim 1, further comprising the step of:
- doping a portion of said channel region beneath said pass gate oxide to a concentration greater than that of a portion of said channel region beneath said floating gate.
Parent Case Info
This is a Division of application Ser. No. 08/093,517 filed on Sept. 15,1993 which is a Continuation of Ser. No. 07/641,952 filed Jan. 17, 1991, now abandoned.
US Referenced Citations (3)
Foreign Referenced Citations (2)
Number |
Date |
Country |
58-209164A |
Dec 1983 |
JPX |
2107519 |
Oct 1982 |
GBX |
Divisions (1)
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Number |
Date |
Country |
Parent |
93517 |
Sep 1993 |
|
Continuations (1)
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Number |
Date |
Country |
Parent |
641952 |
Jan 1991 |
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