Claims
- 1. A semiconductor device, comprising:
a semiconductor substrate; a first highly doped layer having a first conductivity type uniformly implanted into the semiconductor substrate a first predetermined distance below a surface of the semiconductor substrate; a first insulating layer formed over the semiconductor substrate; a charge storage layer formed over the first insulating layer; a second insulating layer formed over the charge storage layer; a source having a second conductivity type implanted into a first predetermined region of the substrate; a drain having the second conductivity type implanted into a second predetermined region of the substrate; and a second highly doped layer having the first conductivity type implanted in only a drain side of the first insulating layer and extending through the drain and under the first insulating layer a second predetermined distance from an edge of the first insulating layer.
- 2. The semiconductor device of claim 1, wherein the substrate directly below the first insulating layer and above the first highly doped layer has a dopant concentration lower than a dopant concentration of the first highly doped layer.
- 3. The semiconductor device of claim 2, wherein the substrate directly below the first insulating layer is the first conductivity type.
- 4. The semiconductor device of claim 2, wherein the charge storage layer comprises nitride.
- 5. The semiconductor device of claim 2, wherein the substrate directly below the first insulating layer is of a second conductivity type, different from the first conductivity type.
- 6. The semiconductor device of claim 1, wherein the charge storage layer comprises polysilicon.
- 7. The semiconductor device of claim 1, wherein the charge storage layer comprises a plurality of nanocrystals.
- 8. The semiconductor device of claim 1, wherein the first highly doped layer or the second highly doped layer is implanted using indium.
- 9. The semiconductor device of claim 1, wherein a channel region formed between the source and the drain below the first insulating layer has a length of between 0.35 micron and 0.06 micron.
- 10. The semiconductor device of claim 9, wherein the second highly doped region is implanted at an angle determined to increase a dopant gradient within the second predetermined distance and to maintain a relatively low dopant concentration within the channel region.
- 11. The semiconductor device of claim 10, wherein the semiconductor device is a non-volatile memory cell and during an access to the memory cell a depletion region forms in the channel region at an edge of the channel region to mask the increased dopant gradient within the second predetermined distance.
- 12. A method for forming a semiconductor device, comprising the steps of:
providing a semiconductor substrate; implanting a first highly doped layer having a first conductivity type into the semiconductor substrate a first predetermined distance below a surface of the semiconductor substrate; forming a first insulating layer over the semiconductor substrate; forming a charge storage layer over the first insulating layer; forming a second insulating layer over the charge storage layer; implanting a source having a second conductivity type into a first predetermined region of the substrate; implanting a drain having the second conductivity type into a second predetermined region of the substrate; and implanting a second highly doped layer having the first conductivity type in only a drain side of the first insulating layer and extending through the drain and under the first insulating layer a second predetermined distance from an edge of the first insulating layer.
- 13. The method of claim 12, wherein the substrate directly below the first insulating layer and above the first highly doped layer has a dopant concentration lower than a dopant concentration of the first highly doped layer.
- 14. The method of claim 12, further comprising the step of forming a gate electrode over the second insulating layer.
- 15. The method of claim 14, further comprising the step of forming a masking layer over the source and the gate electrode before implanting the second highly doped layer.
- 16. The method of claim 12, wherein the charge storage layer comprises nitride.
- 17. The method of claim 12, wherein the charge storage layer comprises polysilicon.
- 18. The method of claim 12, wherein the charge storage layer comprises a plurality of nanocrystals.
- 19. The method of claim 12, wherein the first highly doped layer and/or the second highly doped layer is implanted using indium.
- 20. The method of claim 12, wherein a channel region formed between the source and the drain below the first insulating layer has a length of between 0.35 micron and 0.06 micron.
- 21. The method of claim 20, wherein the second highly doped region is implanted at an angle determined to increase a dopant gradient within the second predetermined distance and to maintain a relatively low dopant concentration within the channel region.
- 22. The method of claim 21, wherein the semiconductor device is a non-volatile memory cell and during an access to the memory cell a depletion region forms in the channel region at an edge of the channel region to mask the increased dopant gradient within the second predetermined distance.
- 23. A semiconductor device, comprising:
a semiconductor substrate; a highly doped layer having a first conductivity type uniformly implanted into the semiconductor substrate a first predetermined distance below a surface of the semiconductor substrate; an oxide-nitride-oxide structure formed over the semiconductor substrate; a gate electrode formed over the oxide-nitride-oxide structure; a source having a second conductivity type implanted into a first predetermined region of the substrate; a drain having the second conductivity type implanted into a second predetermined region of the substrate; and an angled halo having the first conductivity type implanted in only a drain side of the oxide-nitride-oxide structure and extending through the drain and under the oxide-nitride-oxide structure a second predetermined distance from an edge of the oxide-nitride-oxide structure.
- 24. The semiconductor device of claim 23, wherein the substrate directly below the oxide-nitride-oxide structure and above the highly doped layer has a dopant concentration lower than a dopant concentration of the highly doped layer.
- 25. The semiconductor device of claim 24, wherein the substrate directly below the oxide-nitride-oxide structure is the first conductivity type.
- 26. The semiconductor device of claim 24, wherein the substrate directly below the oxide-nitride-oxide structure is of a second conductivity type, different from the first conductivity type.
- 27. The semiconductor device of claim 23, wherein the highly doped layer and/or the angled halo is implanted using indium.
- 28. The semiconductor device of claim 23, wherein the angled halo is implanted at an angle determined to increase a dopant gradient within the second predetermined distance and to maintain a relatively low dopant concentration within a channel region formed between the source and the drain below the oxide-nitride-oxide structure.
- 29. The semiconductor device of claim 28, wherein the semiconductor device is a non-volatile memory cell and during an access to the memory cell a depletion region forms in the channel region at an edge of the channel region to mask the increased dopant gradient within the second predetermined distance.
RELATED APPLICATIONS
[0001] This is related to United States Patent Application by Hoefler et al. having attorney docket number SC12314TP, filed on even date, and entitled “Non-Volatile Memory Device and Method for Forming.”