Patent Application
20070268905
The present disclosure may be better understood, and its numerous features and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates similar or identical items.
In general, the CPU 102 processes computer readable instructions, such as software programs. During operation, the CPU 102 generates memory access requests to the RAM 110 and to the non-volatile memory 104 to request access to particular data. The GPMI 106 may receive the memory access requests, retrieve the requested payload data, and provide the payload data and the associated error detection code and error correction code (ECC) data to the error detection/correction module 108. The error detection/correction module 108 may process the payload data to identify locations and values of errors within the payload data. The error detection/correction module 108 may correct the errors based on the identified locations and values and may store the error corrected data 112 in the RAM 110. Depending on the implementation, the GPMI 106 may transfer the requested data via the bus 116 for storage in RAM 110. The error detection/correction module 108 may load the transferred data 114 from the RAM 110 for processing based on error detection and ECC data provided by the GPMI 106.
In general, the non-volatile memory 104 may be partitioned into a data payload region and a redundant data region. Payload data may be stored in the data payload region, and error detection and error correction data associated with the payload data may be stored in the redundant data region. Additionally, metadata error correction data related to the error detection and error correction data may be stored in the redundant data region or may be stored within a metadata redundant data region, depending on the specific implementation.
The redundant data area 206 includes redundant data associated with each of the individual payload areas 208, 210, 212 and 214. The redundant data area 206 as shown includes parity areas 216, 220, 224, 228 and 232 and syndrome areas 218, 222, 226, and 230. In a particular embodiment, each of the parity areas 216, 220, 224, 228 and 232 and each of the syndrome areas 218, 222, 226, and 230 include up to 12 bytes of information related to payload data of one of the payload areas 208, 210, 212, and 214.
For example, the payload area 208 includes 512 bytes of payload data. The parity area 216 and the syndrome area 218 each include 12 bytes of parity data and 12 bytes of syndrome data, respectively. The 12 bytes of parity data and the 12 bytes of syndrome data are associated with the 512 bytes of payload data of the payload area 208. In a particular example, the parity areas 216, 220, 224, 228 and 232 each include eight 9-bit symbols with three additional bytes of alignment padding. The syndrome areas 218, 222, 226, 230 and 234 each include eight 9-bit symbols with three additional bytes of alignment padding.
In general, the metadata parity data stored in parity area 232 and the computed metadata syndrome data stored in syndrome area 234 are associated with the parity data of the of the parity areas 216, 220, 224, and 228 and with the syndrome data of the syndrome areas 218, 222, 226, and 230, respectively. Additionally, the redundant data area 206 includes 20 bytes of auxiliary storage 236. The metadata parity data and the metadata syndrome data represent parity data and syndrome data of the data stored in the parity areas 216, 220, 224, and 228 and in the syndrome areas 218, 222, 226, and 230. In one embodiment, the parity data and the syndrome data represent metadata of the payload data. The data stored in the parity area 232 and in the syndrome area 234 represent metadata of the metadata.
In general, the partitions and payload areas 204 and 206 of the non-volatile memory 104 of
In an alternative embodiment, the partitions and payload areas may be adjusted for a 4K page size. For example, the data payload area 204 may be extended to include eight payload areas, each having approximately 512 bytes of information. Each of the parity areas 216, 220, 224, and 228 and each of the syndrome areas 218, 222, 226 and 230 in the redundant data area 206 may similarly be extended to store 20 bytes of parity data and 20 bytes of syndrome data. In this instance, the parity data area 232 and the syndrome data area 234 may include 12 bytes of parity and syndrome data associated with the parity areas 216, 220, 224, and 228 and with the syndrome areas 218, 222, 226, and 230, but the auxiliary data in the auxiliary data area 236 may be increased. In one instance, the auxiliary data is increased to approximately 68 bytes of information. The payload parity/syndrome areas may thus consist of sixteen 9-bit symbols with two bytes of alignment padding, and the auxiliary parity/syndrome area 236 may consist of eight 9-bit symbols with three bytes of alignment padding. In another embodiment, the metadata ECC data may be stored in a separate data area.
In another embodiment, the redundant data area 206 and the payload data area 204 may be distributed. In this instance, the parity areas 216, 220, 224, and 228 and the syndrome areas 218, 222, 226 and 230 may be at non-contiguous memory address locations. For example, the payload data of the payload data area 204 may be stored in separate payload partitions at various memory addresses, which may be interspersed with redundant data partitions of the redundant data area 206. For example, the payload area 208, the associated parity area 216, and the syndrome area 218 may be stored in adjacent memory partitions within the non-volatile memory 104.
In general, the parity and syndrome data provide information that can be used by the error detection/correction module 108 to detect and correct data errors within the payload data. Moreover, if the parity/syndrome data includes errors, the metadata ECC data may be used by the error detection/correction module 108 to detect and correct such errors.
In general, the payload data is stored in a payload data area of the non-volatile memory and the redundancy data associated with the payload data is stored in a redundant data area of the non-volatile memory. The redundancy data includes a first payload error correction code (ECC) data associated with a first payload data region, and a first metadata associated with the first payload data region. A metadata ECC data associated with the first metadata may also be stored in the redundant data area. The metadata ECC data may be retrieved and used to correct errors in the redundancy data, without having to retrieve the payload data from memory. The first metadata may include cyclic redundancy check (CRC) data, or other types of error detection data. Alternatively, the first metadata may include an error syndrome, which can be used by an error correction module to correct an error in payload data or in metadata associated with the payload data.
In general, the AHB bus master arbiter and controller 408 couples the error detection/correction module 108 to the bus 116 for communication with other modules and components of the system 100. In general, the AHB bus master arbiter and controller 408 provides high bandwidth and low latency for data transactions by performing burst operations, fixed priority arbitration and the like. Moreover, the AHB bus master arbiter and controller 408 limits stalls from the NAND interface (the GPMI 106.
In general, the syndrome generation module 402 receives blocks of data from the non-volatile memory 104 via the general purpose memory interface (GPMI) 106. The blocks of data may include a fixed amount of payload data and parity data associated with the fixed amount of payload data. The syndrome generation module 402 may also receive control information associated with a data block. The syndrome generation module 402 calculates syndrome information from the payload and parity data. The syndrome generation module 402 provides the payload data, the parity data and the calculated syndromes to the bus master arbiter and controller 408.
The bus master arbiter and controller 408 may include an asynchronous first input first output (FIFO) register (as shown in
Alternatively, the syndrome generation module 402 may store the payload data, the parity data, the syndrome information and the control information in a system memory or another memory location, such as RAM 110 in
The error equation solver and evaluator 406 receives the syndromes 410 of the payload data from the bus master arbiter and controller 408. The error equation solver and evaluator 406 processes the syndromes 410 to produce a symbol index 412 and a symbol mask 414. The symbol index 412 identifies symbols that contain one or more errors, and the symbol mask 414 indicates the particular bits within the symbol which should be complemented to correct the error. The error equation solver and evaluator 406 notifies the bus master arbiter and controller 408 when processing is complete so that the bus master arbiter and controller 408 can present the next set of syndromes 410. The error equation solver and evaluator 406 provides pairs of error indexes 412 and masks 414 to the error correction unit 407, which complements the particular bit errors via the bus master arbiter and controller 408. The error equation solver and evaluator 406 may also provide an indication of how many corrections were required or an indication that the payload data was uncorrectable to the bus master arbiter and controller 408.
In general, if the syndrome generation module 402 marks a block of data as containing errors, then the bus master arbiter and controller 408 schedules an error correction pass through the key equation solver. Thus, the syndrome generation module 402 performs an error detection on blocks of data, and the error correction process is performed by the error equation solver and evaluator 406 only when errors are detected.
The bus master arbiter and controller 408 may be adapted to complement data bits within a block of memory using the error index and the error mask. The corrected data may be stored in a system memory, in a temporary memory such as a cache memory or the RAM memory 110, in a non-volatile memory, such as the non-volatile memory 104, and/or in any combination thereof.
In general, the error equation solver and evaluator 406 can provide an error index 412 and an error mask 414 for a correctable block of data, where a block of data includes n-symbols minus 2t-parity symbols. The n-symbols refers to a block size in symbols (such as 512 symbols in the payload data areas of
The syndrome generation module 402 calculates 2t syndromes. The error equation solver and evaluator 406 generates a set of 2t linear equations with 2t unknown variables. The error equation solver and evaluator 406 solves the set of equations using an Euclidean algorithm, which divides a special polynomial of degree 2*t (e.g. x8 or x16) by the syndrome polynomial formed from the 2t syndromes. Once the division generates a remainder of degree that is less than or equal to the number of correctable errors (t), the error equation solver and evaluator 406 terminates the algorithm and creates an error evaluator polynomial and an error locator polynomial to determine the error index 412 and the error mask 414.
The syndrome generator 402 is coupled to the asynchronous FIFO 506 and to the GPMI and counters 504. The asynchronous FIFO 506 is also connected to the GPMI and counters 504 and to the bus master arbiter and controller 408. The GPMI and counters 504 is connected to the bus master arbiter and controller 408 and to the error correction module 108.
The error correction module 108 includes a key equation solver (KES) interface 512, a key equation solver 514, a Chein search and Forney evaluator 516, a symbol to address converter 518, one or more registers 520, and an error correction module 522. The KES interface 512 is coupled to the bus master arbiter and controller 408, to the key equation solver 514, and to the error correction module 522. The Chein search/Forney Evaluator 516 is connected to the symbol to address converter 518, which may be connected to one or more registers 520 and to the error correction module 522. The error correction module 522 is connected to the bus master arbiter and controller 408.
The bus master arbiter and controller 408 includes a bus master interface 508 and an arbiter and controller 510. The bus master interface 508 is connected to the bus 116, and the arbiter and controller 510 is connected to the GPMI and counters 504, to the asynchronous FIFO 506, to the KES interface 512, and to the error correction module 522.
In general, the GPMI parallel Input/output 502 provides address information to the GPMI and counters 504. The syndrome generation module 402 provides a block number to the GPMI and counters 504. Additionally, the syndrome generation module 402 provides payload data blocks to the asynchronous FIFO 506 along with calculated syndrome data, parity data, and control information. On read operations, the payload data blocks are processed by the syndrome generation module 402 and passed to the asynchronous FIFO 506. In one particular implementation, except for the last write operation, the output word of the syndrome generation module 402 consists of 32-bits of data (meaning either payload, parity or syndrome bits) and 4 flag bits. The last output word of a payload data block may be a status word that identifies whether certain conditions were detected within the block that might save processing time. For example, if the symbol generation module 402 did not detect an error, error correction may be avoided. The asynchronous FIFO 506 may provide a flow control signal to the syndrome generation module 402 to control the transfer of the data blocks and syndrome information. The data block and associated parity and syndromes information may be written to the asynchronous FIFO 506.
In addition, there are a number of control signals that pass from the GPMI and counters 504 and from the syndrome generation module 402 to the bus master arbiter and controller 408, such as a mode bit, memory addresses, a channel number, and the like. Typically, the control information may be included at the beginning of a payload data block.
The asynchronous FIFO 506 provides the data, syndrome information, parity data, and control information to the GPMI and counters 504. In general, the control information may include bit flags that indicate the first word of a new data block, the start and end of a data block transfer, and a status word flag. Control logic of the asynchronous FIFO 506 may monitor the status of the FIFO and report a full condition to the syndrome generation module 402 whenever the FIFO has insufficient space for new data.
The GPMI and counters 504 transfers the data and syndrome information to the KES interface 512. The KES interface 512 provides the calculated syndrome data to the key equation solver 514 for error detection. If a block of data is marked with no error, the GPMI and counters 504 may transfer the block of data to the arbiter and controller 510, bypassing the KES interface 512. The key equation solver 514 provides error detection information to the Chein search and Forney Evaluator unit 516.
Once the key equation solver 514 has completed the error detection, the KES interface 512 provides the block information to the error correction module 522. The Chein search and Forney evaluator (CF) unit 516 calculates error masks and error indices for the data block and provides them to the error correction unit 522. The symbol to address converter 518 converts the symbol index into a system word-aligned address and converts the symbol mask into a word-aligned mask.
The error correction module 522 performs a word read-modify-write operation to complete an error correction. Depending on the operating mode of the system, the number of read-write-modify corrections may vary. For example, there may be up to 16 read-modify-write corrections for an 8-bit mode, and up to 8 read-modify-write corrections for a 4-bit mode.
It should be understood that while the above discussion focused on a generic read operation, the error correction may be applied in a number of ways. For example, changes to payload data may also require changes to the metadata and to the metadata ECC data stored in the redundant data area of the non-volatile memory. Errors detected in the payload data may be corrected using the metadata. Errors in the metadata may be corrected using the metadata ECC data. The recovery process may be applied to the payload data, to the payload error detection data (such as parity data), to metadata, to metadata ECC data, and so on. By storing the metadata, the parity data, the metadata error correction code (ECC) data, and the payload data separately, the error correction module 108 can access one or more of the data elements to efficiently correct data errors.
In general, each write operation causes the error correction module to generate the syndrome data based on the payload data (e.g. metadata) and to generate metadata ECC data based on the syndrome data. During an error correction process, the metadata ECC data may be used by the error correction module to correct the syndrome data, and the syndrome data may be used to correct the payload data. These error correction processes may be performed sequentially or independently from one another.
In general, the reading of payload data from the non-volatile memory may proceed as described with respect to
By storing the metadata and error detection data in a redundant data area of the non-volatile memory and by storing metadata error correction code (ECC) data associated with the metadata and the error detection data separately within the redundant data area, logic within the error correction module may correct for bit errors in the payload data and within the metadata of the payload data, without having also to load the payload data.
The metadata ECC data may include a syndrome associated with the metadata of payload data. The non-volatile memory may include payload ECC data as well as metadata ECC data. Each data payload within the data payload area may have a corresponding parity data area and syndrome data area within the redundant data area. Each corresponding parity data area and syndrome data area pair may have a corresponding metadata ECC data stored within the redundant data area. Thus, a first data payload may have first parity data and first metadata, which are stored in a redundant data area. The first parity data and the first metadata may have corresponding first metadata ECC data. A second data payload may have a second parity data and a second metadata, which are stored in a redundant data area. In one embodiment, the first metadata ECC data includes metadata ECC data for the first and the second parity data and the first and the second metadata. In a second embodiment, second metadata ECC data includes metadata ECC data for the second parity data and the second metadata.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true spirit and scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
