Non-volatile memory module

FIELD OF THE INVENTION
This invention relates to memory devices and more particularly memory modules for use in disk storage sub-systems.
BACKGROUND OF THE INVENTION
As is known in the art, the increasing performance characteristics of central processor units (CPUs) and memories has not generally been matched by similar performance increases in peripheral sub-systems. This has lead to the development of disk sub-systems which include disk memory arrays implemented as redundant arrays of inexpensive disks (RAID).
As is also known, there are presently at least five different organizations of disk arrays which are generally referred to as RAID levels. For example, the so-called RAID level 5 or simply RAID-5 systems refer to those systems in which data and parity check information are distributed across all disks in the disk array. Because of the data integrity and availability advantages provided by RAID-5 systems, there is presently a trend to implement the RAID-5 data management protocol in disk storage sub-systems.
One problem with such disk storage sub-systems, however, is that there exists a set of failure modes which can occur and which cannot be addressed by the RAID-5 protocol or any other RAID protocol. Such failure modes may lead to corrupted and/or lost data. The corrupted or lost data may be restored by a user, however, such restoration may involve considerable time and expense. It would, therefore, be desirable to increase the data integrity of disk storage sub-systems implemented as a RAID system, and in particular it would be desirable to increase the data integrity of those disk storage sub-systems implementing a RAID-5 data management protocol.
There are several approaches to solving the problem of failure modes leading to corrupted and/or lost data in RAID systems. One approach to solving this problem is to provide the disk sub-system with a memory module which includes an electrically erasable, programmable read-only memory (EEPROM). Data and parity check information may be stored in the EEPROM prior to being written onto the disk array. However, one problem with this approach is that presently available EEPROMs can accommodate only a limited number of write cycles before the EEPROM loses its ability to retain data. Presently, the number of guaranteed write cycles of an EEPROM is in the order of 100,000 writes for relatively small devices and in the order of 10,000 writes in larger arrays. Furthermore, the array sizes are relatively small compared with other available memory devices.
Another problem with the EEPROM approach is the relatively long write cycle time required. This is especially true when the write must be performed on a byte by byte basis. However, even when a page write can be employed, the write cycle time is typically in the range of tens of milliseconds for small page sizes.
Additionally, the cost per megabyte of memory for EEPROMs is relatively high compared with other types of memories. Due to the above and other limitations, EEPROMS are thus typically used to hold data that changes infrequently and not used for general system random access memory (RAM).
Another approach to solving the corrupted and/or lost data problem is to provide a memory module having a flash memory disposed thereon. The flash memory cell structure is similar to that of an EEPROM. Flash memories, however, are provided in much smaller cell sizes than EEPROMs. Consequently, flash memories are provided having greater bit densities and thus are much more cost effective to manufacture (i.e. they have a lower cost per megabyte than an EEPROM).
Flash memories, however, also have a limited number of write cycles. Typically, the number of write cycles is in the order of 10,000 cycles. Furthermore, flash memories have the added limitation that they cannot be selectively erased. That is, the entire flash memory array must be erased and the time to erase a typical flash memory device is generally about one millisecond. Thus, flash memory devices are also typically used to hold data that changes infrequently.
It would thus be desirable to provide a non-volatile memory circuit having a relatively low cost while still providing a reliable technique for improving the data integrity of a disk storage sub-system in which the non-volatile memory circuit is employed.
SUMMARY OF THE INVENTION
In accordance with the present invention, a non-volatile memory module includes a battery, a charging circuit coupled to the battery, at least one volatile random access memory (RAM) and a switch coupled between the battery and the volatile RAM. With this particular arrangement, a non-volatile memory circuit for improving the data integrity of a disk storage sub-system including a sub-system controller and a disk drive is provided. The non-volatile memory circuit may be provided as a non-volatile single in-line memory module (NVSIMM) adapted to couple to a standard SIMM connector of a configuration well known in the art. The NVSIMM may include a printed circuit board having the battery, charging circuit, volatile RAM and switch disposed thereon and having a connector disposed on one edge thereof. The connector may be provided as a type mateable to a vertical or semi-vertical edge type connector disposed on a motherboard thus allowing the NVSIMM to be coupled to the motherboard. The volatile RAM may be part of a memory array having a desired memory size based upon the packaging density given currently available memory devices and the specific storage needs. The volatile RAM may be provided, for example, as static random access memory (SRAM), a pseudo-static random access memory (PSRAM) or a dynamic random access memory (DRAM). The particular type of volatile memory included in the memory array may be selected according to a variety of factors including but not limited to cost, reliability and availability. The battery may be provided as one or more rechargeable lithium (Li) cells or alternatively, the battery may be provided as one or more nickel cadmium (NiCd) cells. The particular type and number of cells should be selected to permit a relatively small module size while still being able to provide sufficient power to the memory array such that the volatile RAM retains data for a predetermined time period.
The non-volatile memory module may be employed within a sub-system controller. In the event a line voltage on the sub-system controller decreases below a predetermined threshold voltage, the switch couples the battery to the memory array thereby substituting the battery power for the normal power supply. Thus data and parity information remain stored in the volatile RAM of the memory array until the information can be successfully written from the volatile RAM to the disk drive thereby avoiding any loss of information.
By providing the memory module as a single in-line memory module (SIMM), the memory module may be rapidly installed on or removed from the sub-system controller. If the sub-system controller fails, the NVSIMM can be removed from the failed controller and installed on a replacement controller. Thus, the user can quickly resume system operation without loss of data.
This avoids the necessity of performing a so-called system reload, which usually results in a loss of data and which is typically required after a disk storage sub-system failure. The time required to perform a system reload is generally between several hours and several days. Thus, the non-volatile memory module minimizes the amount of system downtime in the event of a sub-system controller failure.
The battery cells are charged by the charging circuit. The battery capacity is selected in conjunction with the power requirements of the volatile RAM such that the volatile RAM retains data for a predetermined period of time, for example thirty days. A larger battery may, of course, be used with a resultant greater data retention period. By providing the memory module as a SIMM, the memory module may be used as a drop in replacement for a conventional SIMM which does not include the data retention characteristics of the present invention.
The memory module of the present invention, however, significantly increases the data integrity of the disk storage sub-system in the event the sub-system controller fails. Moreover, the present invention also provides several additional advantages including an unlimited number of read/write cycles, low power consumption, the use of low cost volatile memory, and high speed reads and writes.
In accordance with a further aspect of the present invention, a non-volatile single in-line memory module (NVSIMM) includes an array of static random access memory (SRAM) integrated circuits disposed on a printed circuit board fabricated in compliance with industry-standard specifications for a single in-line memory module (SIMM). The NVSIMM further includes a battery circuit coupled to the SRAM array and a charging circuit coupled to the battery circuit. With this particular arrangement, an NVSIMM is capable of surviving spontaneous loss of system power for an extended period of time without loss of data stored in the SRAM array. In one application, the NVSIMM may be provided as a memory module which is physically and electrically interchangeable with a volatile SIMM having a DRAM array disposed thereon. By providing the memory module with a conventional SIMM form factor and a connector, a modular, removable, high density memory array which is easily connected to a supporting circuit board (motherboard) is provided. Thus the NVSIMM may be replaced, reconfigured, upgraded and/or migrated to other disk storage sub-systems.
The battery circuit includes a rechargeable battery and associated charging, voltage monitoring and supply switching circuitry. The battery circuit is selectively coupled to the SRAM array via the switching circuitry. The battery provides a dedicated source of standby power for the SRAM array. Thus, when system power is unavailable to the NVSIMM, the switching circuitry couples the battery circuit to the SRAM array and the SRAM array is able to maintain data integrity during power interruptions. The battery should be selected to have compatible characteristics with the low standby current and the minimum retention voltage requirements of the SRAM array. The rechargeable battery may be provided, for example, as a lithium battery having a high energy density. The charging requirements, high cell voltage, wide thermal operating range, and low self-discharge characteristic favor the use of lithium batteries on the NVSIMM module although other battery types may be employed.
The NVSIMM further includes a voltage monitor circuit coupled between the system power supply and the SRAM array. The voltage monitor circuit detects power fluctuations and protects the SRAM array from spurious access attempts during such power fluctuations. Thus since spurious access attempts are precluded by the voltage monitor circuit, the SRAM array provides a reliable technique for maintaining data integrity. Moreover, the back up process is self-initiated. That is, the memory module need not receive notification of impending power interruption from the disk storage sub-system controller or any other external system prior to initiating the back up power mode. Furthermore, the NVSIMM is totally passive; i.e. the NVSIMM does not require any clocks, state machines, voltage translation circuitry or memory refresh circuitry. Thus, the NVSIMM backs up data in a highly reliable manner, without external controls.
The NVSIMM further includes a battery voltage monitoring circuit for providing a signal indicative of battery state-of-charge. The NVSIMM also includes a signal buffering circuit for reducing the incremental loading presented by the NVSIMM to the motherboard on which it is installed. The NVSIMM thus increases data integrity and facilitates service of the host disk controller when included on such a controller. A plurality of NVSIMM modules may be configured as high speed storage in a non-volatile write-through write cache which is architecturally located in a data path between a host port and a back-end disk drive port on the sub-system controller. The write cache stores host-written data blocks and associated controller-generated parity blocks until these blocks are successfully written to the disk drive. The ability to retain host data in the write cache through power interruptions allows the sub-system controller to acknowledge a host write operation as complete at a much earlier point in the write translation, and in particular, before the data is actually stored on the magnetic media. This increases the aggregate host write bandwidth. Since the NVSIMM is removable and retains data in the SRAM array even during a power loss, write data stored on the NVSIMM can survive a loss of power on the sub-system controller. The NVSIMM modules can then be removed from the failed sub-system controller and installed in a replacement controller.
As mentioned above, in one application the printed circuit board and SRAM memory array may be provided as mechanically and electrically interchangeable with existing volatile SIMM-based DRAM arrays of the type commonly used in state of the art direct access storage device (DASD) controllers. Thus, the NVSIMM appears, to the DASD controller, to be a conventional volatile SIMM having a DRAM array disposed thereon.
The NVSIMM provides a three-bit identification code to the sub-system controller. The code identifies the module type, (e.g. NVSIMM), module memory capacity and module battery status (e.g. battery voltage below a predetermined nominal voltage level). The NVSIMM operates as a volatile SRAM array if the battery is removed, shorted, discharged or dead. A full battery charge may typically be accomplished in the range of about 40 to 60 hours. Useful battery capacity, however, is restored typically in under ten hours. In one embodiment, the battery charger circuit may be provided as a constant voltage circuit which charges the battery, if necessary, whenever system power is present.

BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing features of this invention as well as the invention itself may be more fully understood from the following detailed description of the drawings in which:
FIG. 1 is a block diagram of a disk storage sub-system including a memory array having a non-volatile memory circuit;
FIG. 2.is a block diagram of a non-volatile memory circuit;
FIG. 3 is a schematic diagram of a non-volatile memory circuit;
FIG. 3A. is a schematic diagram of a battery voltage monitoring circuit;
FIG. 4 is a top view of a non-volatile single in-line memory module;
FIG. 4A is a bottom view of the non-volatile single in-line memory module shown in FIG. 4; and
FIG. 5A-5B are schematic diagram of a battery charging and control circuit.

DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIG. 1, a disk storage sub-system 10 which includes a sub-system controller 12, for controlling the timing and data management on storage sub-system 10. Sub-system controller 12 may include, for example, a microprocessor and associated memory and interrupt generator circuits.
A host interface circuit 18 has a first port 18a coupled to sub-system controller 12, a second port 18b for coupling to a host processor (not shown) and a third port 18c coupled to a control logic circuit 20 at a first control logic port 20a. Address, data and control signals are provided to port 18a while ports 18b, 18c accommodate signals related to data movement of read/write data. Port 18b may be provided, for example, as a SCSI or IPI or any other type of interface adapted to handle control, data and/or address information. Port 18c is adapted to handle signals having control and/or data components.
A second port 20b of control logic circuit 20 is coupled to sub-system controller 12 via a bus 22 and a third port 20c of control logic circuit 20 is coupled via a bus 24 to a drive interface circuit 26 at a first port 26a. A second port 26b of drive interface circuit 26 is coupled to sub-system controller 12 and a third port 26c of drive interface circuit 26 is coupled through a system bus 27 to a disk drive 28. Disk drive 28 is here shown to include a redundant array of inexpensive disks 28a-28N. Thus in this particular embodiment sub-system 10 corresponds to a RAID disk storage sub-system. The NVSIMM is particularly suitable for use in a write cache of a disk system.
A memory array 30 is coupled to control logic circuit 20 via a bus 31. Memory array 30 includes a plurality of non-volatile memory modules 32a-32N generally denoted 32 and an optional dynamic random access memory module (DRAM) 34. As will be described in more detail below in conjunction with FIGS. 2-5B, each of the non-volatile memory modules 32 includes at least one volatile memory device. The control logic circuit 20 receives data and address signals from sub-system controller 12 and in response thereto directs the movement of data between particular address locations in memory array 30 and host and drive interface circuits 18 and 26.
Memory array 30 is provided as a write-through write cache memory disposed between host interface 18 and disk drive interface 26. Non-volatile memory modules 32 thus store host-written data blocks and associated parity blocks generated by sub-system controller 12. The non-volatile memory modules 32 store the data and parity information in the volatile memory devices until these blocks are written to disk drive 28. When the data and parity information are written across all of the disk drives 28a-28N in a so-called striping technique, disk-storage sub-system 10 is operating as a RAID-5 disk storage sub-system.
As will also be described in detail below in conjunction with FIGS. 2-5B, non-volatile memory modules 32 receive system power via sub-system controller 12. Memory modules 32 also includes a stand alone power source independent of sub-system controller 12. Thus, memory modules 32 are able to retain host data in the volatile memory devices even if power is not supplied thereto by sub-system controller 12.
The ability to retain host data in memory modules 32 allows sub-system controller 12 to acknowledge host write operations as complete before the data is actually stored on disk drive 28. Since memory modules 32 retain data therein if power to sub-system controller 12 is lost or if sub-system controller 12 fails, memory modules 32 can be physically removed from the failed sub-system controller and re-installed in a replacement sub-system controller. Thus in the event of system power loss or failure of sub-system controller 12, memory modules 32 preserve the data integrity of the disk-storage sub-system 10.
Referring now to FIG. 2, a non-volatile memory circuit 35 which may be of the type used in sub-system 10 described above in conjunction with FIG. 1, includes an address buffer 36 having a first port 36a coupled to a plurality of address lines generally denoted 38. A second port 36b of address buffer 36 is coupled to a volatile memory array 40 at a first port 40a. Address buffer 36 may accept any desired number of address lines. In the present example 20 address lines are employed. Volatile memory array 40 may be provided for example as an array of static random access memories (SRAMs), an array of a pseudo-static random access memories (PSRAMs) or as an array of dynamic random access memories (DRAM). In some applications, it may be desirable for memory array 40 to include more than one of the memory types mentioned above.
A plurality of data lines 42 are coupled to a data buffer 44 at a first port 44a. A second port 44b of data buffer 44 is coupled to an input port 40b of volatile memory array 40.
A plurality of control lines 46 are coupled to a control buffer 48 at a first port 48a. A second port 48b of control buffer 48 is coupled along a signal path 50 to a third port 40c of volatile memory array 40. Signal path 50 is also coupled to a control circuit 52.
A system voltage V.sub.SIMM.sbsb.--.sub.VCC is also coupled to the control circuit 52 via a signal path 53. Control circuit 52 includes a voltage detection circuit which determines whether the system voltage V.sub.SIMM.sbsb.--.sub.VCC is above or below a predetermined threshold. Control circuit 52 also includes switching circuits to perform switching functions. The switching circuits of control circuit 52 receive control signals from the detection circuit. The control signals take on values indicative of the voltage level of the system voltage V.sub.SIMM.sbsb.--.sub.VCC. When the system voltage V.sub.SIMM.sbsb.--.sub.VCC falls below a predetermined threshold voltage, the switching circuits of control circuit 52 decouple the volatile memory array 40 from the system voltage V.sub.SIMM.sbsb.--.sub.VCC and couple the battery 59 to the volatile memory array 40 to thus provide battery voltage to the memory array 40.
Thus, the control circuit 52 includes switching circuitry to couple one of a plurality of voltage sources to the volatile memory array. Control circuit 52 also includes switching circuitry to switch a supply voltage to the SIMM card, to thus control voltage provided to the SIMM module itself. The control circuit 52 further includes switching circuitry to charge the battery, when instructed to do by the charging circuit 56.
It should also be noted that when memory array 40 is provided as a PSRAM, sub-system controller 12 (FIG.1) implements a refresh cycle in the PSRAM to save data stored therein. To place the PSRAM in a refresh cycle mode sub-system controller 12 sends a signal to control circuit 52. Thus, the PSRAM may be placed in either a standby mode or a refresh cycle mode via sub-system controller 12 and control circuit 52.
Control circuit 52 is coupled via signal path 54 to a charging circuit 56 and charging circuit 56 is coupled via signal path 57 to the battery circuit 58. Charging circuit 56 monitors the voltage level of the battery 59 and provides charge control signals to control circuit 52 to ensure that battery 59 is able to provide sufficient voltage to memory array 40 such that memory array 40 is able to reliably retain information stored therein when memory array 40 is powered by the battery 59.
As will be described further below in conjunction with FIGS. 3-5B, battery circuit 58 includes a battery 59 and switch circuitry. Battery 59 may be coupled to memory array 40 via the switch circuitry of battery circuit 58. Battery 59 provides a battery voltage to memory array 40 when memory array 40 is coupled thereto. Battery 59 is coupled to memory array 40, for example, when the system voltage V.sub.SIMM.sbsb.--.sub.VCC is below an established threshold.
An optional temperature monitor circuit 60 is coupled to charging circuit 56. Temperature monitor circuit 60 should preferably be used when battery circuit 58 includes Nickel-Cadmium (NiCd) battery cells. NiCd batteries should not be charged outside a particular temperature range. Thus, temperature monitor circuit 60 prevents charging circuit 56 from providing a charging current signal to battery circuit 58 outside a predetermined temperature range.
It should be noted that if the operating temperature range of battery 59 is within the operating temperature range of memory circuit 35, temperature monitor circuit 60 may be omitted from memory circuit 35.
If temperature monitor circuit 60 is included in circuit 35, charging circuit 56 receives both a temperature sense signal from the temperature monitor circuit 60 and a voltage level sense signal from control circuit 52. Thus, control circuit 52 provides signals to charging circuit 56 and also receives signals from charging circuit 56 to either allow charging or not allow charging based on the level of the V.sub.SIMM.sbsb.--.sub.VCC voltage and the battery temperature.
In a first embodiment, referring to FIG. 3, a non-volatile memory circuit 62 includes a connector 64 through which are fed a plurality of data lines 66a-66M generally denoted 66, a plurality of address lines 68a-68N generally denoted 68, a plurality of control lines 70a-70d, generally denoted 70, a system voltage supply line 72 and a SEAL signal line 74. Data lines 66 are coupled through connector 64 to a first port 76a of a buffer circuit 76. Buffer circuit 76 includes a plurality of data buffers 78a-78Q. Data buffers 78a-78Q are coupled at data buffer port 76b to a volatile memory array (not shown). A data bus is coupled between data buffer port 76b and a memory array which may be similar to memory array 40 (FIG. 2) to carry data to or from memory array 40.
Similarly, address lines 68 are coupled through connector 64 to a corresponding plurality of input ports 80a-80N of an address multiplexer 81. A like plurality of output ports 82a-82N of address multiplexer 81 are coupled via a bus 84 to corresponding address lines of the volatile memory array.
Address signals are provided from sub-system controller 12 (FIG. 1) to input ports 68a-68N of connector 64. The addresses may be provided as a time multiplexed address. Thus, the first ten address bits are delivered to multiplexer input ports 80a-80N and a predetermined period of time later the second ten address bits are delivered.
The first ten address bits typically correspond to the row address and are latched into address multiplexer 81 by a row address strobe signal (RAS) fed into circuit 62 on input port 70a. The second ten bits typically corresponding to the column address are latched into address multiplexer 81 by a column address strobe signal (CAS) fed into circuit 62 on input port 70c. In this particular embodiment, the second ten bits are latched into address multiplexer 81 via the row address strobe delayed signal (RASD) fed into circuit 62 on port 70b. The time between latching the first and second ten bits in multiplexer 81 is based upon the access time of the memory as well as set up and pulse width requirements which determine the minimum delay time between address assertions, etc.
For example, in some applications it may be advantageous for non-volatile memory circuit 62 to emulate or mimic a DRAM SIMM. A DRAM typically has an access time of about 60-70 nanoseconds (nsec) and also has a set up time to accommodate pulse width requirements. In this example sub-system controller 12 provides timing signals compatible with a DRAM. Consequently, the row and column information is received based on the timing requirements of a DRAM. Thus, memory circuit 62 would accept the timing signals for a dram provided by sub-system controller 12 even though memory circuit 62 may not include any DRAMs.
In an alternate embodiment, sub-system controller 12 may provide timing signals compatible with an SRAM. In this case all twenty address bits may be provided to the SRAM in parallel rather than in first and second ten bit segments.
Address bus 84 is also coupled to an input port 86a of a control circuit 86 such that the high order three bits of the address on bus 84 are coupled into control circuit 86. Control circuit 86 includes a three to eight line decoder circuit 87. Decoder circuit 87 decodes the three address bits fed thereto into one of eight unique output signals and provides a corresponding signal on one of a plurality of chip enable signal ports CE0-CE7. Thus, the high order three bits coupled from address bus 84 define which memory bank of a plurality of memory banks is being addressed at any given time. Although here decoder circuit 87 can enable at most eight memory banks, those of ordinary skill in the art will recognize that the memory array could include fewer or more than eight memory banks. If the memory array includes more than eight memory banks a larger number of bits for the purpose of bank selection must be provided. Thus, in this event, decoder circuit 87 may be provided for example as a four to sixteen line decoder, assuming of course that the memory array has no more than sixteen memory banks.
Each of the output lines of decoder 87 are coupled to one of a plurality of control circuit output ports through a corresponding one of a plurality of series resistors 88 as shown. Series resistors 88 aid in decreasing the rate of change of the signal to thus improve signal quality by, for example, reducing the amount of undershoot and overshoot of the signals.
Each of the output signal lines of decoder circuit 87 is coupled to a pull up resistor in a resistor bank 89. Pull up resistors 89 have a first terminal coupled to a nonvolatile voltage V.sub.NV.sbsb.--.sub.VCCA provided by a battery 59 (FIG. 2) rather than to a system voltage V.sub.cc provided by a system voltage supply via input port 72. Consequently, when circuit 62 operates in a back up mode and system voltage V.sub.CC is not available, resistors 89 are coupled to a back up power source which provides non-volatile voltage V.sub.NV.sbsb.--.sub.VCCA and assures that the chip enable signals CE0-CE7 are pulled high during back up mode to thus reduce the current requirements of the SRAM array.
As mentioned above, control lines 70a-70d couple the RAS, RASD, CAS and write-enable WE signals to a corresponding plurality of input ports 90a-90d of a control circuit 90. Control circuit 90 includes an inverting buffer circuit 92 and a plurality of logic circuits 94-108. Logic circuits 94-108 are provided as either NAND gates or NOR gates. Those of ordinary skill in the art will recognize of course that the function of control circuit 90 can be achieved using any type of appropriate logic circuitry. Control circuit 90 provides at output port 90a a row latch signal RLAT which corresponds to the logical OR of the RAS and the RASD signals.
The RLAT signal latches the column address in address multiplexer 81 and holds it unchanged for the duration of the access cycle. Thus, the column address component of address multiplexer 81 is transparent until the RLAT signal asserts at which time the multiplexer contents are held unchanged and are unaffected by signals on input ports 80a-80N.
The contents of multiplexer 81 remain stable to thus provide the SRAM array a stable address until the cycle is terminated and the RASD signal goes away at which time multiplexer 81 again accepts address input signals at input ports 80a-80N.
A pair of output enable signals OE.sub.-- A and OE.sub.-- B provided at logic circuit output ports 90b, 90c enable memory array driver circuits. Thus, during a read cycle when data is being read from the memory array, signals OE.sub.-- A and OE.sub.-- B activate the SRAM driver circuits.
The output enable signals OE.sub.-- A and OE.sub.-- B are functionally identical, however, two signals are used for reasons of drive capability. That is, it is undesirable to couple an excessive number of inputs to a single signal, thus two signals are here used. Thus one-half of the memory array is coupled to a first one of the output enable signals (e.g. OE.sub.-- A) and the other half of the memory array is coupled to a second one of the output enable signals (e.g. OE.sub.-- B).
A pair of write enable signals WE.sub.-- A and WE.sub.-- B are provided at logic circuit output ports 90d, 90e. In a manner similar to output enable signals OE.sub.-- A, OE.sub.-- B, write enable signals WE.sub.-- A, WE.sub.-- B each drive one-half of the memory array.
Output enable signals OE.sub.-- A, OE.sub.-- B are asserted only during a read cycle and conversely write enable signals WE.sub.-- A, WE.sub.-- B are asserted only during a write cycle. Buffer circuit 92 receives a signal on one of a plurality of input ports 92a-92h and provides an inverted signal on a corresponding one of a plurality of output ports 93a-93h.
Logic circuits 96, 98 are provided as NAND gates and receive at first input ports 96a, 98a the RAS signal from output port 93b of inverter 92. NAND gate 96 receives at a second input port 96b the CAS signal. NAND gate 98 receives at a second input port 98b the write enable signal WE. The RAS signal indicates that an access cycle is presently occurring and that a subsequent CAS or WE signal should be used in this cycle. Thus the presence of the RAS signal indicates that the CAS or write enable WE signal is valid.
In the presently disclosed embodiment, the CAS signal is de-asserted only during read cycles and the write enable signal WE is de-asserted only during write cycles. Thus the signals provided by logic gates 96, 98 are mutually exclusive signals and thus output enable signals OE.sub.-- A, OE.sub.-- B and write enable signals WE.sub.-- A and WE.sub.-- B are mutually exclusive pairs of signals.
The signals coupled between control circuit output ports 90f, 90g and data buffer ports 76c, 76d are used to control the data transceivers that either receive data from sub-system controller 12 or deliver data to sub-system controller 12 depending on whether a read or write cycle is being executed.
Buffer circuit 76 has a pair of ports 76c, 76d. Port 76c corresponds to a direction port DIR which alerts data buffer 76 the direction in which data is flowing. Port 76d corresponds to an enable port EN which determines when to actually turn on the driver circuit in the selected direction.
Logic circuits 100-108 provide a direction signal DIR and an enable signal EN to control ports 76c, 76d of data buffer 76. The direction and enable signals DIR, EN are provided in the following manner. Logic circuit 100 is provided as a NAND gate and receives the RAS signal on a first input port thereof. A second input port of NAND gate 100 is coupled to an output port of logic circuit 102 which is provided as a NOR gate
NOR gate 102 has a first input port coupled to the output port of NAND gate 100. A second input port of NOR gate 102 is coupled to the output port of NAND gate 98. Thus, when the RAS and WE signals are present at the input ports of NAND gate 98, NOR gate 102 receives a write signal WR at the second input port.
The output port of NOR gate 102 is coupled to a first input port of a NAND gate 104. A second input port of NAND gate 104 is coupled to ground. Thus NAND gate 104 provides a logic one signal to first input ports of NOR gates 106, 108. The output of NOR gate 108 is coupled to input port 76d of buffer circuit 76. Thus NOR gate 108 sources the enable signal EN to buffer circuit 76.
The output of NOR gate 106 is coupled to input port 92h of inverter circuit 92. Output port 93h of inverter 92 is coupled to input port 76c of buffer circuit 76. Thus, logic circuits 96-108 decode the direction signal and inverter 92 provides a direction signal DIR to input port 76c of data buffer 76.
Thus logic circuit 90 decodes the control signals RAS, RASD, CAS and WE provided by sub-system controller 12 (FIG. 1) and provides direction and enable signals DIR, EN to data buffer 76.
Logic circuit 90 also extends the enable signal EN such that the output enable signal EN is asserted for the full cycle. This is accomplished by NAND gate 100 and NOR gate 102 performing a sample and hold function on the enable signal EN. During a write cycle when NAND gate 98 initially provides a signal having a logic level one to the input port of NOR gate 102 the output enable EN signal is activated. A predetermined period of time later the write enable signal WE is no longer present at the input port of NAND gate 98.
However, even after the write enable signal WE is no longer present, NAND gate 100 continues to provide a signal to the second input port of NOR gate 102. This causes the output enable signal EN to be provided to data buffer port 76d until the RAS signal is removed from the first input port of NAND gate 100. Thus, the enable signal EN cannot be asserted until the write enable signal WE is provided, however, when the write enable signal WE is de-asserted the output enable signal EN remains present until the RAS signal is removed.
Thus, logic circuits 100, 102 perform both a decoding function and a timing function by stretching the cycle of the output enable signal EN beyond the cycle of the write enable signal WE. This technique guarantees that data from the memory array is not removed before sub-system controller 12 instructs the memory array to write the data.
Supply voltage V.sub.CC is coupled from input port 72 to an input port 110a of a voltage monitor circuit 110. Voltage monitor circuit 110 monitors the level of system supply voltage V.sub.CC. If the voltage level of supply voltage V.sub.CC falls below a predetermined threshold level, voltage monitor 110 provides at an output port 110b an output signal PFAIL. Signal PFAIL is coupled to an input port 86b of decoder 86. When decoder circuit 86 receives signal PFAIL at terminal 86b, decoder 86 de-asserts each chip enable signal CE0-CE7 and thus prevents any access to the memory array.
Supply voltage V.sub.CC is also coupled to a battery circuit 112 at a first input port 112a. Supply voltage V.sub.CC is coupled through a pair of series resistors 114, 116 to a node 118. A first diode 120 has an anode coupled to node 118 and a cathode coupled to a positive terminal of a battery 122. A second diode 124 here provided as a zener diode has a cathode coupled to node 118 and an anode coupled to a negative terminal of battery 122 and to ground. Resistors 114, 116 and diodes 120, 124 form a battery charging circuit which provides a charge current to battery 122.
Battery circuit 112 is coupled through a resistor 126 to a battery switching circuit 130. Resistor 128 is provided as a pull down resistor for the SEAL signal. Battery switching circuit 130 here includes a pair of switching circuits 132, 134. Switching circuits 132, 134 may be provided, for example, as the type manufactured by Maxim corporation and identified as part number MAX1259. Those of ordinary skill in the art will recognized of course that any equivalent electronic switching device may also be used.
Resistor 126 has a first terminal coupled to the positive terminal of battery 122 and a second terminal coupled to an input port of battery switching circuit 130. Resistor 126 is disposed such that if any circuit component fails (e.g. short circuits) resistor 126 limits the amount of current which may be provided to battery 122. Thus, if switching circuit 132 or 134 fails and provides a low impedance path between the terminals 132a, 132b or 134a, 134b, battery 122 will not be directly connected to the supply voltage V.sub.CC. Rather resistor 126 acts as a current limiting resistor in series between the supply voltage V.sub.CC and the positive terminal of battery 122. Resistor 126 thus provides a measure of a safety to avoid an explosion of battery 122 caused by switching circuit 132, 134 failure.
Battery switching circuit 130 has a pair of output ports 130a, 130b which are coupled to a non-volatile memory array (not shown). As will be explained in detail in conjunction with FIGS. 4 and 4A below, each switching circuit 132, 134 is coupled to one-half of memory devices in the non-volatile memory array.
Switches 132, 134 are coupled such that they each receive the same battery input signals and the same supply voltage signal V.sub.CC at the respective input ports 132a, 132b, 134a, 134b thereof. Switches 132 and 134 are each coupled to input port 72 and monitor supply voltage V.sub.CC. When switch circuits 132, 134 sense a drop in supply voltage V.sub.CC, switches 132, 134 couple battery 122 to the memory array and thus provide a non-volatile voltage V.sub.NC.sbsb.--.sub.VCCA, V.sub.NV.sbsb.--.sub.VCCB at output ports 130a, 130b respectively.
Switch 134 also has a second function. When supply voltage signal V.sub.CC falls below a predetermined threshold voltage, switch 134 provides a power fail output signal PF to logic circuit 136.
In this particular embodiment, the predetermined threshold voltage corresponds to a voltage typically of about 1.26 times the battery voltage. The battery voltage here corresponds to about 3.0 volts and thus the threshold voltage corresponds to approximately 3.75 volts. Thus when the system voltage V.sub.CC falls below 3.75 volts, switching circuit 134 asserts a power fail signal PF on signal line 130c. Output port 130c is coupled to an input port of a logic circuit 136.
When the system voltage continues to decay to the level of the battery voltage, V.sub.CC is disconnected from the memory array and the battery circuit 112 provides the source of power to the array through the switches 132, 134. Thus, it should be noted that no external intervention is necessary to cause memory circuit 62 to initiate the power back up mode; the application of back up power being initiated and applied within the memory circuit 62.
A control signal SEAL is coupled to an input port 130d of battery switching circuit 130. When the SEAL signal is applied, the next time supply voltage V.sub.CC is removed, battery 122 will not back up the SRAM array. That is, the back up function provided by battery 122 can be programmably disabled via switch circuit 130 to thus prevent battery discharge before non-volatile memory circuit 62 is placed in an active system. Thus battery 122 is sealed for storage by the SEAL signal.
When the SEAL signal is first asserted, no effect is immediately apparent. However, the affect becomes apparent when supply voltage V.sub.CC is removed and data is not retained in the memory array due to loss of power. Thus, the SEAL signal may be advantageously asserted, for example, after non-volatile memory circuit 62 is tested but before it is shipped to a customer to prevent battery 122 from discharging prior to final installation.
Backup mode is automatically re-enabled upon subsequent restoration of system voltage V.sub.CC. Thus, in a manufacturing environment, the battery on each NVSIMM should be fully charged and the backup function disabled prior to shipment. The minimum shelf life of an unpowered non-volatile memory circuit 62 having the back up function disabled, and thus a disconnected battery, is dependent upon the particular type of battery used and is typically about ten years for a lithium battery.
Many of the circuit components disposed on the motherboard to which memory circuit 62 may be coupled operate reliably only when the components receive at least 4.5 volts. Thus, these circuit components fail to operate predictably whenever the voltage provided thereto drops below 4.5 volts. It is desirable to therefore protect the SRAM array from spurious access attempts which may occur at a voltage level typically at or below approximately 4.5 volts.
Therefore, voltage detection monitor circuit 110 detects if supply voltage V.sub.CC falls below a second predetermined threshold of approximately 4.5 volts. If supply voltage V.sub.CC falls below 4.5 volts, voltage detection circuit 110 provides a PFAIL signal which prevents all access to the volatile memory array.
Voltage detection circuit 110, however, fails to operate below a third predetermined threshold voltage corresponding to approximately 1 volt. Since supply voltage V.sub.CC will eventually reach zero volts it is necessary to maintain the SRAM protection function. Thus battery management circuit 134 provides signal PF when V.sub.CC falls below 3.75 volts.
Thus, voltage detection circuit 110 initially detects the supply voltage V.sub.CC falling below 4.5 volts. Voltage detection circuit 110 then asserts signal PFAIL which is fed to logic circuit 136 to de-assert the four chip enable output signals CE.sub.A -CE.sub.D.
Logic gates 136a-136d are provided as logic AND gates. Thus chip enable signals CE.sub.A -CE.sub.D are asserted when both the PFAIL signal provided by voltage monitor circuit 110 and the PF signal provided by battery management circuit 134 are fed to logic circuit 136. The volatile memory array is thus protected from spurious access attempts which may occur due to the decreasing system supply voltage V.sub.CC.
It should be noted that each of the logic gates 136a-136d are powered by the non-volatile voltage signal V.sub.NV.sbsb.--.sub.VCCB provided at battery switching circuit output port 130b during back up mode. Thus, logic circuit 136 remains powered and active during back up mode.
The supply voltage V.sub.CC is constantly being monitored by monitor circuit 110 and battery switching circuit 130. When the supply voltage V.sub.CC initially decreases, voltage detection circuit 110 first initiates the memory array protection function by providing signal PFAIL. As supply voltage V.sub.CC continues to decrease, battery switching circuit 130 via switch 134 maintains the protection function by asserting the PF signal.
It should be noted that although logic circuit 136 is here coupled to switch 134, logic circuit 136 could alternatively be coupled to switch 132. The additional loading on switch 132 or 134 due to logic circuit 136 should be selected to have a minimal loading effect on switch circuit 130. That is, the loading effect on switch circuit 130 due to logic circuit 136 should preferably be a small percentage of the overall load on switch 130.
It should be noted that in order to guarantee that the SRAMs meet their maximum back-up current requirement specifications, all chip enable signals presented to back up memory array should be de-asserted to within 0.2 volts of their respective rail voltage. If the memory array is provided as an array of SRAMs, previously written data may be retained reliably when the SRAMs are powered by as little as two volts.
Those of ordinary skill in the art will recognize that as technology improves it may be possible that volatile memory devices may retain previously written data with voltages less than two volts.
Referring now to FIG. 3A, a battery voltage monitoring circuit 150 has a battery voltage terminal 150a, a supply voltage terminal 150b, a reference voltage terminal 150c and an output port 150d. A battery voltage V.sub.BATT is coupled through battery voltage terminal 150a to an input port of a comparator 151. A supply voltage V.sub.CC is coupled through supply voltage terminal 150b to a first port 152a of a reference voltage circuit 152. A second port 152b of reference voltage circuit 152 is coupled to a second input port of comparator 151.
Reference voltage circuit 152 includes a first resistor 153 having a first terminal coupled to supply voltage terminal 150b and a second terminal coupled to a cathode of a zener diode 154 at a node 155. An anode of diode 154 is coupled to a first reference potential corresponding to ground.
A second resistor 156 has a first terminal coupled to node 155 and a second terminal coupled to the second input port of comparator 151. A third resistor 157 and a capacitor 158 are coupled between the second terminal of resistor 156 and ground. An output port of comparator 151 is coupled to output port 150d of battery voltage monitoring circuit 150.
Diode 154 establishes through resistor 156, a reference voltage V.sub.REF, at the second input terminal of comparator 151. When the battery voltage V.sub.BATT has fallen below the reference voltage V.sub.REF comparator 151 provides an output signal at port 150d.
The output of battery voltage monitoring circuit 150 is fed to sub-system controller 12 (FIG. 1). This may be accomplished, for example, by coupling port 150d through connector 64 (FIG. 3) to sub-system controller 12. Thus a signal is fed from memory module 62 (FIG. 3) to sub-system controller 12 to indicate the charge status of battery 122. The present battery voltage monitoring circuit is configured to provide at least an 8 hour warning period prior to data retention failure and typically provides a warning period several tens of hours longer than the worst case scenario.
A test voltage V.sub.TEST may be applied to terminal 150c to allow in-circuit test equipment to be used to confirm the proper operation of battery voltage monitoring circuit 150. Voltage V.sub.REF may thus be used to ensure that comparator 151 and diode 154 are working properly.
Referring now to FIGS. 4 and 4A, a non-volatile single in-line memory module (NVSIMM) 160 includes a printed circuit board (PCB) 162 having first and second opposing surfaces 162a (FIG. 4), 162b (FIG. 4A). PCB 162 is preferably fabricated in compliance with industry-standard specifications for a single in-line memory module (SIMM). PCB 162 is provided having on one edge thereof an 80 pin edge-connector 164. Edge-connector 164 is here provided as a vertical edge connector. Those of ordinary skill in the art will recognize of course that non-vertical edge-connectors or any other type of connector may be employed. Thus, NVSIMM 160 is provided as a modular, removable, high density memory array which may be coupled to a supporting circuit board (motherboard) via connector 164. Furthermore, memory module 160 may be easily installed or replaced by a different memory module having more memory, for example. Moreover, by providing memory module 160 as a SIMM, if a sub-system controller fails, memory module 160 may be removed from the failed sub-system controller and installed on a new operable sub-system controller. Thus a user may rapidly resume system operation and avoid any loss of information or the need to perform a system reload.
Disposed on surface 162a is a rechargeable surface mount battery 165. Rechargeable battery 165 may be provided as a 90-100 mAh 3 V coin-cell of the type manufactured by Panasonic and identified as part number Vanadium Pentoxide Lithium VL3032-1F2. Alternatively, battery 165 may be provided as the type manufactured by Sanyo and identified as part number Manganese dioxide Lithium ML2430-TT1.
Also disposed on surface 132a is an array of integrated circuit static random access memory (SRAM) components 166a-166t generally denoted 166. Similarly, disposed on surface 162b is a second array of integrated circuit SRAM components 168a-168t generally denoted 168. Each SRAM array 166, 168 includes twenty 128K.times.8 bit 5 V SRAM IC's arranged as 524,288 thirty-nine bit words (i.e. each array is 2 megabytes). The word width is selected to accommodate a 32-bit data word and an accompanying 7-bit ECC field. Each SRAM 166a-168t may be provided as the type manufactured by Samsung and identified as part number KM681000ALT-7L, or as part number HM628128LT-7L manufactured by Hitachi or as part number UPD 31000AGZ-7OLL manufactured by NEC or any other suitable device. The NVSIMM 160 presently includes 2 Megabytes (MB) or 4MB of SRAM memory however, any desired capacity may be employed within the limits of current memory IC capacities.
Thus, in this particular embodiment, NVSIMM 160 includes forty SRAM components disposed on printed circuit board 162. It should be noted that although forty SRAM components are disposed on printed circuit board 162, the particular number of SRAM components which are disposed on PCB 162 is selected in accordance with a variety of factors including but not limited to the overall package size of PCB 162, the amount of memory provided by each SRAM array 166, 168 and the amount of memory required in the system in which NVSIMM 160 is to be employed. Battery 165 provides power to SRAM arrays 166, 168 during periods of power loss.
Coupled between battery 165 and SRAMs 166, 168 are a pair of battery management circuits 170a, 170b generally denoted 170. Battery management circuits 170 monitor a supply voltage fed from a system voltage supply to memory module 160 through connector 164. The battery management circuits 170 may be of the type manufactured by Dallas Semiconductor and identified as part number DS1259S or the type manufactured by Maxim and identified as part number MAX1259CWE. Other battery management circuits having equivalent electrical characteristics may also be used. In the event the system voltage supply fails to provide the supply voltage to memory module 160, battery management circuits 170a, 170b couple battery 165 to SRAMs 166, 168. Thus, battery 165 provides power to SRAM arrays 166, 168 and any information stored in SRAM arrays 166, 168 is thereby preserved.
The forty SRAM components 166, 168 are grouped into eight banks of five SRAMs each. That is, on side 162a of PCB 162, SRAMs 166a-166e provide a first memory bank 172, SRAMs 166f-166j provide a second memory bank 174, SRAMs 166k-166o provide a third memory bank 176 and SRAMs 166p-166t provide a fourth memory bank 178.
Likewise, on side 162b of PCB 162, SRAMs 168a-168e provide a first memory bank 180, SRAMs 168f-168j provide a second memory bank 182, SRAMs 168k-168o provide a third memory bank 184 and SRAMs 168p-168t provide a fourth memory bank 186.
Thus, the first four memory banks 172-178 are disposed on the first or so-called component side 162a of PCB 162 and the second four memory banks 180-184 are disposed on the second or so-called circuit side 132b of PCB 162.
The battery voltage V.sub.NV.sbsb.--.sub.VCCA provided at the output port 130a (FIG. 3) of battery switch circuit 130 (FIG. 3) is coupled to one-half of the circuit components on the component side of PCB 162 and one-half of circuit components on the circuit side of PCB 162. Likewise, battery voltage signal V.sub.NV.sbsb.--.sub.VCCB provided at output port 130b (FIG. 3) of battery switch circuit 130 (FIG. 3) is coupled to one-half the circuit components on the component side 162a of PCB 162 and one-half the circuit components on the circuit side 162b of PCB 162.
For example, battery voltage V.sub.NV.sbsb.--.sub.VCCA may be coupled from battery management circuit 170a to SRAMs 166a-166c in memory bank 172 and also to SRAMs 166f-166h in memory bank 174. Battery voltage V.sub.NV.sbsb.--.sub.VCCB, on the other hand, would be coupled from battery management circuit 170b to SRAMs 166d, 166e in memory bank 172 and also to SRAMs 166i and 166j in memory bank 174. Power is supplied to the memory banks 172-186 in this manner in part due to the electrical characteristics of battery management circuits 170. Specifically, the current flow through battery management circuits 170 should preferably be below a predetermined threshold current in order to ensure that battery management circuits 170 are working within specifications.
When one of the SRAMs 166, 168 are accessed, the amount of current drawn by the SRAM increases substantially. Conversely, when the SRAM is not accessed (i.e. the SRAM is in a so-called standby mode) the current drawn by the SRAM is greatly reduced. Since only one of the memory banks 172-186 may be accessed at any given time, it is desirable to minimize the number of SRAM circuit components 166, 168 which are in active current consumption mode and which are coupled to the same battery management circuit 130a or 130b. Thus, in each SRAM memory bank 172-186, a portion of the SRAM components 166, 168 are powered via battery management circuit 170a and the remainder of the SRAM components are powered via battery management circuit 170b.
Thus, whenever a particular one of memory banks 170-186 is accessed, a first one of the battery management circuits 170a should be coupled to three SRAM components in active mode and seventeen SRAM components in inactive mode. Conversely, a second one of the battery management circuits 170b should be coupled to two SRAM components in active mode and eighteen SRAM components in inactive mode. Thus, five SRAM components each in the same memory bank should be placed in their active mode and the remaining thirty five SRAM components should be placed in their inactive mode. This results in each of the battery management circuits 170a, 170b having a worst case current which is within an acceptable current range of the battery management circuit. Those of ordinary skill in the art will recognize of course that a single battery management circuit could be used if it could source sufficient current for the connected memory devices.
Also disposed on surface 162a are a plurality of data buffer circuits 188a-188e generally denoted 188. Since address and data lines are fed through edge connector 164, address and data buffer circuits 188a-188e are disposed near the edge connector 164.
Data buffer circuits 188 may be provided as the type manufactured by Texas Instruments and identified as part number 74ABT245 or known generically as 74245. Those of ordinary skill in the art will recognize of course that any functionally equivalent part may be employed. In this particular embodiment a 40 bit bus is coupled between data buffers 188 and SRAM arrays 166, 168. However as mentioned above only 39 bits are used for data and the error correction code.
An address multiplexer 190 may be provided, for example, as the type manufactured by Texas Instruments and identified as part number 74ABT162260 is disposed on surface 162a. Those of ordinary skill in the art will recognized of course that any part having equivalent functional and electrical characteristics may also be used. Output signal lines of multiplexer 190 are coupled to an N bit address bus which is coupled to SRAM arrays 166, 168.
A battery voltage monitoring circuit 192 which may be similar to circuit 150 described above in conjunction with FIG. 3A, is disposed on component side 132a of PCB 132. The battery voltage monitoring circuit 192 monitors the battery voltage and provides a battery status signal to the sub-system controller via connector 164 to indicate the charge state of battery 165.
A monitor circuit 194 is disposed on side 162b of PCB 162. Monitor circuit 194 is coupled to the supply voltage provided to memory module 160 from the system voltage supply and operates in a manner similar to monitor circuit 110 described above in conjunction with FIG. 3. Monitor circuit 194 may be provided as the type manufactured by Dallas Semiconductor and identified as part number DS1233. Those of ordinary skill in the art will recognize of course that any circuit capable of detecting a change in the voltage level of a supply voltage and providing an output signal in response thereto may also be used.
In an alternative embodiment employing NiCd cells, and referring to FIG. 5A-5B, a battery circuit 200 includes a battery 202 which includes a plurality of voltage cells 203a-203c each of which corresponds to a nickel cadmium (NiCd) 1.2 volt (V) cell. Those of ordinary skill in the art will recognize of course that the particular type of cell, the number of cells and the voltage level of each cell may be selected to satisfy particular application requirements including but not limited to the overall voltage which must be supplied by battery 202 as well as the form factor of the battery 202.
Battery 202 provides a voltage V.sub.BATT at an output terminal 202a. Output battery terminal 202a is coupled to a charge circuit 204 at first and second terminals 204a, 204b and 204c. Charge circuit 204 includes a charge control circuit 208 which may be provided as an integrated circuit. For example, charge control circuit 208 may be provided as the type manufactured by Integrated Circuit Systems, Inc. and identified as part number ICS 1700.
In brief overview, the charge control circuit 208 initiates battery charge and discharge cycles by providing a periodic series of logic level output signals, some of which initiate a battery charge cycle and some of which initiate a battery discharge cycle. The charge and discharge signals are separated by rest periods during which time the battery 202 is neither being charged nor discharged, but monitored for its cell voltage.
The periodic charge and discharge cycles are provided to optimize the charge and performance of the NiCd battery. That is, the NiCd battery 202 should be charged for period of time, allowed to rest for a period of time and then discharged for a relatively small period of time. This sequence is repeated by the charge control circuit 208. Thus, suffice it to say that the charge control circuit 208 controls the operation of the charging circuit 204.
The charge control circuit 208 has two operating modes. A first or high charge operating mode is used when the charge control circuit 208 is charging the battery 202 at a high rate. Thus in the first operating mode, the time period in between the charge and discharge cycles is relatively small. In the high charge mode, when the battery 202 is depleted, the battery 202 can be fully charged in thirty minutes.
A second operating mode of the charge control circuit 208 is generally referred to as a maintenance mode. In the maintenance mode, the time period between the charge and discharge signals is longer than in the high charge mode. Thus, the charge control circuit 208 continuously charges the battery 202, however, once the battery 202 is determined to be fully charged the charge control circuit 208 will enter the maintenance mode in which the charge control circuit 208 alters the charge and discharge cycles.
The charge control circuit 208 stops charging the battery 202 if any one of several conditions occur. For example, the charge control circuit 208 stops charging the battery 202 or automatically switches into the maintenance mode if (a) the charge control circuit 208 determines that the battery 202 is fully charged; or (b) the charge control circuit 208 stops charging the battery 202 if the battery temperature falls outside of a predetermined temperature range determined by a temperature monitor circuit 224. In addition to the above, the charge control circuit 208 stops charging the battery 202 if the charge control circuit 208 is placed in a reset mode or if the voltage level V.sub.CC falls below a predetermined threshold.
In the present embodiment, the charge control circuit 208 stops charging the battery 202 by providing the logic level output signals having a voltage level corresponding to a logic level 0. For example, when the temperature about battery 202 is outside the predetermined temperature range the charge control circuit output signals which are TTL logic signals are placed at logic level 0.
In addition to the charge control circuit 208, the charge circuit 204 also includes a charging transistor 214 having a first terminal 214a coupled to a node 213, a second terminal 214b coupled to a first terminal of a resistor R1 and a third terminal coupled through a resistor R214 to an output port 216d of a switch control circuit 216. A second terminal of the resistor R1 is coupled to the battery terminal 202a and to a first terminal of a resistor R2. A second terminal of the resistor R2 is coupled to a zener diode D1 as shown. The resistor R2 and the zener diode D1 are appropriately selected having values such that in the event that the voltage V.sub.CC rises above a predetermined voltage level the zener diode D1 will conduct and thus protect the battery 202 from being exposed to an excessive voltage.
When charge circuit 204 is in a charge mode, transistor 214 couples a voltage at node 213 to the first terminal of the resistor R1 and the battery 202 is charged by a current provided through the resistor R1. Thus, the resistance value of the resistor R1 is selected such that in the charge mode a predetermined current flows to the battery 202.
It should be noted that although the charge control circuit 208 controls the charge and discharge cycles, the charge level in terms of current is determined by the user. In this particular embodiment, the resistance value of a resistor R1 determines the charge current level in conjunction with the battery voltage. If the resistor R1 is provided having a relatively small resistance value then a high current flows into the battery 202. However, if the resistor R1 is provided having a relatively large resistance value, then a relatively low current is provided to the battery 202.
Charge circuit 204 further includes a discharge signal path provided by a discharge transistor 222 having a first terminal 222a coupled to battery terminal 202a, a second terminal 222b coupled to a first terminal of a termination 223 and a third terminal 222C coupled through a resistor R222 to an output port 216e of the switch control circuit 216. The termination 223 includes a plurality of resistors 223a-223e having resistance values selected to discharge a predetermined amount of current based upon the operating mode of the charge control circuit 208.
When charge circuit 204 is in a discharge mode, the transistor 222 provides a discharge signal path between battery terminal 202a and ground through the resistor network 223. The discharge signal path is needed since, as mentioned above, the charge control circuit 208 employs an algorithm having a charge and a discharge cycle and thus charge control circuit 208 periodically discharges the battery 202 for a short amount of time.
As mentioned above, the NiCd cells 203a-203c are charged continuously by the charging circuit 204 and can be fully recharged from a discharge condition in 30 minutes. It will be appreciated of course that the charging time is dependent upon the resistance value of resistor R1. In some applications it may be desirable to provide resistor R1 having a value which results in a battery recharge time of as along as 24 hours.
When battery circuit 200 operates in a battery back-up mode a transistor 205 couples the battery voltage V.sub.BATT to a volatile memory array (not shown). The battery 202 provides the voltage to the memory array for a pre-determined period during which the memory array can retain the information stored therein. The predetermined period of time depends upon a variety of factors including but not limited to the size of the memory array. For example, in the present embodiment the battery voltage is sufficient to provide a minimum of 30 days of data retention for 2 megabytes (MB) of pseudo static RAM (PSRAM). That is, when the volatile memory array is provided as PSRAM, the standby power requirement of the PSRAM are such that battery 202 can power the PSRAMs for approximately 30 days. A larger battery may of course also be used in which case, the PSRAM memory array could maintain data for more than thirty days.
The length of data retention time will depend upon a variety of factors including but not limited to memory size and type, battery size and type and temperature. In some applications it may be desirable to provide a minimum of 15 days of data retention for 4 MB of PSRAM or alternatively, it may be desirable to provide one week of data retention for 8 MB of PSRAM.
A pair of resistors R100 and R102 are coupled input terminals 208a, 208b of the charge control circuit 208. The resistance values of resistors R100 and R102 notify the charge control circuit 208 the rate at which the charge control circuit 208 will operate to charge the battery 202. In the present embodiment, the resistors R100, R102 are provided having resistance values which indicate that the charge control circuit 208 is in the high charge mode. This mode is related to the time of charging and is unrelated to the maintenance charge or the hard charge operations described above. Thus the resistors R100, R102, notify the charge control circuit 208 the rate at which the battery 202 is being charged. There are four different charging rates available as mentioned above and in the present embodiment, the battery 202 is being charged at the high charge rate such that the battery 202 can be rapidly re-charged. Those of ordinary skill in the art will recognize of course that in some applications other charge rates may be preferred.
A capacitor C2 and a diode D2 are coupled as shown to provide a reset circuit which is coupled to a reset port 208c of the charge control circuit 208. The charge control circuit 208 receives the voltage V.sub.CC through the reset circuit.
Charge control circuit 208 receives on an input port 208d a temperature sense input signal from a temperature circuit 224. The charge control circuit 208 monitors the temperature sense signal fed thereto on port 208d via the temperature monitor circuit 224 in accordance with the predetermined algorithm of charge control circuit 208.
The charge control circuit 208 includes an internal oscillator used to generate an internal clock signal. An input terminal 208e of the charge control circuit 208 is coupled through a resistor R104 and a capacitor C4 as shown to the node 213 such that card voltage V.sub.CC is provided to the internal oscillator circuit of charge control circuit 208 to generate the internal clock signal. After charge control circuit 208 receives a reset signal on terminal 208c the charge control circuit 208 uses the internal oscillator to count some predetermined period of time prior to implementing the algorithm.
Charge control circuit 208 at input port 208f monitors the battery voltage V.sub.BATT through a voltage divider circuit which here includes a pair of voltage divider resistors R3, R4 and a noise suppression capacitor C3 coupled as shown. The charging circuit 204 is coupled to the battery terminal 202a through the voltage divider circuit such that charge control circuit 208 can monitor the battery voltage V.sub.BATT. The voltage divider circuit is required because the charge control circuit 208 is intended to examine the voltage from a single battery cell and in the present embodiment, battery 202 includes three cells 203a--203c. The battery voltage V.sub.BATT is monitored at predetermined times in accordance with the battery charging algorithm.
Thus, the charge control circuit 208 monitors a temperature sense input signal at terminal 208d, a card voltage at terminal 208c and a battery voltage at terminal 208f.
The charge control circuit 208 provides on output ports 208g, 208h the logic level output signals V.sub.CHARGE and V.sub.DISCHARGE in accordance with the predetermined algorithm. The charge control circuit output ports 208g, 208h are coupled to input ports 216g, 216h respectively of the switch control circuit 216. Thus the charge control circuit 208 provides the logic level output signals V.sub.CHARGE and V.sub.DISCHARGE to the switch control circuit 216.
The charge control circuit 208 provides a first status signal V.sub.ERROR on an output port 208i and a second status signal V.sub.MODE on an output port 208j. The status signals V.sub.ERROR and V.sub.MODE are coupled to LEDs 236, 236' to provide visual indicators of the status of the circuit 204.
In the present embodiment, switch control circuit 216 is a charge pump and level translation circuit which may, for example, be of the type manufactured by Maxim Corporation and identified as part number Max 620 or Max 621. Those of ordinary skill in the art will recognize of course that any switch control circuit having suitable electrical characteristics may also be used. Switch control circuit 216 receives charge control signals V.sub.CHARGE, V.sub.DISCHARGE from the charge control circuit 208 and also receives on input port 216f a control signal V.sub.RESET from a voltage detect circuit 206.
As mentioned above charge control signals V.sub.CHARGE and V.sub.DISCHARGE are logic level signals. When signal V.sub.CHARGE is provided as a logic high signal (i.e. a logic level 1) the switch control circuit 216 provides a signal to control terminal 214c of charging transistor 214 to thus bias transistor 214 into its conductive state. In its conductive state, transistor 214 provides a low impedance signal path between the card voltage V.sub.CC at node 213 and resistor R1 and thus a current flows to battery 202 thus charging the battery 202.
As also mentioned above, the battery 202 is coupled to the memory array (not shown) through the transistor 205. The battery terminal 202a is also coupled to a first terminal 205a of the transistor 205. A second terminal 205b of transistor 205 is coupled to the volatile random access memory array (not shown) which may be provided for example as a pseudo-static random access memory array (PSRAM). A control terminal 205c of transistor 205 is coupled to a terminal 206b of the detection circuit 206 which may be for example part number LTC 690 as the type manufactured by Linear Technology, Inc. Other detection circuits having equivalent electrical and functional characteristics may of course also be used.
When transistor 205 is biased into its conductive state, the transistor 205 provides a signal path through which the battery voltage V.sub.BATT is coupled to the non-volatile RAM to thus provide the battery voltage V.sub.BATT to the non-volatile RAM in the event that the system voltage V.sub.SIMM.sbsb.--.sub.VCC fails or is otherwise unavailable to the non-volatile RAM. Thus in the event of a system voltage failure, the battery voltage V.sub.BATT is coupled to the PSRAM through the transistor 205.
To prevent a significant voltage drop from occurring when transistor 205 is turned off and transistors 210, 212 are turned on to thus decouple the memory array from the battery voltage and couple the memory array to the system voltage, a capacitor C1 is coupled as shown to store charge and thus maintain the predetermined voltage level for the brief period of time it takes for transistors 210 and 212 to turn on. It is undesirable for the voltage provided to the memory to drop below a predetermined voltage level when switching between the battery voltage V.sub.BATT and system voltage V.sub.SIMM.sbsb.--.sub.VCC and vice-versa. Thus capacitor C1 maintains the voltage while switch 205 is turning off and switches 210 and 212 are turning on and prevents any significant voltage drop from occurring when a change is being made between battery voltage V.sub.BATT and system voltage V.sub.SIMM.sbsb.--.sub.VCC.
It should be noted that the transistor 205 is provided as a logic level P-channel field effect transistor (PFET) while transistors 210, 212 and 214 are provided as N-channel logic level FETs (NFETs) and in particular N-channel MOSFETs. This selection was made since PFETs conduct when the voltage applied to the gate terminal thereof is lower than the input voltage whereas NFETs, on the other hand, conduct when the voltage applied to the gate terminal is greater than the input voltage. Thus, when the card 200 is powered down (i.e. when V.sub.SIMM.sbsb.--.sub.VCC is off) V.sub.RESET is low and the FET 205 will conduct since the drain is at a higher potential than the gate. Those of ordinary skill in the art will recognized of course that other types of FETs and corresponding switching schemes may also be employed.
Transistor 205 is biased into its conductive state in the following manner. An input terminal 206a of detection circuit 206 is coupled to the system voltage V.sub.SIMM.sbsb.--.sub.VCC. Voltage detection circuit 206 includes an internal comparator which measures the voltage level of the system voltage V.sub.SIMM.sbsb.--.sub.VCC. Circuit 206 determines whether or not system voltage V.sub.SIMM.sbsb.--.sub.VCC has reached a predetermined threshold and thus whether the card voltage V.sub.CC can be provided to the remaining circuit components on the battery circuit 200.
When detection circuit 206 senses that system voltage V.sub.SIMM.sbsb.--.sub.VCC is below a predetermined threshold voltage, detection circuit 206 provides a signal V.sub.RESET to control terminal 205c of the transistor 205. In response to the V.sub.RESET signal, transistor 205 provides a low impedance signal path between the battery terminal 202a and the volatile RAM.
The system voltage V.sub.SIMM.sbsb.--.sub.VCC is also directly coupled to a pair of transistors 210, 212 at terminals 210a, 212a respectively. Transistors 210, 212 are here each provided as MOSFET transistors. Transistor 210 has a second terminal 210b coupled to the PSRAM memory array and a third terminal 210c coupled to terminal 216b of the switch control circuit 216 through a resistor R210. When battery circuit 200 operates in a normal mode the system voltage V.sub.SIMM.sbsb.--.sub.VCC is coupled to the memory array through transistor 210.
Transistor 212 has a second terminal 212b coupled to the node 213 and a third terminal 212c coupled through a resistor R212 to the switch control circuit 216 at terminal 216c. The transistor 212 acts as a switch to provide the card voltage V.sub.CC to particular circuitry of the battery circuit 200.
It should be noted that transistor 205 is biased by the battery 202 rather than by the system voltage V.sub.SIMM.sbsb.--.sub.VCC or the card voltage V.sub.CC. This is because it is necessary to power the memory array from the battery 202 when no system or card voltage is present. Thus transistor 205 must remain operational when the system voltage V.sub.SIMM.sbsb.--.sub.VCC is unavailable.
Transistors 210 and 212 on the other hand are coupled to and biased by the system voltage V.sub.SIMM.sbsb.--.sub.VCC and transistor 214 is biased by the card voltage V.sub.CC. It is neither necessary nor desirable to power the transistors 210, 212 or the remaining circuitry of the battery circuit 200 from the battery 202 since this would undesirably drain the battery 202 when the system voltage V.sub.SIMM.sbsb.--.sub.VCC is unavailable.
System voltage V.sub.SIMM.sbsb.--.sub.VCC is also coupled to a power pin 216a of the switch control circuit 216. Thus, switch control circuit 216 directly receives the system voltage V.sub.SIMM.sbsb.--.sub.VCC. Capacitors 218, 219 and 220 are coupled to the switch control circuit 216 as shown and used by the charge pump of switch control circuit 216 to increase the voltage at output ports 216b-216e to a predetermined voltage having a value approximately eleven and one-half volts above the system voltage V.sub.SIMM.sbsb.--.sub.VCC.
Thus, system voltage V.sub.SIMM.sbsb.--.sub.VCC is directly coupled to voltage detect circuit 206, transistors 210, 212 and to switch control circuit 216.
As mentioned above, detection circuit 206 detects whether voltage V.sub.SIMM.sbsb.--.sub.VCC is falling below a predetermined threshold. If voltage V.sub.SIMM.sbsb.--.sub.VCC falls below a predetermined threshold voltage, detection circuit 206 provides the signal V.sub.RESET at output port 206a and signal V.sub.RESET is coupled to input port 216f of switch control circuit 216. In response to the signal V.sub.RESET, switch control circuit 216 provides bias signals on terminals 216b, 216c which bias the transistors 210, 212 into their non-conductive states. In its non-conductive state transistor 210 decouples the non-volatile RAM from the system voltage V.sub.SIMM.sbsb.--.sub.VCC. Similarly in its non-conductive state, transistor 212 prevents the card voltage V.sub.CC from being provided to the circuit components of the circuit 200.
When switch control circuit 216 receives the signal V.sub.CHARGE on input port 216g switch circuit 216 biases transistor 214 into its conductive state and thus, transistor 214 couples the voltage V.sub.CC at node 213 through the resistor R1 to battery terminal 202a.
The battery charge transistor 214 is turned on and off via the switch control circuit 216 to selectively supply the card voltage V.sub.CC to the battery 202 to thus charge the battery 202 in accordance with the charging algorithm executed by the charge control circuit 208. When the transistor 214 is biased into its conductive state, the charge signal is provided through the resistor R1 to the battery 202.
When switch control circuit 216 receives a signal V.sub.DISCHARGE on input port 216h, switch control circuit 216 biases the transistor 222 into its conductive state. In its conductive state, transistor 222 provides the discharge signal path between battery terminal 202a and ground through the termination network 223.
Battery circuit 200 further includes the temperature monitor circuit 224 coupled to the charging circuit 204 at terminal 204d. The temperature monitor circuit 224 provides an output signal which indicates whether the monitored temperature is outside of the prescribed temperature limits. Temperature monitor circuit 224 provides at output port 224c, an output signal indicative of whether the battery temperature is within a predefined range. Temperature monitor circuit 224 includes a temperature sensor 226 which provides at an output port 226a an output signal having a voltage amplitude proportional to the ambient temperature at temperature sensor 226. In some embodiments it may be preferable to place sensor 226 in direct contact with battery 202.
Output port (op amp) 226a is coupled to a first input port of a first operational amplifier 228 which may for example, be provided as an LM 358A. A second input port of op amp 228 is coupled to a first output port of a voltage reference circuit 230. Voltage reference circuit 230 provides a reference voltage V.sub.HI to the second input port of op amp 228.
As the ambient temperature in the vicinity of temperature sensor 226 rises, temperature sensor 226 provides at output port 226a a signal V.sub.TEMP having a voltage amplitude proportional to the ambient temperature at temperature sensor 226. When the temperature rises to a predetermined level such that the voltage V.sub.TEMP is greater than the reference voltage V.sub.HI op amp 228 provides a control signal to a temperature monitor port 204d of charging circuit 204 which is coupled to charge control terminal 208d. In response to the control signal from comparator 228 charging circuit 204 ceases to charge battery 202.
Temperature sensor output port 226a is also coupled to a first input port of a operational amplifier 232 which also may be provided as an LM 358A. A second input port of op amp 232 is coupled to a second output port of voltage reference circuit 230. Voltage reference circuit 230 provides a reference voltage V.sub.LO to the second input port of op amp 232. As the ambient temperature in the vicinity of temperature sensor 226 decreases, temperature sensor 226 provides at output port 226a the signal V.sub.TEMP. When the temperature decreases to a predetermined level such that the voltage V.sub.TEMP is lower than the reference voltage V.sub.LO, comparator 232 provides a control signal to temperature monitor port 204d of charging circuit 204 which is coupled to charge control terminal 208d. In response to the control signal from op amp 232 charging circuit 204 ceases to charge the battery 202.
Thus, temperature monitor circuit 224 prevents the charging circuit 204 from charging battery 202 when the ambient temperature in the vicinity of temperature sensor 226 is above or below the predetermined thresholds. Thus, it is desirable to place temperature sensor 226 in physical proximity to the battery 202.
The charge control circuit 208 thus monitors the signal provided from temperature monitor circuit 224 and in response to a signal fed thereto from the temperature circuit 224, places the V.sub.CHARGE and V.sub.DISCHARGE at logic level zero which thereby causes switch control circuit 216 to turn off transistors 214 and 222.
If charging circuit 204 senses an error while in a charging mode, charge control circuit 208 provides a signal V.sub.ERROR to an indicator circuit 234 which includes a light emitting diode 236 and a pair of resistors 238, 240 coupled as shown. Error signal V.sub.ERROR is also provided to an input port of a status indicator circuit 242.
Indicator circuit 234 also includes an LED 236' and a pair of resistors 238', 240'. LED 236' receives a signal V.sub.MODE from charge control circuit 208. In response to the V.sub.MODE signal LED 236' blinks to indicate that charging circuit 204 is providing a charge current to the battery 202. The V.sub.MODE signal may, for example, cause LED 236' to blink at a particular rate to indicate the operating mode of the charge control circuit 208. If the charge control circuit 208 operates in its maintenance mode, then LED 236' may blink at a rate of once per second. Thus signal V.sub.MODE indicates whether charge control circuit 208 is operating in one of its normal charge modes or in its maintenance mode. Thus, LEDs 236, 236' provide a visual indication of whether or not a problem exists with the battery based on the voltage input or if the temperature goes outside a predetermined temperature range.
Status circuit 242 includes a plurality of resistors 244-252 each having a first terminal coupled to system supply voltage V.sub.CC and a second terminal coupled to an input port of a buffer circuit 254. The second terminals of resistors 244 and 246 are coupled to ground through series resistors 250 and 252 respectively. The resistance values of each of resistors 244-252 is selected such that signals ID.sub.0, ID.sub.1, and ID.sub.2 provided on output ports 254d-254f of buffer circuit 254 have values which indicate the amount of non-volatile RAM coupled to battery circuit 200.
For example, if the memory array includes 2 MB of non-volatile RAM, signals ID.sub.0 -ID.sub.2 take on a first set of values. If the memory array includes 4 MB of RAM signals ID0-ID2 take on a second different set of values. Similarly, signals ID0-ID2 take on a third distinct set of values to indicate an error in battery circuit 200 or in the memory array. Thus, battery circuit 200 provides a three bit identification code to sub-system controller 12 (FIG. 1). The code identifies memory module characteristics including but not limited to the module capacity and an error status.
Battery Circuit Operation
The battery circuit 200 operates in the following manner. Assume at a time T=0 power is applied to the battery charge circuit 200. Voltage detection circuit 206, switch control circuit 216 and transistors 212, 214 are directly coupled to the system voltage V.sub.SIMM.sbsb.--.sub.VCC. Thus upon initial power up, circuits 206 and 216 receive system voltage V.sub.SIMM.sbsb.--.sub.VCC and become operable, however, the remaining active circuit components on the card 200 have not yet received power. Battery 202 provides the battery voltage V.sub.BATT at terminal 202a.
Upon initial power up, the transistor 214 is in its unbiased state and thus prevents the voltage V.sub.BATT from reaching the node 213. Transistor 205 is in its conductive state to thus couple the battery voltage V.sub.BATT to the PSRAMs.
Detection circuit 206 determines whether or not the system voltage V.sub.SIMM.sbsb.--.sub.VCC is at the proper level to power up the memory array and those circuit components of battery circuit 200 which do not yet have a voltage signal provided thereto. If the system voltage V.sub.SIMM.sbsb.--.sub.VCC fails to reach the predetermined threshold voltage then voltage detection circuit 206 prevents the system voltage V.sub.SIMM.sbsb.--.sub.VCC from being coupled to the memory array or to any other circuit components of battery circuit 200 by continuing to assert the V.sub.RESET signal. If the system voltage V.sub.SIMM.sbsb.--.sub.VCC reaches the predetermined voltage level, detection circuit 206 de-asserts the reset signal V.sub.RESET to input terminal 216f of the switch control circuit 216 and to the gate electrode 205c of transistor 205. Transistor 205 thus decouples the battery 202 from the memory array.
When switch control circuit 216 receives the de-asserted V.sub.RESET signal, switching control circuit 216 provides a bias signal to the gate terminals of transistor 210 to bias the transistor 210 into its conductive state. When biased into its conductive state, transistor 210 couples the system voltage V.sub.SIMM.sbsb.--.sub.VCC to the PSRAMs coupled to transistor terminal 210b.
Similarly, in response to the de-asserted V.sub.RESET signal, switch control circuit 216 also provides a bias voltage to the gate terminal of transistor 212 and biases the transistor 212 into its conductive state. In its conductive state transistor 212 couples the system voltage V.sub.SIMM.sbsb.--.sub.VCC to node 213 to thus provide the card voltage V.sub.CC at the node 213. Thus, transistor 212 allows the card voltage V.sub.CC to be provided to the remaining active circuit components on the battery circuit 200. For example, the card voltage V.sub.CC is provided to the temperature monitoring circuit 224 at terminals 224a, 224b; to the buffer circuit 242; and to the charging circuit 204 at terminals 204e, 204f.
Thus when system voltage V.sub.SIMM.sbsb.--.sub.VCC is first supplied to the battery circuit 200, the voltage V.sub.SIMM.sbsb.--.sub.VCC rises to a predetermined threshold voltage which may be 5 volts, for example. Circuit components 206 and 216 and transistors 210, 212 each have the system voltage V.sub.SIMM.sbsb.--.sub.VCC provided thereto while the remainder of the circuit components on the battery circuit 200 do not receive any voltage.
Based on the voltage level of the system voltage V.sub.SIMM.sbsb.--.sub.VCC provided to the voltage detection circuit 206, the remaining circuit components of the battery circuit 200 will either receive a voltage or not. If the system voltage V.sub.SIMM.sbsb.--.sub.VCC provided to the battery circuit 200 does not reach the proper level for at least a predetermined period time, the battery 202 will remain coupled to the memory array through the transistor 205 and the remaining circuit components of the battery circuit 200 will not have a voltage applied thereto.
Assuming the voltage V.sub.SIMM.sbsb.--.sub.VCC rises to the predetermined voltage level, the card voltage V.sub.CC is provided to the remaining circuit components of the battery circuit 200, the voltage V.sub.RAM.sbsb.--.sub.VCC is coupled to the memory array through the transistor 210 and the battery 202 is de-coupled from the memory array.
The charge reset input terminal 208c of the charge control circuit 208 monitors the voltage V.sub.CC as modified by the reset circuit formed by capacitor C2 and diode D2. Thus, as system voltage is provided to the battery circuit 200, voltage is provided to the charge control circuit 208 based on a time constant of the reset circuit.
Upon initial application of the system voltage V.sub.SIMM.sbsb.--.sub.VCC, the voltage V.sub.SIMM.sbsb.--.sub.VCC has a rising voltage characteristic which reaches a predetermined level at time T.sub.1. Since the card voltage V.sub.CC is switched through the transistor 212 the card voltage V.sub.CC rises to a predetermined voltage level with a characteristic similar to a step function characteristic at a time T.sub.2 =T.sub.1 +t.sub.1
Capacitor C2 is selected having a relatively large capacitance value which may typically be about one microfarad, for example, and thus there is some period of time T.sub.3 =T.sub.2 +t.sub.2 when the signal on the charge reset terminal 208c of the charge control circuit 208 is at a logic low and the voltage V.sub.CC is at a logic high. In this condition, the charge control circuit 208 is in a reset mode. Thus upon initial power up of the battery circuit 200 the charge control circuit 208 initially enters a reset mode.
The diode D2 is provided as part of the reset circuit such that when the voltage V.sub.CC is removed, the capacitor C2 rapidly discharges through the diode D2. Thus, the charge control circuit 208 reset time is based on the capacitance value of the capacitor C2.
The charge control circuit 208 next examines the level of the battery voltage V.sub.BATT. At this time transistor 205 is turned off because V.sub.RESET is a logic high signal and, in the present embodiment, transistor 205 is provided as a PFET. Transistors 210 and 212 are on, transistor 214 is off and transistor 222 is off. Thus, the charge control circuit 208 examines the battery voltage V.sub.BATT through the voltage divider resistors R3, R4 and based on the voltage level of the battery voltage the charge control circuit 208 determines whether or not to enter a charge mode.
Thus the charge control circuit 208 monitors the battery voltage and, via the internal clock of the charge control circuit 208, at a predetermined period of time, the charge control circuit 208 charges and discharges the battery 202 as described herein above.
Having described preferred embodiments of the invention, it will be apparent to those of ordinary skill in the art that other embodiments incorporating the inventive concepts may be employed. Accordingly, these embodiments should be viewed as exemplary and the invention should be limited only by the scope and spirit of the appended claims.

Number	Name	Date
3980935	Worst	Sep 1976
4656605	Clayton	Apr 1987
4727513	Clayton	Feb 1988
4850892	Clayton et al.	Jul 1989
4882700	Mauritz et al.	Nov 1989
4908793	Yamagata et al.	Mar 1990
4984211	Tran	Jan 1991
4992849	Corbett et al.	Feb 1991
4992850	Corbett et al.	Feb 1991
5051994	Bluethman et al.	Sep 1991
5070450	Holman, Jr. et al.	Dec 1991
5072450	Helm et al.	Dec 1991
5089993	Neal et al.	Feb 1992
5103247	Sugano et al.	Apr 1992
5138434	Wood et al.	Aug 1992
5148546	Blodgett	Sep 1992
5162979	Anzelone et al.	Nov 1992
5164916	Wu et al.	Nov 1992
5189598	Bolan et al.	Feb 1993
5191657	Ludwig et al.	Mar 1993
5198965	Curtis et al.	Mar 1993
5204840	Mazur	Apr 1993
5321663	Nishi	Jun 1994
5359569	Fujita et al.	Oct 1994
5373478	Komatsu et al.	Dec 1994

Number	Date	Country
4-259982	Sep 1992	JPX
1439333	Jun 1976	GBX
1557684	Dec 1979	GBX

Non-volatile memory module

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CPC

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