Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices and data servers. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory), Electrically Erasable Programmable Read-Only Memory (EEPROM), and others.
When a memory system is deployed in or connected to an electronic device (the host), the memory system can be used to store data and read data. It is important that once data is stored in a memory system, the data can be read back. Therefore, some memory systems will encode the data prior to storing using error correction codes. Subsequently, when reading the data, the memory system will decode the data and (hopefully) correct any errors found. If the number of errors is within the capabilities of the error correction codes, then the memory system will decode the data and return the data error free to the host. If the number of errors is beyond the capabilities of the error correction codes, then the memory system will report an error message to the host without returning any data to the host.
Like-numbered elements refer to common components in the different figures.
There are some applications that do not require 100% error free data. For example, with photographs, video streaming and audio streaming, a small number of errors may be tolerated and even preferred as compared to completely failing to provide the data. Therefore, it is proposed to provide a non-volatile memory system that can be configured to return data that is “error reduced” rather than “error free” for applications that do not necessarily need error free data. For example, the host (or other entity external to the memory system) sends one or more commands to the memory system to read data (the “target read data”). In response to the commands, the memory system performs one or more read operations and returns multiple copies of the target read data to the host (or other entity external to the memory system), with the multiple copies returned over time progressively getting better (e.g., later in time returned results have lower number of errors than earlier returned results). Thus, the host receives multiple copies of the target read data, with different numbers of errors between the copies of target read data (or different reliability scores between the target read data). The host can wait until the data is good enough, and then abort the remainder of the read process or ignore subsequently provided copies of the target read data (subsequent results). In this manner, the host only needs to wait until the quality of the data is good enough and does not need to wait unnecessarily for better data than it needs. In some instances, the host will be better able to correct errors in the provided data using an error correction process with multiple copies of the data having different error rates.
One embodiment of a non-volatile storage apparatus that implements the proposed technology comprises non-volatile memory and one or more control circuits connected to the non-volatile memory. The one or more control circuits are configured to program to and read from the non-volatile memory. The one or more control circuits are configured to report multiple copies of data read in response to receiving one or more read commands, with each reported copy of the data read having a different number of errors.
In one embodiment, non-volatile memory 104 comprises a plurality of memory packages. Each memory package includes one or more memory die. Therefore, Controller 102 is connected to one or more non-volatile memory die. In one embodiment, each memory die in the memory packages 14 utilize NAND flash memory (including two dimensional NAND flash memory and/or three dimensional NAND flash memory). In other embodiments, the memory package can include other types of memory.
Controller 102 communicates with host 120 via an interface 130 that implements NVM Express (NVMe) over PCI Express (PCIe). For working with memory system 100, host 120 includes a host processor 122, host memory 124, and a PCIe interface 126. Host memory 124 is the host's physical memory, and can be DRAM, SRAM, non-volatile memory or another type of storage. Host 120 is external to and separate from memory system 100. In one embodiment, memory system 100 is embedded in host 120.
Control circuitry 310 cooperates with the read/write circuits 328 to perform memory operations (e.g., write, read, and others) on memory structure 326, and includes a state machine 312, an on-chip address decoder 314, a power control circuit 316 and a temperature detection circuit 318. State machine 312 provides die-level control of memory operations. In one embodiment, state machine 312 is programmable by software. In other embodiments, state machine 312 does not use software and is completely implemented in hardware (e.g., electrical circuits). In another embodiment, state machine 312 is replaced by a micro-controller. In one embodiment, control circuitry 310 includes buffers such as registers, ROM fuses and other storage devices for storing default values such as base voltages and other parameters.
The on-chip address decoder 314 provides an address interface between addresses used by Controller 102 to the hardware address used by the decoders 324 and 332. Power control module 316 controls the power and voltages supplied to the word lines and bit lines during memory operations. Power control module 316 may include charge pumps for creating voltages. The sense blocks include bit line drivers.
For purposes of this document, the phrase “one or more control circuits” refers to a controller, a state machine, a micro-controller and/or control circuitry 310, or other analogous circuits that are used to control non-volatile memory.
In one embodiment, memory structure 326 comprises a three dimensional memory array of non-volatile memory cells in which multiple memory levels are formed above a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory that are monolithically formed in one or more physical levels of memory cells having an active area disposed above a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material such as described, for example, in U.S. Pat. No. 9,721,662, incorporated herein by reference in its entirety.
In another embodiment, memory structure 326 comprises a two dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates such as described, for example, in U.S. Pat. No. 9,082,502, incorporated herein by reference in its entirety. Other types of memory cells (e.g., NOR-type flash memory) can also be used.
The exact type of memory array architecture or memory cell included in memory structure 326 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 326. No particular non-volatile memory technology is required for purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of the memory structure 326 include ReRAM memories, magnetoresistive memory (e.g., MRAM, Spin Transfer Torque MRAM, Spin Orbit Torque MRAM), phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architectures of the memory structure 126 include two dimensional arrays, three dimensional arrays, cross-point arrays, stacked two dimensional arrays, vertical bit line arrays, and the like.
One example of a ReRAM, or PCMRAM, cross point memory includes reversible resistance-switching elements arranged in cross point arrays accessed by X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes. As temperature increases, the mobility of the ions also increases causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element may have a wide range of programming thresholds over temperature.
Magnetoresistive memory (MRAM) stores data by magnetic storage elements. The elements are formed from two ferromagnetic plates, each of which can hold a magnetization, separated by a thin insulating layer. One of the two plates is a permanent magnet set to a particular polarity; the other plate's magnetization can be changed to match that of an external field to store memory. A memory device is built from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current is passed through them, an induced magnetic field is created.
Phase change memory (PCM) exploits the unique behavior of chalcogenide glass. One embodiment uses a GeTe—Sb2Te3 super lattice to achieve non-thermal phase changes by simply changing the co-ordination state of the Germanium atoms with a laser pulse (or light pulse from another source). Therefore, the doses of programming are laser pulses. The memory cells can be inhibited by blocking the memory cells from receiving the light. Note that the use of “pulse” in this document does not require a square pulse, but includes a (continuous or non-continuous) vibration or burst of sound, current, voltage light, or other wave.
A person of ordinary skill in the art will recognize that the technology described herein is not limited to a single specific memory structure, but covers many relevant memory structures within the spirit and scope of the technology as described herein and as understood by one of ordinary skill in the art.
As discussed above, in one embodiment the interface 130 between the memory system 100 and the host 120 is NVMe over PCIe. NVMe is an interface that allows host software to communicate with a non-volatile memory system. This interface is optimized for Enterprise and Client solid state drives, typically attached as a register level interface to the PCIe interface. The register interface and command set are specified apart from any usage model for the non-volatile memory system, but rather only specifies the communication interface to the non-volatile memory system. Thus, this specification does not specify whether the non-volatile memory system is used as a solid state drive, a main memory, a cache memory, a backup memory, a redundant memory, etc. (any of which can be implemented for system 100).
The NVMe interface provides submission and completion queues that are used for the host to submit commands and the memory system to provide an indication of the outcome from executing the submitted commands. An NVMe command (e.g. Read or Write) is initiated at the host and to a particular submission queue that lives in host memory. Once the command is inserted into a queue, the host writes to a per-queue doorbell register on the controller. This doorbell write wakes up the controller, which then probes the queue for the new request(s). The controller reads the queue entry, executes the command, appends a completion into a completion queue and notifies the host of this via an interrupt. The host wakes up, pops that completion off the queue and returns results to the user.
There are two main types of queues that are used: Administrative Queues and I/O Queues. Administrative Queues are used for configuring and managing various aspects of the controller. There is only one pair of Administrative queues per controller. I/O Queues are used to move NVMe protocol specific commands (e.g. Read, Write). There can be up to 64K I/O queues per controller. In some embodiments, there is one pair of I/O queues per processor core; however, processor cores can have more than on pair of I/O queues and/or the number of I/O queues can be unrelated to the number of processor cores. Each queue pair includes a submission queue and a completion queue. In some embodiments, all of the queues reside in host memory.
A submission queue (SQ) is a circular buffer with a fixed slot size that the host software uses to submit commands for execution by the controller. Each submission queue entry is a command. Commands are 64 bytes in size.
A completion queue (CQ) is a circular buffer with a fixed slot size used to post status for completed commands. A completed command is uniquely identified by a combination of the associated SQ identifier and command identifier that is assigned by host software. Multiple submission queues may be associated with a single completion queue. This feature may be used where a single worker thread processes all command completions via one completion queue even when those commands originated from multiple submission queues. A Phase Tag (P) bit in each completion queue entry indicates whether the entry has been newly posted. This enables host software to determine whether the new entry was posted as part of the previous or current round of completion notifications. After reading and processing a completion queue entry, the controller inverts the Phase Tag bit for that entry.
Each of submission queues and completion queues have both head pointers and tail pointers. The tail pointer points to the next available entry to add an entry into the queue. After the producer adds an entry to a queue, the producer increments the tail pointer (taking into consideration that once it gets to the end of the queue, it will wrap back to zero—they are all circular queues.) The queue is considered empty if the head and tail pointers are equal. The consumer uses the head pointer to determine where to start reading from the queue, after examining the tail pointer and determining that the queue is non-empty. The consumer will increment the head pointer after reading the each entry.
The submission queue's tail pointer is managed by the host. After one or more entries have been pushed into the queue, the tail pointer (that was incremented) is written to the controller via a submission queue doorbell register residing on the controller. The controller maintains the head pointer and begins to read the queue once notified of the tail pointer update. It can continue to read the queue until empty. As it consumes entries, the head pointer is updated, and sent back to the host via completion queue entries.
The completion queue's tail is managed by the controller, but unlike the host, the controller only maintains a private copy of the tail pointer. The only indication that there is a new completion queue entry is the Phase Tag bit in the completion queue entry that can be polled. Once the host determines an entry is available, it will read that entry and update the head pointer. The controller is notified of head pointer updates by host writes to the completion queue doorbell register.
Note that all work done by an NVMe controller is either pulled into or pushed out of that controller by the controller itself. The host merely places work into host memory and rings the doorbell (“you've got a submission entry to handle”). Later it collects results from the completion queue, again ringing the doorbell (“I'm done with these completion entries”). So the controller is free to work in parallel with the host. There is no requirement for ordering of completions—the controller can order it's work anyway it chooses.
Queue Pointers 446 include the head and tail pointers for the various sets of queues discussed above. In one embodiment, Controller 102 maintains a copy of the head and tail pointer for each queue. In the example of
Bytes 04-07 of the completion queue entry include a SQ Identifier, which includes 16 bits used to indicate the submission queue to which the associated command was issued. This field is used by host software when more than one submission queue shares a single completion queue to uniquely determine the command completion in combination with the command identifier (CID). The SQ Head Pointer includes 16 bits used to indicate the current submission queue head pointer for the submission queue indicated in the SQ Identifier field. This is used to indicate to the host the submissions queue entries that have been consumed and may be reused for new entries. Bytes 08-11 are reserved. Bytes 12-15 are command specific. If a command uses this double word, then the definition of this double word is contained within the associated command definition. If the command does not use this double word, then the field is reserved. In one embodiment, the tables of
In step 558, after executing the command, controller 102 writes the results to the appropriate completion queue based on the Completion Queue Tail Pointer which only resides on the controller 102. In this example, controller 102 uses Completion Queue Tail Pointer CQTP0 to write in the completion queue (C) for Core 0. The Completion Queue entry added in step 558 includes the updated Submission Queue Head Pointer (SQHP0). In step 560, the Completion Queue Tail Pointer (CQTP0) is incremented. In step 562, controller 102 generates an interrupt on Host 120. The interrupt identifies the appropriate Completion Queue that has been updated. In step 564, in response to the interrupt, Host 120 checks the appropriate Completion Queue at the entry pointed to by the Completion Queue Head Pointer. In step 566, host 120 processes the Completion Queue entry. In step 568, Host 120 updates the Completion Queue Head Pointer (CQHP0). In step 570, Host 120 writes the updated Completion Queue Head Pointer (CQHP0) to the Completion Queue Head Doorbell on the controller (CQHDB0). As long as there are commands in the Active Command Buffer 442, steps 554-570 will continuously be performed. Each time the host writes a command to Submission Queue steps 540-552 will be performed.
Memory system 100 uses Error Correction Codes (ECC) to protect data from corruption. Many ECC coding schemes are well known in the art. These conventional error correction codes are especially useful in large scale memories, including flash (and other non-volatile) memories, because of the substantial impact on manufacturing yield and device reliability that such coding schemes can provide, rendering devices that have a few non-programmable or defective cells as useable. Of course, a tradeoff exists between the yield savings and the cost of providing additional memory cells to store the code bits. As such, some ECC codes are better suited for flash memory devices than others. Generally, ECC codes for flash memory devices tend to have higher code rates (i.e., a lower ratio of code bits to data bits) than the codes used in data communications applications (which may have code rates as low as 1/2). Examples of well-known ECC codes commonly used in connection with flash memory storage include Reed-Solomon codes, other BCH codes, Hamming codes, and the like. Sometimes, the error correction codes used in connection with flash memory storage are “systematic,” in that the data portion of the eventual code word is unchanged from the actual data being encoded, with the code or parity bits appended to the data bits to form the complete code word.
The particular read parameters for a given error correction code include the type of code, the size of the block of actual data from which the code word is derived, and the overall length of the code word after encoding. For example, a typical BCH code applied to a sector of 512 bytes (4096 bits) of data can correct up to four error bits, if at least 60 ECC or parity bits are used. Reed-Solomon codes are a subset of BCH codes, and are also commonly used for error correction. For example, a typical Reed-Solomon code can correct up to four errors in a 512 byte sector of data, using about 72 ECC bits. In the flash memory context, error correction coding provides substantial improvement in manufacturing yield, as well as in the reliability of the flash memory over time.
In some embodiments, controller 102 receives host data, also referred to as information bits, that is to be stored in memory cells of non-volatile three dimensional memory structure 126. The informational bits are represented by the matrix i=[1 0] (note that two bits are used for example purposes only, and many embodiments have code words longer than two bits). An error correction coding process (such as any of the processes mentioned above or below) is implemented in which parity bits are added to the informational bits to provide data represented by the matrix or code word v=[1 0 1 0], indicating that two parity bits have been appended to the data bits. Other techniques can be used that map input data to output data in more complex manners. For example, low density parity check (LDPC) codes, also referred to as Gallager codes, can be used. More details about LDPC codes can be found in R. G. Gallager, “Low-density parity-check codes,” IRE Trans. Inform. Theory, vol. IT-8, pp. 21 28, January 1962; and D. MacKay, Information Theory, Inference and Learning Algorithms, Cambridge University Press 2003, chapter 47. In practice, such LDPC codes are typically applied to multiple pages encoded across a number of storage elements, but they do not need to be applied across multiple pages. The data bits can be mapped to a logical page and stored in non-volatile three dimensional memory structure by programming one or more memory cells to one or more data states, which corresponds to v.
When reading data that has been encoded by error correction codes, the code words v read from the memory cells need to be decoded back to the original data i. In one possible implementation, an iterative probabilistic decoding process is used which implements error correction decoding corresponding to the encoding implemented in the Controller 122. Further details regarding iterative probabilistic decoding can be found in the above-mentioned D. MacKay text. The iterative probabilistic decoding attempts to decode a code word read from the memory by assigning initial probability metrics to each bit in the code word. The probability metrics indicate a reliability of each bit, that is, how likely it is that the bit is not in error. In one approach, the probability metrics are logarithmic likelihood ratios (LLRs) which are obtained from LLR tables. LLR values are measures of the reliability with which the values of various binary bits read from the storage elements are known.
The LLR for a bit is given by
where P(v=0|Y) is the probability that a bit is a 0 given the condition that the state read is Y, and P(v=1|Y) is the probability that a bit is a 1 given the condition that the state read is Y. Thus, an LLR>0 indicates a bit is more likely a 0 than a 1, while an LLR<0 indicates a bit is more likely a 1 than a 0, to meet one or more parity checks of the error correction code. Further, a greater magnitude indicates a greater probability or reliability. Thus, a bit with an LLR=63 is more likely to be a 0 than a bit with an LLR=5, and a bit with an LLR=−63 is more likely to be a 1 than a bit with an LLR=−5. LLR=0 indicates the bit is equally likely to be a 0 or a 1.
An LLR value can be provided for each of the bit positions in a code word. Further, the LLR tables can account for the multiple read results so that an LLR of greater magnitude is used when the bit value is consistent in the different code words.
Controller 102 receives the code word Y1 and the LLRs and iterates in successive iterations in which it determines if parity checks of the error encoding process have been satisfied. If all parity checks have been satisfied, the decoding process has converged and the code word has been successfully error corrected. If one or more parity checks have not been satisfied, the decoder will adjust the LLRs of one or more of the bits which are inconsistent with a parity check and then reapply the parity check or next check in the process to determine if it has been satisfied. For example, the magnitude and/or polarity of the LLRs can be adjusted. If the parity check in question is still not satisfied, the LLR can be adjusted again in another iteration. Adjusting the LLRs can result in flipping a bit (e.g., from 0 to 1 or from 1 to 0) in some, but not all, cases. The flipping of bits can be thought of as correcting a bit or correcting an error in the data sensed from the memory cells. In one embodiment, another parity check is applied to the code word, if applicable, once the parity check in question has been satisfied. In others, the process moves to the next parity check, looping back to the failed check at a later time. The process continues in an attempt to satisfy all parity checks. Thus, the decoding process of Y1 is completed to obtain the decoded information including parity bits v and the decoded information bits i.
It is hoped that the above-described decoding process results in all parity checks being satisfied, meaning that the decoding process converged on error free data, which is then returned to the host.
It is possible that the code words sensed from the memory cells have too many errors for the ECC process (performed by ECC engine 226) to correct. In that case, the data is deemed uncorrectable and an error message (without the data) is returned to the host.
There are some applications that do not require 100% error free data. For example, with photographs, video streaming and audio streaming, a small number of errors may be tolerated. Sometimes a small number of errors is preferred as compared to completely failing to provide the data. Therefore, it is proposed to provide a non-volatile memory system that can be configured to return data that is “error reduced” rather than “error free” for applications that do not necessarily need error free data. By allowing the memory to return data with some errors the data will be provided to the host much quicker. Therefore, in response to one or more host read commands, the memory system returns multiple copies of the data over time, with the returned data progressively getting better so that later in time copies of the data have lower number of errors. The host decides when the error rate is good enough and stops the process (or ignores the rest of the results).
As discussed above, host 120 sends one or more commands to read data from non-volatile memory 104. If the host 120 sends multiple commands to read the data, each of the commands is to read the same data. See
In step 584 of
The host receives multiple copies of the target read data, with different numbers of errors between the copies of target read data (or different reliability scores between the target read data). The host can wait until the data is good enough, and then abort the remainder of the read process or ignore subsequently provided copies of the target read data (subsequent results). In this manner, the host only needs to wait until the quality of data is good enough and does not need to wait unnecessarily for better data than it needs. Additionally, the host will be better able to correct errors in the provided data using an error correction process with multiple copies of the data.
In one embodiment, the process of
In step 602 of
In step 608 of
In step 618, controller 102 accesses the next result, of the multiple results generated in step 606. Note that the multiple results generated in step 606 can be generated over time. In step 620, controller 102 determines whether to continue the process. That is, controller 102 determines whether to send another copy of the target read data. More details of step 620 are provided below. If the controller 102 determines not to send any more copies of the target read data, then in step 622, controller 102 ends the processing of the read command received in step 602. If controller 102 determines to send more copies of the target read data than in step 624 controller 102 appends an indication of reliability to the current result being worked on (and accessed in the previous iteration of step 618).
In step 626, the controller 102 stores the result in the read buffer. Storing the result in the read buffer in step 626 can include appending the additional result to the end of the buffer or overriding the data that is already in the buffer. In one embodiment, the buffer is in host memory as discussed above. In another embodiment, the buffer storing the results from step 626 can include the Host Memory Buffer which is a portion of host memory that can be allocated (upon request from controller 102) to be used by controller 102. In another embodiment, the results stored in step 626 are saved into the Controller Memory Buffer (CMB), which is a region of general purpose read/write memory on the controller (e.g. DRAM 106) that may be used for a variety of purposes. The controller indicates which purposes the memory may be used by setting support flags in a configuration register. Hosts can then use the CMB to store any of the queues or read buffers discussed herein. In one embodiment the one or more control circuits described herein are configured to report the multiple copies of data read by storing the multiple copies of data in the CMB within the memory system and behind the host interface from a perspective of the memory system. The phrase behind the host interface from a perspective in the memory system refers to being inside memory system 100 such that access by the host can only be made through the PCIe interface 150 of
In step 702 of
While the process of
In step 730 of
The process of
When the host sends a read command to the controller 102, that read command can include an indication of the maximum number of results (copies of read data) that can be reported. That maximum number is used by the process of
While the process of
In step 882 of
In step 902 of
In step 904, controller 102 reads data from one or more memory die. In step 906, controller 102 generates multiple results. Steps 904 and 906 correspond to step 554 of
In step 908 of
In step 918, the counter is incremented (n=n+1). In step 920, controller 102 accesses the result for command n. In step 922, controller 102 determines whether to continue with the read operation. That is, controller 102 determines whether to continue or not continue to provide additional results based on any of the processes of
As explained above with respect to
The above discussion describes a non-volatile memory system that returns data which is “error reduced.” By allowing the memory to return data with some errors the data will be provided to the host much quicker. Therefore, in response to one or more host read commands, the memory system returns multiple copies of the data over time, progressively getting better so that later in time reported copies of the data have lower number of errors than earlier in time reported copies of the data. The host decides when the error rate is good enough and stops the process (or ignores the rest of the results). In this manner, the host only needs to wait until the quality of the data is good enough and does not need to wait unnecessarily for better data than it needs. Additionally, the host will be better able to correct errors in the provided data using an error correction process with multiple copies of the data.
One embodiment includes a non-volatile memory apparatus comprising non-volatile memory and one or more control circuits in communication with the non-volatile memory. The one or more control circuits are configured to read from the non-volatile memory. The one or more control circuits are configured to report multiple copies of the same data read in response to receiving one or more read commands with each reported copy of the data read having a different number of errors.
One embodiment includes an apparatus comprising a memory interface configured to connect with non-volatile memory, a host interface configured to connect to a host and one or more processors connected to the memory interface and the host interface. The one or more processors configured to receive a read command from a host. The one or more processors are configured to generate and send multiple read instructions to the non-volatile memory via the memory interface in response to the read command. The one or more processors are configured to generate multiple copies of a same read data with corresponding indications of reliability based on raw data received from the non-volatile memory in response to the multiple read instructions. The one or more processors are configured to report the multiple copies of the same read data and corresponding indications of reliability to the host.
One embodiment includes a method of reading data from a non-volatile memory system, comprising: receiving multiple commands to read a same target read data, the multiple commands are received from a single entity; generating multiple copies of the target read data, each copy of the multiple copies of the target read data intentionally has different number of errors than other copies of the multiple copies of the target read data, each copy of the multiple copies of the target read data associated with one of the received multiple commands; and reporting the multiple copies of the target read data back to the single entity.
One embodiment includes a non-volatile memory apparatus comprising a plurality of non-volatile memory cells and means for reading from the memory cells and sequentially reporting multiple copies of data read over time in response to receiving one or more read commands with each reported copy of the data read progressively having a smaller number of errors. For example, the non-volatile memory apparatus may be a solid state drive that includes a controller connected to a memory die. The memory die includes the plurality of non-volatile memory cells, as well as various control circuitry. The controller includes the means for reading from the memory cells and sequentially reporting multiple copies of data read.
In one embodiment, the means for reading from the memory cells and sequentially reporting multiple copies of data read comprises software running on a processor, such as Multi-Read Engine 438 performing the processes of
For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to describe different embodiments or the same embodiment.
For purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more others parts). In some cases, when an element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intervening elements. When an element is referred to as being directly connected to another element, then there are no intervening elements between the element and the other element. Two devices are “in communication” if they are directly or indirectly connected so that they can communicate electronic signals between them.
For purposes of this document, the term “based on” may be read as “based at least in part on.”
For purposes of this document, without additional context, use of numerical terms such as a “first” object, a “second” object, and a “third” object may not imply an ordering of objects, but may instead be used for identification purposes to identify different objects.
For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.
The foregoing detailed description has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the proposed technology and its practical application, to thereby enable others skilled in the art to best utilize it in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope be defined by the claims appended hereto.
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Number | Date | Country | |
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20190294344 A1 | Sep 2019 | US |